JPH05333372A - Tft liquid crystal display device and its production - Google Patents

Tft liquid crystal display device and its production

Info

Publication number
JPH05333372A
JPH05333372A JP13834692A JP13834692A JPH05333372A JP H05333372 A JPH05333372 A JP H05333372A JP 13834692 A JP13834692 A JP 13834692A JP 13834692 A JP13834692 A JP 13834692A JP H05333372 A JPH05333372 A JP H05333372A
Authority
JP
Japan
Prior art keywords
gate bus
bus electrodes
electrode
electrodes
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13834692A
Other languages
Japanese (ja)
Inventor
Jun Kuwata
純 桑田
Mutsumi Yamamoto
睦 山本
Tomizo Matsuoka
富造 松岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13834692A priority Critical patent/JPH05333372A/en
Publication of JPH05333372A publication Critical patent/JPH05333372A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To obviate the generation of a short circuit at the intersected parts of gate bus electrodes and source bus electrodes and to expand a picture element electrode area by forming ruggedness in the prescribed parts on a light transparent insulating substrate and forming the gate bus electrodes on the substrate formed with the ruggedness. CONSTITUTION:The striped rugged parts 9 are formed on the surface of the light transparent insulating substrate 1. The gate bus electrodes 2 and the gate electrodes 2a are formed thereon. An insulating film 3, a semiconductor layer and an ohomic contact layer are formed and are patterned to island shapes. The source bus electrodes 6 and drain electrodes are thereafter formed. The electric resistance is lowered and the high-speed responsiveness are assured without increasing the film thickness of the gate bus electrodes 2 by this constitution. In addition, the level differences at the pattern edges of the intersected parts of the gate bus electrodes 2 and the source bus electrodes 6 are smoothed and the electrical short circuit is hardly generated. Further, the area of the picture element electrodes is expanded.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、特にゲート電極,ゲー
トバス電極構造による特徴を有するTFT液晶表示装置
およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT liquid crystal display device having a characteristic of a gate electrode and a gate bus electrode structure and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、TFT液晶表示装置のゲート電極
にはAl,Cr,Ta等が、ソース,ドレイン電極に
は、Al,Ti,Mo等の金属導電膜が用いられてい
る。一方、コンピュータの端末機としてのTFT液晶表
示装置としては、高精細,高速応答,高視認性が要求さ
れており、特に画像のちらつきがない高輝度が要望され
ている。この要望に応えるためには、絵素面積を増やさ
なければならず、ゲート電極の線幅を狭くしかつ電極線
抵抗を下げなければならない。
2. Description of the Related Art Conventionally, a gate electrode of a TFT liquid crystal display device is made of Al, Cr, Ta or the like, and a source or drain electrode is made of a metal conductive film of Al, Ti, Mo or the like. On the other hand, a TFT liquid crystal display device as a terminal of a computer is required to have high definition, high speed response and high visibility, and in particular, high brightness without flicker of an image is required. In order to meet this demand, the pixel area must be increased, the line width of the gate electrode must be narrowed, and the electrode line resistance must be reduced.

【0003】従来技術で作成したTFT液晶表示装置の
面内配線パターン図を図7に、図7のA−A部断面図,
B−B断面図をそれぞれ図5,図6に示す。
FIG. 7 shows an in-plane wiring pattern diagram of a TFT liquid crystal display device prepared by a conventional technique, and FIG.
BB sectional views are shown in FIGS. 5 and 6, respectively.

【0004】図5,図6において、1は透光性絶縁性基
板、2はゲートバス電極、2aはゲート電極、3は絶縁
膜、4は半導体層、4aは半導体保護層、5はオーミッ
クコンタクト層、6はソースバス電極、7はドレイン電
極、8は絵素電極である。すなわちゲートバス電極2お
よびソースバス電極6は絶縁膜3を介して交差した構造
になっている。ゲートバス電極2の線幅を狭くすると同
一の電極線抵抗を確保するには金属導電膜の膜厚を厚く
するとパターンエッジが急峻になるためにゲートバス電
極2とソースバス電極6の交差部で電気的に短絡しやす
くなる。そこでゲートバス電極2の上の絶縁膜3として
は電極パターンの側面にも絶縁膜が形成される陽極酸化
膜や化学気相成長法で製膜された窒化珪素膜や酸化珪素
膜が用いられている。
In FIGS. 5 and 6, 1 is a translucent insulating substrate, 2 is a gate bus electrode, 2a is a gate electrode, 3 is an insulating film, 4 is a semiconductor layer, 4a is a semiconductor protective layer, and 5 is an ohmic contact. A layer, 6 is a source bus electrode, 7 is a drain electrode, and 8 is a pixel electrode. That is, the gate bus electrode 2 and the source bus electrode 6 have a structure intersecting with each other with the insulating film 3 interposed therebetween. If the line width of the gate bus electrode 2 is narrowed, the same electrode line resistance is ensured. If the film thickness of the metal conductive film is increased, the pattern edge becomes steeper. Therefore, at the intersection of the gate bus electrode 2 and the source bus electrode 6. It becomes easy to electrically short-circuit. Therefore, as the insulating film 3 on the gate bus electrode 2, an anodic oxide film in which an insulating film is formed on the side surface of the electrode pattern, a silicon nitride film or a silicon oxide film formed by a chemical vapor deposition method is used. There is.

【0005】[0005]

【発明が解決しようとする課題】このような従来の構成
では、ワーク・ステーションのような300万画素以上
の表示が必要な超高精細・高速応答カラー表示端末機を
従来技術を用いてTFT液晶表示装置を作るとゲートバ
ス電極線幅が狭くできずまた画像のちらつきを防ぐ補助
容量が大きくできなくなる。またさらには、ゲートバス
電極の線幅を狭くして膜厚を厚くするとソースバス電極
と交差した部分において対向電極とのギャップが局所的
に狭くなり、機械的強度が不足してこの交差部でのゲー
トバス電極とソースバス電極との電気的短絡が生じる確
率を増やすこととなる。
In such a conventional structure, an ultra-high-definition, high-speed response color display terminal, which requires a display of 3 million pixels or more, such as a work station, has been manufactured by using the conventional technology for TFT liquid crystal display. When a display device is manufactured, the width of the gate bus electrode line cannot be narrowed and the auxiliary capacitance that prevents image flicker cannot be increased. Furthermore, if the line width of the gate bus electrode is made narrower and the film thickness is made thicker, the gap between the source bus electrode and the counter electrode becomes narrower locally, and the mechanical strength becomes insufficient. The probability that an electrical short circuit will occur between the gate bus electrode and the source bus electrode will be increased.

【0006】本発明は上記課題を解決するもので、ゲー
トバス電極とソースバス電極との交差部で電気的短絡が
発生せず、絵素電極の面積を拡大したTFT液晶表示装
置を提供することを目的とする。
The present invention solves the above problems, and provides a TFT liquid crystal display device in which an electrical short circuit does not occur at the intersection of a gate bus electrode and a source bus electrode and the area of a pixel electrode is enlarged. With the goal.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明は、透光性絶縁基板上の所定部に凹凸を形成
し、その凹凸を形成した透光性絶縁基板上に少なくとも
ゲートバス電極を形成した構成よりなる。
In order to achieve the above-mentioned object, the present invention is to provide at least a gate bus on a translucent insulating substrate on which irregularities are formed in a predetermined portion on the translucent insulating substrate. It is composed of electrodes.

【0008】[0008]

【作用】上記構成により、ゲートバス電極の膜厚を厚く
することなく電極抵抗を低減し、高速応答性が確保で
き、しかも、ゲートバス電極およびソースバス電極との
交差部のパターンエッジでの段差を滑らかにし電気的短
絡が発生し難くなり、さらには、絵素電極の面積を拡大
できる。
With the above structure, the electrode resistance can be reduced without increasing the film thickness of the gate bus electrode, high-speed response can be ensured, and a step at the pattern edge at the intersection with the gate bus electrode and the source bus electrode can be ensured. And makes it difficult for an electrical short circuit to occur, and further, the area of the pixel electrode can be increased.

【0009】[0009]

【実施例】本発明の一実施例であるTFT液晶装置の従
来例の図5,図6および図7に対応する図を、図1,図
2および図3に示す。図1,図2において、従来例の図
5,図6と同一部分の説明は省略する。すなわち本発明
の特徴は図1に示すように透光性の絶縁性基板1の表面
に凹凸部9を設けていることである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1, 2 and 3 are views corresponding to FIGS. 5, 6 and 7 of a conventional example of a TFT liquid crystal device which is an embodiment of the present invention. 1 and 2, the description of the same parts as those of FIGS. 5 and 6 of the conventional example will be omitted. That is, a feature of the present invention is that the uneven portion 9 is provided on the surface of the translucent insulating substrate 1 as shown in FIG.

【0010】具体的な実施例について説明する。透光性
絶縁基板1として、コーニング社の7059ガラス基板
を用いた。ガラス基板表面に、ストライプ状の凹凸を形
成するためにドライエッチングを行った。その後にウェ
ットエッチングによりパターンエッジを滑らかにした。
つぎにそのストライプ状の凹凸部9を形成した透光性の
絶縁性基板1上にDCスパッタリング法により、ターゲ
ットはAlターゲット、スパッタガスにAr、ガス圧
0.3Paおよびスパッタ電力10W/cm2の条件でア
ルミニウム(Al)薄膜を200nmの膜厚で成膜し、
所定のパターンをウェットエッチング法により形成し、
ゲートバス電極2およびゲート電極2aとした。そし
て、絶縁膜3とし、プラズマCVD法により絶縁性基板
1の温度が350℃で、窒化シリコン膜を400nm、
半導体層4としてのa−Si膜100nmと半導体保護
層4aとして窒化シリコン膜を100nmで連続的に製
膜した。そして、半導体保護層4aを所定のパターンに
加工した。オーミックコンタクト層5としてn+型a−
Si膜を30nmの厚みに製膜した後、半導体層4と同
時に島状にパターン形成した。その後、ゲートバス電極
2およびゲート電極2aと同じAl薄膜300nmの膜
厚で製膜し所定のパターンに加工しソースバス電極6,
ドレイン電極7を形成した。その後、絵素電極8をIT
O膜を200nmの厚みで製膜パータンニングして形成
した。以上のように構成されたTFT液晶表示装置を動
作したところ、良好な結果を得ることができた。
A specific embodiment will be described. As the translucent insulating substrate 1, a 7059 glass substrate manufactured by Corning Incorporated was used. Dry etching was performed on the surface of the glass substrate to form stripe-shaped irregularities. After that, the pattern edge was smoothed by wet etching.
Next, the target is an Al target, the sputtering gas is Ar, the gas pressure is 0.3 Pa, and the sputtering power is 10 W / cm 2 on the translucent insulating substrate 1 on which the stripe-shaped uneven portion 9 is formed by DC sputtering. An aluminum (Al) thin film with a film thickness of 200 nm under the conditions,
Form a predetermined pattern by wet etching,
The gate bus electrode 2 and the gate electrode 2a were used. Then, as the insulating film 3, the temperature of the insulating substrate 1 is 350 ° C. and the silicon nitride film is 400 nm by plasma CVD.
An a-Si film of 100 nm as the semiconductor layer 4 and a silicon nitride film of 100 nm as the semiconductor protective layer 4a were continuously formed. Then, the semiconductor protective layer 4a was processed into a predetermined pattern. N + type a-as ohmic contact layer 5
After forming a Si film to a thickness of 30 nm, an island pattern was formed simultaneously with the semiconductor layer 4. After that, an Al thin film having the same film thickness of 300 nm as the gate bus electrode 2 and the gate electrode 2a is formed and processed into a predetermined pattern to form the source bus electrode
The drain electrode 7 was formed. After that, the pixel electrode 8
An O film was formed by film forming with a thickness of 200 nm. When the TFT liquid crystal display device configured as described above was operated, good results were obtained.

【0011】本実施例では、凹凸部の形状としてストラ
イプ状のものを示したが、その他に凹凸部形状として
は、穴状のものもある。例えば、本実施例として円形の
穴状にレーザビームを照射して下地を溶かして形成した
後にさらにゲートバス電極用の導電膜を製膜することに
より、同様の効果を得ることができる。ここで、この凹
凸により電極線幅がどれだけ広げられるかその効果につ
いて概算する。凹凸の高さをtとし、線幅をWとし、凹
凸の数をn個とするとストライプでは、みかけの線幅は
2nt+Wとなる。例えば、Wが50μmでtが1μm
とし、5μmピッチで凹凸を形成したとすると、n=1
0,2nt=20μmとなり、5/7幅を削減できる。
実際には、図4に示したように斜面状に形成されるので
みかけの線幅は2((W/2n)2+t21/2nに近く
なり、上記の例で計算すると53.8μm程度となり、
7%弱の削減にしかならない。ところがtを2μmとす
ると64μmとなり、12%程度の削減となる。このこ
とから溝tの深さが深いほど本発明の効果が大きいこと
がわかる。また、下地の凹凸の形状を穴状に形成し、さ
らにゲート電極膜を形成するとストライプ状の溝に比べ
ると効果は劣るが処理無しと比較すると効果がある。本
発明の凹凸形成方法としてはパターン形状に応じて選択
すれば良い。
In the present embodiment, the shape of the uneven portion is shown as a stripe shape, but in addition to this, the uneven portion may have a hole shape. For example, in the present embodiment, a similar effect can be obtained by forming a conductive film for a gate bus electrode after forming a circular hole by irradiating a laser beam to melt the base. Here, the effect of how much the electrode line width can be widened by this unevenness will be roughly estimated. When the height of the unevenness is t, the line width is W, and the number of the unevenness is n, the apparent line width of the stripe is 2nt + W. For example, W is 50 μm and t is 1 μm
And unevenness is formed at a pitch of 5 μm, n = 1
Since 0,2nt = 20 μm, the width of 5/7 can be reduced.
Actually, the apparent line width is close to 2 ((W / 2n) 2 + t 2 ) 1/2 n because it is formed in a slope shape as shown in FIG. 4, which is 53. About 8 μm,
The reduction is just under 7%. However, when t is 2 μm, it becomes 64 μm, which is about 12% reduction. From this, it is understood that the effect of the present invention is greater as the depth of the groove t is deeper. Further, when the unevenness of the base is formed in a hole shape and the gate electrode film is further formed, the effect is inferior to the stripe-shaped groove, but it is effective as compared to the case without treatment. The unevenness forming method of the present invention may be selected according to the pattern shape.

【0012】[0012]

【発明の効果】以上の実施例から明らかなように本発明
は、透光性絶縁基板上の所定部に凹凸を形成し、その凹
凸を形成した透光性絶縁基板上に少なくともゲートバス
電極を形成した構成によるので、その結果、絵素電極の
面積を拡大することができ、しかも、ゲートバス電極お
よびソースバス電極の交差部の対抗電極とのギャップの
機械的圧力による電気的短絡を防ぐことができるTFT
液晶表示装置を提供できる。
As is apparent from the above-described embodiments, the present invention forms irregularities on a predetermined portion of a translucent insulating substrate, and at least a gate bus electrode is provided on the translucent insulating substrate on which the irregularities are formed. As a result of the formed structure, the area of the pixel electrode can be expanded as a result, and moreover, the electrical short circuit due to the mechanical pressure of the gap between the counter electrode at the intersection of the gate bus electrode and the source bus electrode can be prevented. TFT that can
A liquid crystal display device can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるTFT液晶表示装置
の一部断面図
FIG. 1 is a partial cross-sectional view of a TFT liquid crystal display device according to an embodiment of the present invention.

【図2】図1とは異なる部分の断面図FIG. 2 is a sectional view of a portion different from FIG.

【図3】図1,図2の断面部を含むTFT液晶表示装置
の平面図
FIG. 3 is a plan view of a TFT liquid crystal display device including the cross-sectional portions of FIGS.

【図4】本発明の他の実施例におけるTFT液晶表示装
置の一部断面図
FIG. 4 is a partial cross-sectional view of a TFT liquid crystal display device according to another embodiment of the present invention.

【図5】従来のTFT液晶表示装置の一部断面図FIG. 5 is a partial sectional view of a conventional TFT liquid crystal display device.

【図6】図5とは異なる部分の断面図FIG. 6 is a sectional view of a portion different from FIG.

【図7】図5,図6の断面部を含むTFT液晶表示装置
の平面図
FIG. 7 is a plan view of a TFT liquid crystal display device including the cross-sectional portions of FIGS.

【符号の説明】[Explanation of symbols]

1 透光性絶縁性基板 2 ゲートバス電極 2a ゲート電極 3 絶縁膜 4 半導体層 4a 半導体保護層 5 オーミックコンタクト層 6 ソースバス電極 7 ドレイン電極 8 絵素電極 9 凹凸部 1 translucent insulating substrate 2 gate bus electrode 2a gate electrode 3 insulating film 4 semiconductor layer 4a semiconductor protective layer 5 ohmic contact layer 6 source bus electrode 7 drain electrode 8 picture element electrode 9 uneven portion

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 透光性絶縁基板と、その透光性絶縁基板
上に順次パターン形成されたゲートバス電極,ゲート電
極,絶縁膜,半導体層およびオーミック電極とを少なく
とも有するTFT液晶表示装置において、前記透光性絶
縁基板上の所定部に凹凸を形成し、その凹凸を形成した
透光性絶縁基板上に少なくともゲートバス電極を形成し
たことを特徴とするTFT液晶表示装置。
1. A TFT liquid crystal display device having at least a translucent insulating substrate and a gate bus electrode, a gate electrode, an insulating film, a semiconductor layer and an ohmic electrode which are sequentially patterned on the translucent insulating substrate, A TFT liquid crystal display device characterized in that irregularities are formed on a predetermined portion of the translucent insulating substrate, and at least a gate bus electrode is formed on the irregular translucent insulating substrate.
【請求項2】 透光性絶縁基板上の所定部に物理的エッ
チング法および化学的エッチング法のうち少なくとも一
つを用いて凹凸部を形成し、その凹凸部を含む前記透光
性絶縁基板上にゲートバス電極を形成する工程を少なく
とも有することを特徴とするTFT液晶表示装置の製造
方法。
2. An uneven portion is formed on a predetermined portion of the transparent insulating substrate using at least one of a physical etching method and a chemical etching method, and the uneven insulating portion includes the uneven portion. A method for manufacturing a TFT liquid crystal display device, which further comprises at least a step of forming a gate bus electrode.
JP13834692A 1992-05-29 1992-05-29 Tft liquid crystal display device and its production Pending JPH05333372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13834692A JPH05333372A (en) 1992-05-29 1992-05-29 Tft liquid crystal display device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834692A JPH05333372A (en) 1992-05-29 1992-05-29 Tft liquid crystal display device and its production

Publications (1)

Publication Number Publication Date
JPH05333372A true JPH05333372A (en) 1993-12-17

Family

ID=15219779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834692A Pending JPH05333372A (en) 1992-05-29 1992-05-29 Tft liquid crystal display device and its production

Country Status (1)

Country Link
JP (1) JPH05333372A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006064928A (en) * 2004-08-26 2006-03-09 Seiko Epson Corp Electrooptical apparatus and electronic device
CN104733476A (en) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 Array substrate, display panel and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006064928A (en) * 2004-08-26 2006-03-09 Seiko Epson Corp Electrooptical apparatus and electronic device
CN104733476A (en) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 Array substrate, display panel and display device

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