JPH05327733A - Decentralized processing system - Google Patents

Abstract

PURPOSE:To provide a decentralized processing system which can perform the broadcast communication and also can collect the confirmed answers from the receiver side for each module at the transmitter side of the broadcast communication. CONSTITUTION:A communication control circuit 62 included in a processing module 5 instructs the start of a confirmed answer with a 1st answer collection timing signal and then designates in sequence the modules that should send the answers with a 2nd answer collection timing signal after transmission of the broadcast data in the transmission state of the broadcast communication. In the reception state of the broadcast communication, the answer signal showing a normal or abnormal reception state is transmitted in the answer timing assigned to its own module.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a distributed processing system in which a plurality of processing modules are connected by a common bus, and one processing module can perform broadcast transmission to a plurality of other processing modules. The present invention relates to a distributed processing system that can be used.

[0002]

2. Description of the Related Art In a distributed processing system including a plurality of processing modules, there are a distributed processing system that performs confirmation response and a system that does not perform confirmation response during broadcast communication. In a system that does not make a confirmation response, the processing module of the transmission source cannot confirm whether or not the broadcast communication is surely performed.

As a system for making a confirmation response, there is a system provided with a so-called future bus. The bus has a response signal line, and each processing module is wired or connected to the response signal line through the gate of the open collector.

When outputting the confirmation response of the broadcast communication, a low level signal is output to the response signal line as an abnormal response. In addition, a signal that is not low level is output as a normal response. Therefore, the transmission source processing module can know that the broadcast communication has not been normally completed when the level of the response signal line is low. During individual communication, the processing module on the reception side outputs a low-level normal response signal to the response signal line.

However, in such a system,
The transmission source processing module cannot specify which processing module has the reception abnormality. As an improved version of such a system, for example, Japanese Patent Laid-Open No. 64-114 is known.
There is one described in Japanese Patent No. 38.

FIG. 8 is a configuration diagram showing the configuration of the distributed processing system described in that publication. In the figure, 2 is a common bus that connects the processing modules 100a to 100n, and 3 is an arbiter circuit that arbitrates the request for the transmission right of the processing modules 100a to 100n.

FIG. 9 is a block diagram showing a part of the processing module 100a in detail. In the figure, 20 is a control signal bus, 21 is an address bus, and 22 is a data bus.

A broadcast transmission circuit 104 is connected to the broadcast response reception circuit 141 and the broadcast address generation circuit 142 connected to the address bus 21, a driver 143 connected to the data bus 22, and a local bus connection to the driver 143. Parity generating circuit 144, three registers 145,
146 and 147 are included.

Reference numeral 105 is a broadcast receiving circuit, which is a broadcast address detecting circuit 15 connected to the address bus 21.
1, a receiver 152 connected to the data bus, a receiver 152, and a parity check circuit 153 connected to the control signal bus 20. Further, the open collector AND circuit 15 which logically ANDs the output of the broadcast address detection circuit 151, the output of the parity check circuit 153 and the data of the control signal bus 20 and outputs the logical product to the address bus 21.
4, three registers 15 connected to the receiver 152
5,156,157 are included. The other processing modules 100b to 100n have the same configuration as the processing module 100a.

Next, the operation will be described with reference to the timing chart of FIG. Each processing module 100a-100
A predetermined number (for example, 3) of n is grouped into one group. The processing module in each group is connected to one line of the address bus 21. That is, each processing module belonging to a certain group is wired or connected to a specific one line in the address bus 21 assigned to the group.

When transmitting, the processing module which is the transmission source, for example, the processing module 100a, sends a BRQ signal to the arbiter circuit 3 via the control signal bus 20 as shown in FIG. Upon receiving the BAK signal thus generated, the right to use the common bus 2 is obtained.

Here, considering the case of broadcasting 3 bytes of data by broadcasting, after acquiring the right to use the common bus 20,
Broadcast address generation circuit 142 of processing module 100a
Generates a broadcast address and outputs it to the address bus 21. Then, the parity check generation circuit 144
Generates a parity bit for the data set in the registers 145 to 147 and sends it to the driver 143 together with the data. The driver 143 outputs the data with the parity bit to the data bus 22.

In the other processing modules 100b to 100n, the broadcast address detection circuit 151 takes in the data on the address bus 21 and compares it with the broadcast address value. When they match, the detection signal indicating the detection of the broadcast communication is sent to the AND circuit 154 and the receiver 152.

When the receiver 152 receives the detection signal,
3 bytes of data on the data bus 22 are fetched. Then, the parity bit in the data is sent to the parity check circuit 153, and the parts other than the parity bit are stored in the registers 155 to 157. The parity check circuit 153 performs a parity check based on the parity bit.

The AND circuit 154 includes a control signal bus 20.
The control signal, the detection signal, and the signal indicating the result of the parity check are input. The output of the AND circuit 154 is connected to one specific line of the address bus 21 and serves as a confirmation response signal. Here, if the result of the parity check is NG, the AND circuit 154 outputs a low level. The transmission source processing module 100a fetches the acknowledgment signal from the address bus 21 at the timing when the BAK signal changes from "1" to "0".

When there is a low level line, the transmission source processing module 100a can recognize that a reception abnormality has occurred in any of the processing modules connected thereto.

[0017]

Since the conventional distributed processing system is configured as described above, it is possible for the processing module of the transmission source to specify the group including the processing module in which the reception is abnormal. However, it is impossible to specify the processing module itself in which the reception is abnormal.
Further, since the address bus is used as a line for the confirmation response, the number of processing modules capable of transmitting the confirmation response is limited by the number of bits of the address bus. further,
When performing broadcast communication for any of a plurality of processing modules of the processing modules 100a to 100n, detailed information regarding the destination address is added to the transmitted data, and the data is addressed to the own module. It is necessary for each processing module on the receiving side to determine whether or not it is a real thing, and when performing such broadcast communication, there is a problem that a large load is applied to each processing module.

The present invention has been made in order to solve the above problems, and the number of processing modules that can make a confirmation response in broadcast communication is not limited, and a processing module in which an abnormality has occurred can be confirmed by a confirmation response. It is an object of the present invention to obtain a distributed processing system that can be specified and that can perform broadcast communication in which the other party is arbitrarily specified without increasing the load on the processing module.

[0019]

A distributed processing system according to a first aspect of the present invention comprises a plurality of processing modules and a common bus connecting these processing modules, and one of the processing modules is provided. A system for performing broadcast communication in which a processing module transmits the same data to a plurality of other processing modules, wherein a common bus transmits a first timing signal indicating a timing for collecting a response signal for the broadcast transmission. No. 1 response collection timing line and the second showing the response timing of the response signal of each processing module
A second response collection timing line for transmitting the timing signal and a response signal line for transmitting the response signal, and each processing module transmits the broadcast transmission data when it becomes the transmission side of the broadcast communication. After that, after sending the first timing signal to the first response collection timing line and then sending the second timing signal to the second response collection timing line, the first response signal is sent to the receiving side of the broadcast communication. The communication control circuit sends out a response signal indicating whether or not the reception of the broadcast transmission data is normally performed to the response signal line at the response signal return timing of its own module in the timing signal 2 of FIG.

A distributed processing system according to a second aspect of the present invention comprises a plurality of processing modules and a common bus connecting these processing modules, and one of the processing modules is the other processing module. A system for performing broadcast communication for transmitting the same data to a plurality of processing modules of a common bus, wherein a common bus transmits a first timing signal indicating a timing for collecting response signals for the broadcast transmission. A timing line, a second response collection timing line for transmitting a second timing signal indicating the return timing of the response signal of each processing module, and a response request signal line for transmitting a response request signal designating the destination of the broadcast communication. And a response signal line for transmitting a response signal, and each processing module includes a reception buffer for storing the data received from the common bus. , If it becomes the transmitting side of the broadcast, after the transmission of the broadcast transmission data, after sending the first timing signal to said first response collection timing line, a second
A second timing signal is sent to the response collection timing line of, and a response is made when the processing module is the destination of the broadcast communication in synchronization with the response return timing of each processing module indicated by the second timing signal. When the request signal is significant and becomes the receiving side of the broadcast communication, when the response request signal is significant at the response signal return timing of the own module in the second timing signal, the reception of the broadcast transmission data A communication control circuit that sends a response signal to the response signal line indicating whether or not it has been normally performed, and does not send the response signal when the response signal is unwilling and discards the broadcast data in the reception buffer. Is to have.

[0021]

In the communication control circuit according to the invention of claim 1,
When it becomes the sending side of the broadcast communication, it can check the reception result of each processing module on the receiving side by fetching each response signal on the response signal line, and regardless of the number of processing modules in the system. The broadcast reception result of the processing module can be confirmed for each processing module.

Further, the communication control circuit according to the second aspect of the present invention notifies each processing module on the receiving side of the broadcast communication whether or not the module is the destination of the broadcast communication by a response request signal. , Allows non-destination modules to discard received data and not acknowledge.

[0023]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a distributed processing system according to an embodiment of the present invention. In the figure, 1a to 1n are processing modules, and 2 is those processing modules 1a.
It is a common bus connecting ~ 1n. Each processing module 1
In a to 1n, reference numeral 5 is a broadcast communication circuit with a confirmation response (hereinafter referred to as a broadcast communication circuit) having a confirmation response function.

FIG. 2 is a block diagram showing the structure of the broadcast communication circuit 5 and the detailed structure of the common bus 2. As shown in FIG. 2, in this case, the common bus 2 is a data bus 23 for transmitting information data, destination address data in individual communication, and address data meaning broadcast in broadcast communication, An address tag signal line 24 for transmitting an address tag signal indicating that the signal on the data bus 23 is address data, and a data tag signal indicating that the signal on the data bus is information data Data tag signal line 25, clock line 2 for transmitting a transmission clock indicating the sampling timing of information data
6. The first response collection timing line 27 that transmits the first response collection timing (first timing signal) that the transmission side notifies the reception side that the response collection is started, and which processing module is the response A second response collection timing line 28 for transmitting a second response collection timing (second timing signal) for designating whether to return, and a response signal indicating whether or not the receiving side has normally received the data. A response signal line 29 for returning to the side, a busy line 30 for transmitting a busy signal indicating that any one of the processing modules 1a to 1n uses the common bus 2, and a BRQ signal for an arbiter circuit (not shown). And an occupancy control line 31 for transmitting the BAK signal from the arbiter circuit.

In the broadcast communication circuit 5, 61 is a processor, 62 is a communication control circuit for controlling broadcast communication,
63 is a transmission data buffer for temporarily storing transmission data prepared by the processor, 64 is a reception data buffer for temporarily storing data received by the communication control circuit 62, 65 is a driver for transmitting data to the common bus 2, and 66 is It is a receiver for taking in data from the common bus 2.
67 is an internal bus that connects the processor 61 to the communication control circuit 62, the transmission data buffer 63, and the reception data buffer 64, and 68 is the communication control circuit 62 that is the processor 61.
It is an interrupt signal line for transmitting the reception completion to the.

Next, the operation will be described with reference to the timing chart of FIG. Here, a case where the processing module 1n broadcasts data D1 to D4 to the other processing modules 1a to 1m will be described as an example.

First, in the processing module 1n of the transmission source, the processor 61 sets the transmission data in the transmission data buffer 63 and sets the transmission data length in the communication control circuit 62. Then, a transmission start instruction is given to the communication control circuit 62 to transmit the transmission data using the broadcast address.
When the communication control circuit 62 obtains the bus use right from the arbiter circuit via the occupancy control line 31, the communication control circuit 62 makes the busy signal indicating that the common bus 2 is in use significant (low level in FIG. 3).

Next, a broadcast address value indicating that this transmission operation is broadcast communication is sent to the data bus 23. Further, one pulse is sent to the address tag signal line 24 in order to cause each of the processing modules 1a to 1n to detect the broadcast address value (the address tag is turned on and off once). The communication control circuit 62 of each of the processing modules 1a to 1n samples the data on the data bus 23 at the rising edge of the address tag, for example, and detects that the transmission operation is broadcast communication.

The communication control circuit 62 of the processing module 1n at the transmission source uses the data tag 2 to transmit the information data.
5 is made significant (low level in FIG. 3), a parity bit is added to the data in the transmission data buffer 63, and then it is sequentially sent to the data bus 23. Further, a transmission clock synchronized with the data is sent to the clock line 26 in order to cause each of the processing modules 1a to 1n to take in the information data.

Since the communication control circuit 62 of each of the processing modules 1a to 1n recognizes that it is a broadcast communication, if there is a free space in the reception data buffer 64, the data bus 23
The above information data is fetched according to the transmission clock and stored in the reception data buffer 64. At the same time, the parity check is performed.

After transmitting the information data, the communication control circuit 62 of the processing module 1n of the transmission source first notifies the processing modules 1a to 1n that the response collection is started.
1 pulse is sent to the response collection timing line 27 of. Further, in order to set the timing at which each processing module 1a to 1n returns a response, the second response collection timing line 2
The signal on 8 is turned on and off n + 1 times.

The communication control circuit 62 of each of the processing modules 1a to 1n samples the level on the first response collection timing line 27 at the rising edge of the signal on the second response collection timing line 28 to obtain the first response collection timing. The timing at which the significant level of is detected is recognized as the starting point of the response return timing of the processing module having the module address "1" (see FIG. 3 (i)). Then, the subsequent rise of the second response collection timing is sequentially recognized as the starting point of the response return timing of the processing modules of the module addresses “2” to “n”.

The communication control circuit 62 of each of the processing modules 1a to 1n returns a response signal when the recognized module address matches the address of its own module. If the reception data buffer 64 is empty and the information data is received and the result of the parity check is normal, the broadcast communication circuit 5 makes the response signal significant (low level in FIG. 3) at the response return timing. To do. If the received data buffer 64 is received in a non-empty state or if the result of the parity check is abnormal, the response signal is disabled at the response return timing.

The example shown in FIG. 3 (i) is an example in which only the processing module with the module address "4" could not be received normally. The signals on the communication control circuit 62 and the interrupt signal line 68 that have returned the normal response are made significant, and the reception completion is notified to the processor 61.

The communication control circuit 62 of the transmission source processing module 1n also receives the response return timing of each of the processing modules 1a to 1n from the signals on the first response collection timing signal line 27 and the second response collection timing signal line 28. Can be recognized. Then, the response signals from the processing modules 1a to 1n can be collected by sequentially sampling the response signals at the trailing edge of the second response collection timing signal. In the example of FIG. 3, it is recognized that the reception abnormality has occurred only in the processing module having the module address “4”.

After that, the communication control circuit 62 of the processing module 1n at the transmission source makes the busy signal insignificant and releases the common bus 2. In this embodiment, the transmission source processing module 1n also receives the information data and returns a response signal. However, since the transmission source processing module 1n knows that its own module is the transmission source, it receives it. Control may be performed such that the information data and the response signal are discarded.

Example 2. FIG. 4 is a block diagram showing a configuration of processing modules and a detailed configuration of a common bus in a distributed processing system according to another embodiment of the present invention. The overall configuration of the system is the same as the configuration shown in FIG. As shown in FIG. 4, in this case, the common bus 2 is
Each processing module 1a synchronized with each response return timing
Includes a response request signal line 32 that transmits a response request signal indicating whether or not 1n is a broadcast destination.

Next, the operation will be described with reference to the timing chart of FIG. Also here, the case where the processing module 1n broadcasts the data D1 to D4 to the other processing modules 1a to 1m will be described as an example.

Also in this case, the processing module 1 of the transmission source
n performs broadcast communication as in the case of the first embodiment. That is, first, in the processing module 1n of the transmission source,
The processor 61 sets the transmission data in the transmission data buffer 63, and sets the transmission data length in the communication control circuit 62. Then, a transmission start instruction is given to the communication control circuit 62 to transmit the transmission data using the broadcast address. When the communication control circuit 62 obtains the bus use right from the arbiter circuit via the exclusive control line, it makes the busy line 30 indicating that the common bus 2 is in use.

Next, a broadcast address value indicating that this transmission operation is broadcast communication is sent to the data bus 23. Further, one pulse is sent to the address tag line 24 in order to cause each of the processing modules 1a to 1n to detect the broadcast address value. Broadcast communication circuit 5 of each processing module 1a-1n
Samples the data on the data bus 23 at the rising edge of the address tag and detects that the transmission operation is broadcast communication.

The communication control circuit 62 of the transmission source processing module 1n uses the data tag 2 to transmit the information data.
5 is made significant, a parity bit is added to the data in the transmission data buffer 63, and then it is sequentially transmitted to the data bus 23. Further, a transmission clock synchronized with the data is sent to the clock line 26 in order to cause each of the processing modules 1a to 1n to take in the information data.

Since the communication control circuit 62 of each of the processing modules 1a to 1n recognizes that it is a broadcast communication, if there is a free space in the reception data buffer 64, the data bus 23
The above information data is fetched according to the transmission clock and stored in the reception data buffer 64. At the same time, the parity check is performed.

After transmitting the information data, the communication control circuit 62 of the processing module 1n as the transmission source first notifies the processing modules 1a to 1n that the response collection is started.
1 pulse is sent to the response collection timing line 27 of. Furthermore, in order to set the timing at which each processing module 1a-1m returns a response, the second response collection timing line 2
The signal on 8 is turned on and off n + 1 times.

The communication control circuit 62 of each of the processing modules 1a to 1n samples the level of the signal on the first response collection timing line 27 at the rising edge of the second response collection timing, and determines the significance of the first response collection timing. The timing at which the level is detected is recognized as the start point of the response return timing of the processing module having the module address "1" (see FIG. 3 (i)). Then, the subsequent rise of the second response collection timing is sequentially recognized as the starting point of the response return timing of the processing modules of the module addresses “2” to “n”.

In this case, the transmission source processing module 1
The n further specifies the processing module to which the response is to be returned by the response request signal. That is, if the processing module corresponding to each response return timing defined by the signals on the first response collection timing signal line 27 and the second response collection timing signal line 28 is a module that does not need to return a response. At the response return timing, the response request signal line 32 is made insignificant (high level in FIG. 5) in synchronization with the fall of the second response collection timing signal. If the processing module is to return a response, the response request signal line 32 is made significant at the response return timing.

The communication control circuit 62 of each processing module 1a-1n samples the signal on the response request signal line 32 at the rising edge of the signal on the second response collection timing signal line 28 at the response return timing of its own module. ,
It recognizes whether or not its own module is requested to respond, that is, whether or not it is the destination of the broadcast communication.

When the communication control circuit 62 of each of the processing modules 1a to 1n recognizes that its own module is the destination of the broadcast communication, it returns a response signal at the response return timing of its own module. That is, the communication control circuit 62 receives the information data when the reception data buffer 64 is empty,
If the result of the parity check is normal, the response signal is made significant at the response return timing. Whether the received data buffer 64 is not empty
Alternatively, if the result of the parity check is abnormal, the response signal is invalidated at the response return timing.

When the communication control circuit 62 of the processing modules 1a to 1n recognizes that its own module is not the destination of the broadcast communication, it makes the response signal insignificant at the response return timing of its own module. Further, the data in the reception data buffer 64 is discarded. In the example of FIG. 5, the processing modules with the module addresses “2” and “3” are not the destination of the broadcast communication, so the response signal is not significant, and the processing module with the module address “5” is the destination. There is a case where the response signal line 29 is not significant because the reception is not normally completed.

The communication control circuit 62 of the transmission source processing module 1n receives the response return timing of each of the processing modules 1a to 1n from the signals on the first response collection timing signal line 27 and the second response collection timing signal line 28. Recognize. Then, the response signals from the respective processing modules 1a to 1n are collected by sequentially sampling the response signals at the trailing edge of the signal of the second response collection timing signal in the period in which the response request signal is significant. In the example of FIG. 5, it is recognized that the reception abnormality has occurred only in the processing module of the module address “5”.

After that, the communication control circuit 62 of the processing module 1n at the transmission source makes the busy signal insignificant and releases the common bus 2. In this way, the information data is substantially sent to only the processor 61 designated by the response request signal, and an excessive load is prevented from being applied to the processor of the processing module which is not the destination of the broadcast communication. To be done.

Example 3. In the second embodiment, the first response collection timing line 27 and the second response collection timing line 2
8, the response request signal line 32 and the response signal line 29 were independent signal lines.
You may also use it together.

FIG. 6 shows the first response collection timing line 27,
Second response collection timing line 28, response request signal line 32
And response signal line 29 is a block diagram showing a broadcast communication circuit of a processing module of the distributed processing system in which each line of the data bus 23 is shared. As shown in the timing chart of FIG. 7, for example, the first response collection timing line, the second response collection timing line, the response request signal line, and the response signal line are respectively the third bit (d3) of the data bus 23. ), The second bit (d2), the first bit (d1), and the zeroth bit (d0).

Next, the operation will be described with reference to the timing chart of FIG. Also here, the case where the processing module 1n broadcasts the data D1 to D4 to the other processing modules 1a to 1m will be described as an example.

Also in this case, the processing module 1 of the transmission source
n performs broadcast communication as in the case of the first embodiment. That is, first, in the processing module 1n of the transmission source,
The processor 61 sets the transmission data in the transmission data buffer 63, and sets the transmission data length in the communication control circuit 62. Then, a transmission start instruction is given to the communication control circuit 62 to transmit the transmission data using the broadcast address. When the communication control circuit 62 obtains the bus use right from the arbiter circuit via the exclusive control line, it makes the busy line 30 indicating that the common bus 2 is in use.

Next, a broadcast address value indicating that this transmission operation is broadcast communication is sent to the data bus 23. Further, one pulse is sent to the address tag line 24 in order to cause each of the processing modules 1a to 1n to detect the broadcast address value. Broadcast communication circuit 5 of each processing module 1a-1n
Detects the transmission operation being broadcast communication by sampling the data on the data bus 23 at the rising edge of the address tag, for example.

The communication control circuit 62 of the transmission source processing module 1n uses the data tag 2 to transmit the information data.
5 is made significant, a parity bit is added to the data in the transmission data buffer 63, and then it is sequentially transmitted to the data bus 23. Further, a transmission clock synchronized with the data is sent to the clock line 26 in order to cause each of the processing modules 1a to 1n to take in the information data.

Since the communication control circuit 62 of each of the processing modules 1a to 1n recognizes that it is a broadcast communication, if there is a free space in the reception data buffer 64, the data bus 23
The above information data is fetched according to the transmission clock and stored in the reception data buffer 64. At the same time, the parity check is performed.

The communication control circuit 62 of the processing module 1n at the transmission source makes the signal of the data tag signal line 25 insignificant after transmitting the information data. Each of the processing modules 1a to 1n detects that the signal has become meaningless and detects the data bus 23
It is recognized that the third bit, the second bit, the first bit, and the 0th bit of are assigned to the first response collection timing line, the second response collection timing line, the response request signal line, and the response signal line.

Communication control circuit 6 of the transmission source processing module
2 indicates that each processing module 1a starts the response collection.
In order to notify 1n to 1n, one pulse is sent to the first response collection timing line, that is, the third bit line of the data bus 23 (the signal on this line is referred to as the d3 signal). Furthermore, in order to set the timing at which each of the processing modules 1a to 1n returns a response, the signal (d) on the second response collection timing line, that is, the second bit line of the data bus 23 is set.
2 signals) is turned on and off n + 1 times.

The communication control circuit 62 of each of the processing modules 1a to 1n samples the level of the d3 signal at the rising edge of the d2 signal, and the timing at which the significant level of the d3 signal is detected is the response of the processing module of module address "1". Recognize that this is the start point of the return timing. Then, the subsequent rise of the d2 signal is sequentially recognized as the start point of the response return timing of the processing modules of the module addresses "2" to "n".

The transmission source processing module 1n further includes
The response request signal identifies the processing module to which the response should be sent back. That is, if the processing module corresponding to each response return timing defined by the d3 signal and the d2 signal is a module that does not need to return a response,
At the response return timing, the first bit signal of the response request signal line, that is, the data bus (this signal is referred to as the d1 signal) is made insignificant (high level in FIG. 7) in synchronization with the fall of the d2 signal. .. Further, if the processing module is to return a response, the d1 signal is made significant at the response return timing.

The communication control circuit 62 of each of the processing modules 1a to 1n samples the d1 signal at the rising edge of the d2 signal at the response return timing of its own module,
It recognizes whether its own module is the destination of the broadcast communication.

When the communication control circuit 62 of each of the processing modules 1a to 1n recognizes that its own module is the destination of the broadcast communication, it returns a response signal at the response return timing of its own module. That is, the communication control circuit 62 receives the information data when the reception data buffer 64 is empty,
If the result of the parity check is normal, the response signal line, that is, the data bus 2 at the response return timing.
The 0th bit signal of 3 (this signal is referred to as the d0 signal) is made significant. If the received data buffer 64 is received in a non-empty state, or if the result of the parity check is abnormal, the d0 signal is disabled at the response return timing.

When the communication control circuit 62 of the processing modules 1a to 1n recognizes that its own module is not the destination of the broadcast communication, it makes the d0 signal insignificant at the response return timing of its own module. Further, the data in the reception data buffer 64 is discarded. In the example of FIG. 7, as in the example shown in FIG. 5, the processing modules having the module addresses “2” and “3” are not the destinations of the broadcast communication, so the d0 signal is not significant. The processing module of "5" shows a case where the d0 signal is not significant because the reception is not completed normally although it is the destination.

The communication control circuit 62 of the processing module 1n at the transmission source recognizes the response return timing of each of the processing modules 1a to 1n from the d3 signal and the d2 signal. Then, the response signals from the processing modules 1a to 1n are collected by sequentially sampling the response signals at the falling edge of the d2 signal in the period in which the response request signal is significant.

After that, the communication control circuit 62 of the processing module 1n at the transmission source makes the busy signal unwilling and releases the common bus 2. According to this embodiment, the number of signal lines of the common bus 2 can be reduced as compared with the cases of the first and second embodiments.

As a concrete configuration of the communication control circuit 62 in each of the above embodiments, a hardware logic circuit can be adopted, but a one-chip microprocessor or the like can also be adopted.

[0068]

As described above, according to the invention described in claim 1, in the distributed processing system, the communication control unit of the processing module on the transmission side of the broadcast communication uses the first timing signal and the second timing signal. By setting the response return timing of each processing module on the receiving side and each processing module on the receiving side to return the reception result of the broadcast communication at the response return timing of its own module You can identify the receiving processing module that occurred,
There is an effect that recovery processing such as resending can be performed reliably and quickly, and that there is no limit to the number of modules that can send a response confirmation.

According to the second aspect of the present invention, the distributed processing system is configured so that the destination of the broadcast communication can be designated by the response request signal. Therefore, for any of a plurality of processing modules in the system. It is possible to recognize that the broadcast data is effective data for those modules, and it is possible to obtain the one that can perform the broadcast communication to virtually any plurality of processing modules.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a distributed processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing processing modules and a common bus in the distributed processing system according to the first embodiment of the present invention.

FIG. 3 is a timing diagram for explaining the operation of what is shown in FIG.

FIG. 4 is a block diagram showing processing modules and a common bus in the distributed processing system according to the second embodiment of the present invention.

FIG. 5 is a timing diagram for explaining the operation of the one shown in FIG.

FIG. 6 is a block diagram showing a processing module and a common bus in a distributed processing system according to a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the one shown in FIG.

FIG. 8 is a configuration diagram showing a configuration of a conventional distributed processing system.

9 is a block diagram showing a part of the internal configuration of the processing module shown in FIG.

FIG. 10 is a timing diagram for explaining the operation of what is shown in FIG.

[Explanation of symbols]

 1a to 1n Processing module 2 Common bus 27 First response collection timing line 28 Second response collection timing line 29 Response signal line 32 Response request signal line 62 Communication control circuit 64 Received data buffer

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Claims (2)

[Claims] 1. A processing module comprising a plurality of processing modules and a common bus connecting these processing modules, wherein one processing module of the plurality of processing modules transmits the same data to another plurality of processing modules. In the distributed processing system that performs broadcast communication, the common bus is configured to transmit a first response collection timing line that transmits a first timing signal indicating a timing for collecting a response signal for broadcast transmission, and a response signal of each processing module. A second response collection timing line for transmitting a second timing signal indicating a return timing; and a response signal line for transmitting the response signal, wherein the processing module is a sender of the broadcast communication. , After transmitting the broadcast transmission data, after transmitting the first timing signal to the first response collection timing line,
When the second timing signal is sent to the second response collection timing line and becomes the receiving side of the broadcast communication, the broadcast data is received at the response signal return timing of the own module in the second timing signal. A distributed processing system, comprising: a communication control circuit that sends a response signal indicating whether or not the operation has been normally performed to the response signal line. 2. A plurality of processing modules and a common bus connecting these processing modules are provided, wherein one processing module of the plurality of processing modules transmits the same data to another plurality of processing modules. In the distributed processing system that performs broadcast communication, the common bus is configured to transmit a first response collection timing line that transmits a first timing signal indicating a timing for collecting a response signal for broadcast transmission, and a response signal of each processing module. A second response collection timing line that transmits a second timing signal indicating a return timing, a response request signal line that transmits a response request signal that specifies a destination of the broadcast communication, and a response signal line that transmits the response signal. And the processing module is a receiving buffer for storing data received from the common bus, and is a transmission side of the broadcast communication. In this case, after transmitting the broadcast transmission data, after transmitting the first timing signal to the first response collection timing line, and then transmitting the second timing signal to the second response collection timing line, The second
In synchronization with the response return timing of each processing module indicated by the timing signal of, when the processing module is the destination of the broadcast communication, the response request signal is made significant, and when it becomes the receiving side of the broadcast communication, When the response request signal is significant at the response signal return timing of the own module in the second timing signal, a response signal indicating whether or not the reception of the broadcast transmission data is normally performed is transmitted to the response signal line. A distributed processing system, comprising: a communication control circuit that transmits the response signal and discards the broadcast data in the reception buffer without transmitting the response signal when the response signal is insignificant.