JP2001308958A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit that can prevent a data transmission rate from being deteriorated due to addition of a flag. SOLUTION: No header is added to data stored in a specific register (transmission register 0) among transmission registers, only the data without the header are multiplexed with other data to which headers are attached, and the multiplexed data are transmitted together with a frame synchronizing signal. A receiver side discriminates the data header attached to the received data depending on the presence of the synchronizing signal and identifies a plurality of data on the basis of the data header.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for transmitting and receiving a plurality of types of multiplexed data.

[0002]

2. Description of the Related Art When a plurality of types of data are transmitted / received between transmission / reception devices, they are generally transmitted as independent serial data via individual systems, or a head portion of the transmission data ( A header indicating the destination, attribute, and the like of the data is added to the (starting portion), the data is multiplexed, and a predetermined data frame is transmitted after transmission. The receiving side analyzes the contents of the header attached to the data to determine the distribution destination of the data.

In particular, data transmission and reception between a microchip (an integrated circuit for data transmission and reception including a microprocessor) is performed in a parallel system or a universal asynchronous transmission and reception (U.S.A.).
ART), a clock-synchronous serial interface or the like is used, and when transmitting and receiving a plurality of types of data, for example, display data and arithmetic data via a small number of data line connections, the following software processing and hardware Performing wear processing.

That is, by using a serial transmission / reception interface, a header process is added to all target data by software processing, and protocol processing is performed to distinguish a plurality of types of data from each other, or a dedicated data processing is performed. The processing of adding a header is performed by hardware.

[0005]

However, as described above, when the header is added by software processing, when the data transfer speed of transmission data is high, the processing speed of the processor becomes an obstacle. However, there is a problem that header generation / addition cannot be performed smoothly. In addition, in the case of header addition by hardware, even if data to be handled is only one type of transmission / reception, the header is attached to each data, so that the overhead is not negligible.

An object of the present invention is to provide an interface circuit capable of transmitting and receiving many types of data between a plurality of chips at high speed with a small number of connection lines. It is.

Another object of the present invention is to provide an interface circuit capable of preventing a reduction in data transmission speed (data rate) due to addition of a flag, for example, suitable for handling non-voice data such as packet data and transmitting / receiving the same. To provide an interface circuit.

[0008]

To achieve the above object, the present invention provides an interface circuit for multiplexing and transmitting a plurality of types of data, comprising a plurality of storage means for individually storing the plurality of types of data. Means for arbitrating the read order of the plurality of types of stored data, means for generating a predetermined data header corresponding to each of the plurality of types of data, and the data header among the plurality of types of data. Determining means for determining data to which the data header is to be added and data to which the data header is not added; means for generating a first synchronization signal for each of the plurality of types of data; Means for generating a synchronizing signal, and the data to which the data header is added and the data to which the data header is not added are read in accordance with the reading order. Multiplexing means; and means for transmitting the multiplexed plural types of data in synchronization with the first synchronization signal. The discriminating means includes a specific storage among the plurality of storages. An interface circuit is provided for determining that the data stored in the means is data to which the data header is not added.

According to another aspect of the present invention, there is provided an interface circuit for receiving a plurality of types of multiplexed data, means for receiving a first synchronization signal and a second synchronization signal having a predetermined timing, Means for fetching the plurality of types of data transmitted in synchronization with the synchronization signal, and means for judging a data header added to the fetched data based on the presence or absence of the second synchronization signal. An interface circuit comprising: means for identifying the plurality of types of data based on the data header; and a plurality of storage means for individually storing the plurality of types of data based on the result of the identification. You.

According to another aspect of the present invention, there is provided an interface circuit for transmitting / receiving a plurality of types of multiplexed data, wherein a plurality of transmission data storage means for individually storing the plurality of types of data on a transmission side. Means for arbitrating the read order of the plurality of types of stored data, means for generating a predetermined data header corresponding to each of the plurality of types of data, and the data header among the plurality of types of data. Determining means for determining data to which the data header is to be added and data to which the data header is not added; means for generating a first synchronization signal for each of the plurality of types of data; Means for generating a synchronizing signal, and the data to which the data header is added and the data to which the data header is not added are arranged in accordance with the reading order. Means for the multiplexed, the multiplexed plural kinds of data are provided and means for transmitting in synchronism with the synchronizing signal of the first l, at the receiving side, the first l
Receiving the synchronization signal and the second synchronization signal, capturing the plurality of types of data transmitted in synchronization with the first synchronization signal, and determining whether the second synchronization signal is present. Means for determining a data header added to the fetched data, means for identifying the plurality of types of data based on the data header, and means for identifying the plurality of types of data based on the result of the identification. A plurality of reception data storage means for individually storing data, wherein the determination means does not add the data header to data stored in a specific storage means among the plurality of transmission data storage means. An interface circuit for determining data is provided.

[0011]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a schematic configuration of an entire serial interface circuit according to an embodiment of the present invention.
As shown in FIG.
(10) and a chip b (20). Each of these chips 10, 20 mutually transmits and receives data via the serial interface unit 15, 25. Each of the serial interface units has a data transmission unit and a data reception unit described later.

That is, the chip a (10) includes a central control unit (CPUa) 11 for controlling the entire chip,
The serial interface unit 15 operates under the control of (11). The serial interface unit 15 transmits data from the CPU a to a communication partner, and transmits data from the partner to the data transmission unit a (12). It has a data receiving unit a (13) for receiving. Similarly, the chip b (20) has a CPU b (21) and a serial interface unit 25 that operates under the control of the CPU b (21). The serial interface unit 25 transmits data from the CPU b to a communication partner. A data transmission unit b (22);
Data receiving unit b (2) for receiving data from the other party
3).

The serial interface unit 15,
In FIG. 25, serial data paths (signal lines) 35 and 45 are interposed between each data transmitting unit and the data receiving unit. Of these, the data transmitting unit a of the CPU a Is transmitted to the data transmission unit b of the CPU b, and the data and the like are transmitted from the data transmission unit b of the CPU b to the data transmission unit a of the CPU a via the path 45.

In this embodiment, it is assumed that the plurality of chips are in the same device. However, the present invention is not limited to this, and the configuration described here is provided in different devices. Needless to say, the present invention can be applied to a form in which a plurality of chips are mutually transmitted and received data.

FIG. 2 shows the serial interface section of the serial interface circuit according to the present embodiment.
FIG. 3 is a diagram illustrating an internal configuration of data transmission units 12 and 22. The data transmission circuit shown in FIG.
Four registers (transmission registers 0 to 3) 200 to 203 for storing the transmission data transmitted through 50, a status register 205 for determining whether these registers are empty, for example, Upon receiving a signal from the status register 205, arbitrates the transmission order of the data stored in the four registers (arbitration function) and generates a header corresponding to the arbitration and header generation unit 204, and generates an arbitration and header. A selector 207 for selecting data stored in the register according to the arbitration by the unit 204, a transmission buffer 208 for storing data for transmission to a communication partner, a frame generation unit 209 for generating a predetermined frame synchronization signal, and , A clock generator 206 that generates a synchronous clock for serial transmission
Consists of

FIG. 3 shows a serial interface section of the serial interface circuit according to the present embodiment.
2 shows an internal configuration of the data receiving units 13 and 23. As shown in the figure, the data transmission circuit includes a reception buffer 300 that receives serial data transmitted via the transmission buffer 208 of FIG. 2, and a header analysis unit 301 that analyzes a header portion of the serial data. , The frame detection & counter unit 302 which detects a frame signal and performs a predetermined count, and based on the analysis result by the header analysis unit 301, stores the data in the reception buffer 300 into four corresponding registers (reception registers 0 to 0). 3) A selector 303 for moving to 304 to 307, and a status register 308 for determining the presence or absence of data in the reception register.

The reception registers 0 to 3 (304 to 30)
7), and the output of the status register 308 is:
It is connected to the above-mentioned CPU via a data bus 350.

Therefore, the operation of transmitting and receiving serial data in the serial interface circuit according to the present embodiment will be described. Here, a case where 16-bit data is multiplexed up to four times using four registers in the serial interface unit will be described as an example.

FIG. 4 is a timing chart showing the transmission timing of serial data from the data transmission unit and the data reception timing of the data reception unit in the serial interface circuit according to the present embodiment. Further, the timing chart of FIG. 4 includes a transmission timing group indicated by reference numeral 450 and a reception timing group indicated by reference numeral 460.

The clock generator 206 shown in FIG. 2 generates a serial transmission synchronous clock TXCLK (401) having a repetition cycle shown at the top of FIG. This synchronous clock is received as RXCLK on the data receiving side (see FIG. 3). Also, transmission registers 0 to 3
The status of data storage in (200 to 203) is always determined by the status register 205. The transmission register here may be of, for example, a double buffer format, or may operate in a first-in first-out (FIFO) format. Therefore, the status register 205 stores the data storage states of these registers, in other words, the data has already been accumulated in the registers,
It monitors whether the data is ready to be read, or whether the register is empty and in which new data can be written, whether the data is being written, or whether the data is in a write-protected state. "Status"
To the arbitration & header generation unit 204 described later.

The arbitration & header generation unit 204 arbitrates the transmission order of the data stored in the register and generates a header (also referred to as a flag), which will be described later, based on the above determination result. For example, after starting this interface circuit, first, data of a predetermined length (here, 16 bits) is stored in the transmission register 2 (202), and then the transmission register 0 (20) is stored.
It is assumed that data of a predetermined length is accumulated twice consecutively in (0) and then data is stored in the transmission register 1 (201). In this case, the arbitration & header generation unit 204 instructs the selector 207 to read the data stored as described above from each register in the storage order.

At the same time, the arbitration & header generation unit 204 generates a header to be added to the head of each data according to whether or not a header is added, which is defined in advance for each transmission register. The generated header is sent to the frame generation unit 209 and stored in the header storage unit 208a. In the interface circuit according to the present embodiment, it is determined in advance that data stored in the transmission register 0 (200) does not have a header when transmitting to the other party.

The frame generator 209 generates a timing signal TXF (402) shown in FIG. 4 based on the synchronous clock TXCLK from the clock generator 206 and the header generated by the arbitration & header generator 204 described above. I do.
This timing signal TXF is, in FIG.
, And an l-th frame synchronization signal indicated by
A second frame synchronization signal indicating the start of data,
, And The first frame synchronization signal is composed of a synchronization (SYNC) pulse having a pulse width of one clock cycle of the synchronization clock TXCLK, and the second frame synchronization signal is also a signal having the same pulse width as the first frame synchronization signal. It is.

However, in the interface circuit according to the present embodiment, as described above, the transmission register 0 (200)
No header is added to the data from
Is transmitted in a state of “no header”. Therefore, as shown in FIG. 4, the frame generation unit 209 transmits the transmission register 0 in the second frame synchronization signal constituting the TXF signal (402).
(Corresponding to the dotted line in the figure) is not output.

On the other hand, the selector 207 switches the data path from each transmission register in accordance with the transmission order arbitrated by the arbitration & header generation unit 204, reads the data stored in the register, and transmits the read data. The data is sent to the transmission buffer 208 for each register. As described above, since the header corresponding to each data generated by the arbitration & header generation unit 204 is stored in the header storage unit 208a, the transmission data T
As XD, the data from each register
The multiplexed data to which the header is added is transmitted in synchronization with the frame synchronization signal. At this time, since the arbitration & header generation unit 204 does not generate a header for the data from the transmission register 0, the data from the transmission register 0 in the multiplexed data TXD is specifically described below. As shown, there is no header (flag).

For example, as shown in the timing chart of FIG. 4, for the transmission data TXD (403), "header 2" (because the header here is a maximum of four multiplexes,
Data “TX2 data” from the transmission register 2 (having a data length of 2 bits) (16 bits (D
_{0 to} D ₁₅ )), followed by two pieces of data “TX0 data” from the transmission register 0 without a header, followed by data “TX1 data” from the transmission register 1 with “header 1” added. "Comes. The “header” here is composed of identification bits of data to be multiplexed and transmitted, and the number of bits can be extended according to the number of multiplexes.

As described above, in the interface circuit according to the present embodiment, 16-bit data is multiplexed at a maximum of four times. The characteristic feature of the interface circuit is that “TX0” stored in the transmission register 0 is “TX0”. No header is added to "data", and only that data is multiplexed with other data and transmitted together with the frame synchronization signal.

Next, the operation of the data receiving side (the data receiving section in FIG. 3) will be described. The transmission data TXD and the timing signal TXF described above are input to the data receiving unit as a reception data RXD and a timing signal RXF together with a synchronization clock. That is, the data TXD shown in FIG. 4 is input as RXD to the reception buffer 300 and the header analysis unit 301 in FIG. 3, and the TXF is input as RXF to the frame detection & counter unit 302 at the same time.

The specific operation will be described. The reception buffer 300 and the header analyzer 301 transmit the transmission data TX shown in FIG.
D (403), the frame detection & counter 30
2 receives the signal of the frame synchronization signal TXF in FIG. 4, and the data receiving operation is started. At the same time as receiving the synchronization signal, the frame detection & counter section 302 starts counting operation from “0” in synchronization with the synchronization clock RXCLK as indicated by reference numeral 413 in FIG. When the count value reaches “1”, that is, at the second clock of RXCLK, the frame detection & counter unit 302 detects the presence or absence of a frame synchronization signal. The detection result here is sent to the header analysis unit 301.

When a synchronization signal exists in the received signal,
The frame detection & counter unit 302 clears the counter value, starts counting from “0” again, and returns to “F (16
Hex)). The header analysis unit 301
Receives the presence of this synchronization signal,
As shown by, the contents (header and data) of the header buffer are held. Then, the header analysis unit 3
01 analyzes the content of the held header and sends the analysis result to the selector 303. The header analysis unit 30
1 determines the type (four types) of data represented by a 2-bit header.

The selector 303 outputs a signal (load signal) for selecting a receiving register as a storage destination of data corresponding to the header based on the result of the analysis. For example, in FIG. 4, the first data “TX2 data” taken into the reception buffer 300 among the data of the reception buffer (RXD buf) indicated by reference numeral 412 is output from the selector 303 by the signal RXD_re.
g2 (416) is output. As a result, the selector 30
3, the data path is switched to the reception register 2 (306), and the data in the reception buffer 300 is transferred to the reception register 2.

The reception buffer 300 stores reception data in a serial format in synchronization with a reception clock.
This is a shift register having a 6-bit structure.
The reg2 signal (416) notifies the selector 303 of the timing at which the frame detection & counter unit 302 has completed the count operation for 16 clocks. Then, the selector 303 that has received this notification switches the data path to the reception register 2 as described above.
From 00 to the reception register 2 (306), RXD re
When the g2 signal is in the active state, data is loaded in a parallel format. Therefore, the reception buffer 3
In 00, the header is pushed out at the end of reception of one data, so that no data remains in the buffer.

On the other hand, after the first frame synchronization signal, the second
If no frame synchronization signal exists, the following reception operation is performed. That is, the frame detection & counter unit 302 receives the frame synchronization signal shown in FIG.
The count operation is started from “0” in synchronization with the synchronization clock RXCLK (see reference numeral 413 in FIG. 4). When the count value reaches “1” (second clock), the frame detection & counter section 302 cannot detect the frame synchronization signal, and continues counting as it is. That is, 2
The counter is not reset between the third clock and the third clock.

The header analysis section 301 receives the detection result of the absence of the second frame synchronization signal from the frame detection & counter section 302, and receives the data stored in the header analysis section 301 as a header buffer. (In the header buffer 411 of FIG. 4, T
X 0 (see the section marked (clr & hold))).

As described above, the frame detection & counter unit 302 outputs the data “TX0 data” from the transmission register 0 (200) in FIG. 2 without a header at the head of the data.
Is received and the selector 303 is notified of that fact. Therefore, the selector 303 selects l in order to select the receiving register in which the “TX0 data” is stored.
RXD reg0 (414) is output as an oad signal. As a result, the reception register 0
The data path is switched to (304), and the 16-bit data “TX0 data” captured second in the reception buffer (corresponding to RXD buf 412 in FIG. 4) is when the RXD reg0 signal is in the active state. Then, the data is transferred (loaded) to the reception register 0 in a parallel format via the selector 303.

The data transmission / reception processing for the 1st frame synchronization signal and the 2nd frame synchronization signal shown in FIG. 4 is the same as the case of the above-mentioned synchronization signal (when data without header is transmitted / received). The subsequent data transmission / reception processing for the first frame synchronization signal and the second frame synchronization signal is the same as that for the synchronization signal described above.

As described above, according to the present embodiment, a header is not added to the data stored in the transmission register 0 among the plurality of transmission registers, and only the data is added with the header. By multiplexing with other data and transmitting it together with the frame synchronization signal, various types of data can be transmitted and received at high speed between chips, for example.

Further, since the header is not added to all of the various types of data, it is possible to prevent a reduction in the data transmission speed due to the header. Particularly, in a situation where only data without a header is continuously transmitted, there is an effect that data transmission at a maximum speed is possible.

Further, since the data transmission / reception section can be seen only as a plurality of serial interfaces from software for controlling the interface circuit, a special protocol for data multiplexing is not required, and the processing for that purpose is reduced. Therefore, high-speed data transmission / reception can be realized.

[0041]

As described above, according to the present invention,
When multiplexing a plurality of data to which a data header is added in accordance with a predetermined read order and transmitting the multiplexed plurality of data in synchronization with a synchronization signal, a specific storage unit among a plurality of storage units is used. By multiplexing the stored data without adding a data header, it is possible to prevent a decrease in the data transmission speed due to the addition of a header and to perform data transmission at the maximum speed, and in particular to increase the number of data multiplexes. In this case, the effect of improving the transmission speed by data transmission without the addition of a header is significantly increased.

According to another aspect of the present invention, a data header added to received data is determined based on the presence or absence of a synchronization signal synchronized with data, and a plurality of data are determined based on the data header. Since identification is performed, various types of data can be determined at high speed, and they can be reliably received.

Further, on the transmitting side, a plurality of data to which a data header has been added are multiplexed in accordance with a predetermined read order, and a plurality of multiplexed data are transmitted in synchronization with a synchronization signal. Of the storage means, multiplexing is performed without adding a data header to data stored in a specific storage means, and the receiving side determines whether or not the received data has a synchronization signal synchronized with the data header. By discriminating the data header added to the received data and identifying multiple data based on the data header, it is possible to prevent the data transmission speed from being reduced due to the addition of the header, and to perform data transmission at the maximum speed. In addition to this, various types of data can be determined at high speed and received.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an entire serial interface circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an internal configuration of a data transmission unit of the serial interface unit according to the embodiment.

FIG. 3 is a diagram showing an internal configuration of a data receiving unit of the serial interface unit according to the embodiment.

FIG. 4 is a timing chart showing transmission timing and reception timing of data in the serial interface circuit according to the embodiment.

[Explanation of symbols]

10, 20 ... chip, 11, 21 ... central control unit (CP
U), 12, 22 ... data transmission unit, 13, 23 ... data reception unit, 15, 25 ... serial interface unit, 3
5, 45: serial data path, 200 to 203: transmission registers 0 to 3, 204: arbitration and header generation unit, 20
5 status register, 206 clock generator,
207, 303 ... selector, 208 ... transmission buffer, 2
09 ... frame generation unit, 250, 350 ... data bus,
300: reception buffer, 301: header analysis unit, 302
... Frame detection & counter section, 304-307 ... Receive registers 0-3, 308 ... Status register

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5B077 BA02 GG16 HH04 MM02 5K033 AA01 CA13 DA12 DB11 DB13 DB17 5K034 AA01 DD01 FF01 GG05 HH01 HH02 HH12 HH17 HH26 KK13 MM14 MM18 MM31 MM35 PP01 H04H05H01

Claims (5)

[Claims] 1. An interface circuit for multiplexing and transmitting a plurality of types of data, a plurality of storage units for individually storing the plurality of types of data, and a unit for arbitrating read order of the plurality of types of stored data. Means for generating a predetermined data header corresponding to each of the plurality of types of data; and discriminating, from the plurality of types of data, data to which the data header is added and data to which the data header is not added. Determining means for generating a first synchronization signal for each of the plurality of types of data; means for generating a second synchronization signal according to the presence or absence of the data header; and the data header is added. Data and the data
Means for multiplexing data to which a header is not added in accordance with the read order; and means for transmitting the multiplexed plurality of types of data in synchronization with the first synchronization signal. An interface circuit that determines that data stored in a specific one of the plurality of storage units is data to which the data header is not added. 2. For the data to which the data header is added, the second synchronization signal corresponding to the data header is generated. For the data to which the data header is not added, the data synchronization is performed. 2. The interface circuit according to claim 1, wherein the second synchronization signal corresponding to the header is not generated. 3. An interface circuit for receiving a plurality of types of multiplexed data, a means for receiving a first synchronization signal and a second synchronization signal having a predetermined timing, and synchronizing with the first synchronization signal. Means for capturing the plurality of types of data transmitted as described above; means for determining a data header added to the captured data based on the presence or absence of the second synchronization signal; An interface circuit comprising: means for identifying the plurality of types of data based on a header; and a plurality of storage means for individually storing the plurality of types of data based on a result of the identification. 4. The plurality of types of data are stored when a count value of a predetermined counter matches a data length indicated by the data or a data length indicated by the data and a data header. 4. The interface circuit according to claim 3, wherein said interface circuit is stored in said means. 5. An interface circuit for transmitting and receiving a plurality of types of multiplexed data, wherein at a transmission side, a plurality of transmission data storage means for individually storing the plurality of types of data; Means for arbitrating the read order of the data, means for generating a predetermined data header corresponding to each of the plurality of types of data, and data to which the data header is added and the data among the plurality of types of data A determination unit for determining data to which a header is not added; a unit for generating a first synchronization signal for each of the plurality of types of data; and a unit for generating a second synchronization signal according to the presence or absence of the data header And the data to which the data header is added and the data
Means for multiplexing the data to which the header is not added in accordance with the read order; and means for transmitting the multiplexed plural types of data in synchronization with the first synchronization signal. Means for receiving the first synchronization signal and the second synchronization signal; means for capturing the plurality of types of data transmitted in synchronization with the first synchronization signal; presence or absence of the second synchronization signal Means for determining a data header added to the fetched data, means for identifying the plurality of types of data based on the data header, based on a result of the identification. A plurality of received data storage means for individually storing a plurality of types of data, wherein the determination means, among the plurality of transmission data storage means,
An interface circuit for determining data stored in a specific storage means as data to which the data header is not added.