JPH05327500A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To improve the state setting for measuring a digital logic circuit in the semiconductor integrated circuit containing a digital logic circuit and the A/D conversion circuit. CONSTITUTION:Analog voltage Vi is inputted from a terminal 51, host reference voltage Vp is inputted from a terminal 52, and low-order reference voltage Vm is inputted from a terminal 53. In voltage comparison circuits 2 and 3, the levels of the analog voltage Vi, the host reference voltage Vp and the low- order reference voltage Vm are compared to be inputted to a digital waveform generation circuit 5 and to selectors 6-1 to 6-n as control signals. When Vm<=Vi<=Vp, the digital conversion value of the A/D conversion section 1 is outputted through a digital waveform generation circuit 5 and through terminals 54-1 to 54-n. On the other hand, when Vi<Vm or Vp<Vi, n-pseudo digital values to be outputted from the digital waveform generation circuit 5 is outputted through the selector circuits 6-1 to 6n and through the terminals 54-1 to 54-n. The terminals 54-1 to 54-n are connected to a logic circuit to be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion circuit,
In particular, it relates to an A / D conversion circuit equipped with a test circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional A / D conversion circuit has a terminal 5 to which an analog input voltage V _i is input.
1, a terminal 52 to which the upper reference voltage V _p is input, a terminal 53 to which the lower reference voltage V _m is input, and terminals 54-1 and 54-2, to which n (positive integer) digital values are output,
, 54-n, the A / D conversion circuit 10 is provided, and the analog input voltage V _i input to the terminal 51 is input.
, N terminals 54-1, 54-2, ..., 5
If the digital value output from 4-n is M, and the analog voltage is at a level below the upper reference voltage V _p and above the lower reference voltage V _m , the following equation holds.

M = V _i / [(V _p −V _m ) / 2 ⁿ ] ... (1) V _m ≦ V _i ≦ V _p …………………………………… (2) FIG. 4 is a block diagram showing a semiconductor integrated circuit 11 incorporating the A / D conversion circuit 10 and the digital logic circuit 9 described above. As a measuring device for this kind of semiconductor integrated circuit 11, a digital LSI tester for measuring the logical operation of the digital logic circuit 9, an analog LSI tester for measuring the operation of an analog circuit, and both a digital circuit and an analog circuit are measured. There is a digital / analog mixed tester, etc., and the semiconductor integrated circuit 11 as shown in FIG.
In the above, a digital / analog mixed tester is used, or the digital logic circuit 9 is measured using a digital LSI tester, and the analog circuit is measured using an analog LSI tester. .. However, the digital / analog mixed tester is very expensive, and the latter method is generally used.

Generally, in the digital logic circuit 9, each signal takes two values of "H" level and "L" level.
The actual binary voltage values of the “H” level and the “L” level are different depending on the case, such as the CMOS interface level, the TTL interface level and the ECL interface level, and may be mixed. When measuring the digital logic circuit 9, it is necessary to take care so that an analog circuit that cannot be measured, that is, the A / D conversion circuit 10 or the like does not adversely affect the digital logic circuit 9. Therefore, it is necessary to apply an appropriate "H" level or "L" level voltage as the analog voltage V _i and input a digital signal corresponding to the value to the digital logic circuit 9.
For example, when the analog voltage V _i is “H” level, all digital signal outputs are “H” level, and when the analog voltage V _i is “L” level, all digital signal outputs are “L” level. Thus, the operation of the A / D conversion circuit 10 is approximated to the operation of the digital logic circuit 9.

[0005]

DISCLOSURE OF THE INVENTION The above-mentioned conventional A / D
In the conversion circuit, the digital logic circuit and the conventional A /
In the case of a semiconductor integrated circuit including a D conversion circuit, when the digital logic circuit and the A / D conversion circuit are measured by different testers, the A / D conversion circuit is measured during the measurement of the digital logic circuit. 2 digital outputs
Since only the value can be obtained, the operation of the entire circuit of the semiconductor integrated circuit can be measured, or the digital logic circuit and the A
There is a drawback that it is difficult to measure the operation at the connection point of the / D conversion circuit.

[0006]

The A / D conversion circuit according to the present invention corresponds to the analog input voltage V _i , the upper reference voltage V _p and the lower reference voltage V _m , in response to the analog input voltage V _i . In the A / D conversion circuit that outputs the corresponding n (positive integer) columns of digital conversion values, the normal operation state is a state in which the input level of the analog input voltage V _i satisfies the level relationship of V _m ≤V _i ≤V _p. As an A / D for converting the analog input voltage V _i into a digital value of n columns and outputting
Converter, the analog input voltage V _i , the upper reference voltage V
By inputting _p and the lower reference voltage V _m , the voltage level relationship between the analog input voltage V _i and both reference voltages V _p and V _m is compared, and the level of the analog input voltage V _i is the V _m. The first control signal is output in a state where the level relationship of ≦ V _i ≦ V _p is satisfied, and the level of the analog input voltage V _i is in the level relationship of V _i <V _m or V _i > V _p . A digital value selection control unit that outputs a second control signal and an operation that is stopped upon receiving the first control signal, receives the second control signal, and generates and outputs a pseudo digital value of n columns. The digital waveform generator, the n-column digital conversion values output from the A / D converter, and the n-column pseudo digital values output from the digital waveform generator are input, and the first control signal is input. Through the n columns of digitizers Digital conversion value is selected and outputted via the second control signal, and a digital value selection section for selecting and outputting the pseudo digital value of the n-th column is outputted.

In the digital value selection control section, the analog input voltage V _i is input to the non-inverting input terminal and the upper reference voltage V _p is input to the inverting input terminal, and the analog input voltage. The voltage V _i is input to the inverting input terminal,
It comprises a second voltage comparison circuit to which the lower reference voltage V _m is inputted to the non-inverting input terminal, and an OR circuit for taking the logical sum of the outputs of the first and second voltage comparison circuits and outputting it. Alternatively, the digital waveform generator may count a predetermined clock signal via a second control signal input from the digital value selection controller and output it as an address signal. A ROM for outputting a digital value corresponding to the address signal as the pseudo digital value may be provided.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, the terminal 51 to which the analog input voltage V _i is input, the upper reference voltage V _p.
Corresponding to the terminal 52 to which is input, the terminal 53 to which the lower reference voltage V _m is input, and the terminals 54-1, 54-2, ..., 54-n to which n (positive integer) digital signals are output. The A / D conversion unit 1, the voltage comparison circuits 2 and 3,
An OR circuit 4, a digital waveform generating circuit 5, and n selector circuits 6-1 to 6-n are provided.

In FIG. 1, the analog input voltage V _i input to the terminal 51 is input to the A / D converter 1 and also the non-inverting input terminal of the voltage comparison circuit 2 and the inverting input terminal of the voltage comparison circuit 3. Entered in. The upper reference voltage V _p input from the terminal 52 is also input to the inverting input terminals of the A / D conversion unit 1 and the voltage comparison circuit 2, and the lower reference voltage V _m input from the terminal 53 is also A / D. It is input to the non-inverting input terminals of the D conversion unit 1 and the voltage comparison circuit 3. The voltage comparison circuit 2 compares the levels of the analog voltage V _i and the upper reference voltage V _p, and the voltage comparison circuit 3 compares the levels of the analog voltage V _i and the lower reference voltage V _m , respectively. The level signal output from the voltage comparison circuit is input to the OR circuit 4 to be ORed, and the output of the OR is used as a control signal for the digital waveform generating circuit 5 and the n selector circuits 6-1 to 6-6. Input to -n.

Now, as a level relationship between the analog input voltage V _i , the upper reference voltage V _p and the lower reference voltage V _m , V _m
When ≦ V _i ≦ V _p , as the digital signal output by the A / D conversion unit 1, digital values of n columns corresponding to the analog input voltage V _i are output. Also, V _m ≤V _i ≤V
_Since it is _p , the level signals output from the voltage comparison circuits 2 and 3 are both at "L" level, and therefore the output of the OR circuit 4 is also output at "L" level. The output of the “L” level OR circuit 4 is used as a control signal.
Digital waveform generating circuit 5 and n selector circuits 6-1
Input to 6-n. In response to this "L" level control signal, the operation of the digital waveform generating circuit 5 is stopped, and it is output from the A / D converter 1 and input to the n selector circuits 6-1 to 6-n. The selected digital value is selected via the control signal, and each of the terminals 54-1 to 54-54 is selected.
It is output via -n.

When V _i <V _m or V _p <V _i , one of the level signals output from the voltage comparison circuits 2 and 3 is output as "H" level. The output level of the OR circuit 4 becomes "H" level, and this "H" level control signal is similarly supplied to the digital waveform generating circuit 5 and the n selector circuits 6-1 to 6-.
input to n. As a result, the digital waveform generating circuit 5 is put into an operating state, and the pseudo digital values of the n-th column output from the digital waveform generating circuit 5 are input to the corresponding selector circuits 6-1 to 6-n, and the selector circuit 6- In 1 to 6-n, instead of the digital value output from the A / D conversion unit 1, the digital waveform generation circuit 5 is used.
The pseudo digital value output by the selected is selected and output via the terminals 54-1 to 54-n.

Therefore, as shown in FIG. 4, when the present invention is applied to a semiconductor integrated circuit including an A / D conversion circuit and a digital logic circuit, in the situation where only the digital logic circuit is measured. As described above, the level relationship between the analog input voltage V _i and the lower reference voltage V _m is set to V _i <V _m , or the level relationship between the analog input voltage V _i and the upper reference voltage V _p is V. with _p <V _i, can be as if in the or as a / D conversion circuit operates to implement a single measurement.

In the present embodiment, the digital waveform generating circuit 5 operates when the control signal output from the OR circuit 4 is at "H" level and stops when it is at "L" level. , Selector circuits 6-1 to 6-1
6-n, the digital waveform signal output from the digital waveform generating circuit 5 is selected when the control signal is at the "H" level, and A / A is selected when the control signal is at the "L" level.
Although the digital value output from the D conversion unit 1 is selected, the level of the control signal, the digital generation circuit 5 and the selector circuits 6-1 to 6-n are selected.
The relationship with the action of is only an example, and does not limit the present invention.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing this embodiment. As shown in FIG. 2, in this embodiment, a terminal 51 to which an analog input voltage V _i is input, a terminal 52 to which an upper reference voltage V _p is input, a terminal 53 to which a lower reference voltage V _m is input, and n. Terminal 54-where (positive integer) digital values are output
, 54-2, ..., 54-n, the A / D conversion unit 1, the voltage comparison circuits 2 and 3, the OR circuit 4, and the R circuit.
A digital waveform generating circuit 5 including an OM 7 and a binary counter 8 and n selector circuits 6-1 to 6-n are provided.

As is apparent from FIG. 2, in this embodiment, the digital waveform generating circuit 5 is composed of the ROM 7 and the binary counter 8. Other components are the same as those in the above-mentioned first embodiment. As for the operation of the digital waveform generating circuit 5, when the control signal input from the OR circuit 4 is at "H" level, counting is started in the binary counter circuit 8 by the clock signal CL input from the outside, and the relevant counter is counted. The ROM value written in the address corresponding to the numerical value is input to the corresponding selector circuits 6-1 to 6-n as a digital waveform signal output from the digital waveform generating circuit 5.
Therefore, by writing a pseudo digital value corresponding to the digital value output from the A / D converter 1 in the ROM 7 in advance, a complicated signal waveform such as a video image signal can be simulated. Even in such a case, the digital waveform generating circuit 5 can easily generate and output the pseudo digital value, and there is an advantage that the measurement of the digital logic circuit can be executed in a state closer to the actual operation. ..

[0017]

As described above, the present invention is applied to a semiconductor integrated circuit incorporated in a state of coexisting with a digital logic circuit and uses a control signal generated through an analog input voltage outside the reference level. The digital logic circuit is provided with a means for outputting a pseudo digital value and a digital value selecting means for selecting and outputting either the A / D conversion output value or the pseudo digital value via the control signal. Even in the case of only the measurement, there is an effect that the measurement can be performed by setting the state as if the A / D conversion function is functioning.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a block diagram of a semiconductor integrated circuit including an A / D conversion circuit and a digital logic circuit.

[Explanation of symbols]

 1 A / D converter 2, 3 Voltage comparison circuit 4 OR circuit 5 Digital waveform generation circuit 6-1 to 6-n Selector circuit 7 ROM 8 Binary counter 9 Digital logic circuit 10 A / D conversion circuit 11 Semiconductor integrated circuit

Claims (3)

[Claims] 1. An analog input voltage V _i and an upper reference voltage V
_In the A / D conversion circuit that outputs digital conversion values of n (positive integer) columns corresponding to the analog input voltage V _i in response to the inputs of _p and the lower reference voltage V _m, the input of the analog input voltage V _i The level is V _m ≤V _i
An A / D converter that converts the analog input voltage V _i into a digital value of n columns and outputs the analog input voltage V _i , assuming that the state satisfying the level relationship of ≦ V _p is a normal operation state, the analog input voltage V _i , and the upper reference voltage The analog input voltage V _i is input by inputting V _p and the lower reference voltage V _m.
If, by comparing the voltage level relationship between the two reference voltages V _p and V _m, the level of the analog input voltage V _i is the V _m
In a state in which the first control signal is output in a state satisfying the level relationship of ≦ V _i ≦ V _{p and} the level of the analog input voltage V _i is in the level relationship of V _i <V _m or V _i > V _p A digital value selection control unit that outputs a second control signal, and an operation is stopped upon receipt of the first control signal, and upon receipt of the second control signal, an n-column pseudo digital value is generated and output. The digital waveform generator, the n-column digital converted values output from the A / D converter, and the n-column pseudo digital values output from the digital waveform generator are input, and the first control signal is input. Select and output the digital conversion value of the n-th column via
An A / D conversion circuit, comprising: a digital value selection unit that selects and outputs the pseudo digital value of the n-th column via the second control signal. 2. The digital value selection control section includes: a first voltage comparison circuit in which an analog input voltage V _i is input to a non-inverting input terminal and a higher-order reference voltage V _p is input to an inverting input terminal; and an analog input. The voltage V _i is input to the inverting input terminal and the lower reference voltage V _m is input to the non-inverting input terminal, and the output of the first and second voltage comparing circuits is ORed. And an OR circuit for outputting the output.
The described A / D conversion circuit. 3. A binary count in which the digital waveform generating section counts a predetermined clock signal via a second control signal input from the digital value selection control section and outputs it as an address signal; 3. The A / D conversion circuit according to claim 1, further comprising a ROM that outputs a digital value corresponding to a signal as the pseudo digital value.