JPH05327163A - Mounting structure of electronic component - Google Patents
Mounting structure of electronic componentInfo
- Publication number
- JPH05327163A JPH05327163A JP12657092A JP12657092A JPH05327163A JP H05327163 A JPH05327163 A JP H05327163A JP 12657092 A JP12657092 A JP 12657092A JP 12657092 A JP12657092 A JP 12657092A JP H05327163 A JPH05327163 A JP H05327163A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- substrate
- pad
- pattern
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子部品を基板のパッ
ドに半田付けを行う際、該電子部品を所定の状態で支持
する支持パターンが備えられた電子部品の実装構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of an electronic component provided with a support pattern for supporting the electronic component in a predetermined state when the electronic component is soldered to a pad of a substrate.
【０００２】プリント基板に電子部品を実装する場合
は、一般的に、プリント基板に形成されたパッドに所定
量のクリーム半田を塗布し、半田付けすべき端子を所定
のパッドに当接させるよう電子部品をプリント基板に載
置し、ボンディング槽に挿入させ、クリーム半田を溶融
させ、端子とパッドとを半田によって固着させることが
行われる。When mounting an electronic component on a printed circuit board, generally, a predetermined amount of cream solder is applied to a pad formed on the printed circuit board, and a terminal to be soldered is contacted with the predetermined pad. The components are placed on a printed circuit board, inserted into a bonding bath, the cream solder is melted, and the terminals and pads are fixed by soldering.
【０００３】このような電子部品の端子をプリント基板
のパッドに半田付けする際、それぞれのパッドに塗布さ
れたクリーム半田の溶融が同時に進行されない場合は、
実装された電子部品の底面がプリント基板の表面に対し
て傾斜し、端子とパッドとの間に固着される半田量が不
均一となり、例えば、熱膨張によって実装された電子部
品とプリント基板との間に伸縮が生じた場合は、半田量
の少ない箇所の固着部が切離されることが生じる。When soldering the terminals of such an electronic component to the pads of the printed board, if the cream solder applied to the pads is not melted at the same time,
The bottom surface of the mounted electronic component is inclined with respect to the surface of the printed circuit board, and the amount of solder fixed between the terminal and the pad becomes uneven. When expansion and contraction occur between them, the fixed portion at a portion with a small amount of solder may be separated.
【０００４】そこで、このような端子をパッドにクリー
ム半田によって固着する場合は、それぞれの固着部に於
ける半田量が均一になるように半田付けが行われるよう
にすることが重要となる。Therefore, when such a terminal is fixed to the pad by cream solder, it is important to perform the soldering so that the amount of solder in each fixing portion is uniform.
【０００５】[0005]
【従来の技術】従来は図４の(a)(b)の従来の説明図に示
すように形成されていた。図４の(a)(b) は側面断面図
である。2. Description of the Related Art Conventionally, it was formed as shown in the conventional explanatory views of FIGS. 4A and 4B are side sectional views.
【０００６】図４の(a) に示すように、基板1 の表面1A
に形成されたパッド2 には電子部品3 の底面3A設けられ
た端子4 を対応させ、半田10によって固着することが行
われていた。As shown in FIG. 4 (a), the surface 1A of the substrate 1 is
It has been performed that the terminals 4 provided on the bottom surface 3A of the electronic component 3 are made to correspond to the pads 2 formed on, and are fixed by the solder 10.
【０００７】また、基板1 の表面1Aには半田付けすべき
パッド2 の表面を露出させ、その他の箇所は全面が厚み
t1の塗膜となるソルダーレジスト7 によって覆われるよ
うに形成され、実装すべき電子部品3 を位置決めするた
めの厚みt2の塗膜となる白色のマーキング8 が形成され
ている。Further, the surface of the pad 2 to be soldered is exposed on the surface 1A of the substrate 1, and the other parts are entirely thick.
A white marking 8 is formed so as to be covered with a solder resist 7 that serves as a coating film of t1 and serves as a coating film of thickness t2 for positioning the electronic component 3 to be mounted.
【０００８】そこで、通常、電子部品3 を実装する場合
は、電子部品3 の底面のほぼ中央となる箇所に粘着テー
プなどによって形成されるスペーサ11を設け、パッド2
の表面に所定の厚みのクリーム半田を塗布し、マーキン
グ8 によって表示された箇所に電子部品3 を位置決め
し、電子部品3 の底面3Aをスペーサ11によって支持させ
た状態にすることで、例えば、基板1 をボンディング槽
に挿入することで加熱し、クリーム半田を溶融させるこ
とで端子4 をパッド2 に半田付けすることが行われてい
た。Therefore, when mounting the electronic component 3, usually, a spacer 11 formed of an adhesive tape or the like is provided at a position substantially at the center of the bottom surface of the electronic component 3, and the pad 2
By applying cream solder of a predetermined thickness to the surface of the electronic component, positioning the electronic component 3 at the location indicated by the marking 8, and making the bottom surface 3A of the electronic component 3 supported by the spacer 11, It was performed by inserting 1 into the bonding bath to heat it and melting the cream solder to solder the terminal 4 to the pad 2.
【０００９】この場合、スペーサ11高さH2はパッド2 の
表面と端子4 との間に所定の間隙Sが保たれるよう、H2
＝(H1 ＋S)−t1に形成されていた。In this case, the height H2 of the spacer 11 is set to H2 so that a predetermined gap S is maintained between the surface of the pad 2 and the terminal 4.
= (H1 + S) -t1.
【００１０】[0010]
【発明が解決しようとする課題】しかし、このような電
子部品3 は一旦半田によって固着されたものを障害など
によって新たな電子部品3 と交換する場合が生じる。However, such an electronic component 3 once fixed by solder may be replaced with a new electronic component 3 due to a failure or the like.
【００１１】このような交換に際しては、新たな電子部
品３の半田付けは人手によって行われることになるた
め、図４の(b) に示すように、位置決めされた電子部品
3 を矢印P のように押圧し、半田鏝によって半田付けす
ることが行われる。At the time of such replacement, since the soldering of the new electronic component 3 is performed manually, as shown in FIG.
3 is pressed as shown by arrow P, and soldering is performed with a soldering iron.
【００１２】この場合、矢印P の押圧がスペーサ11の直
上に行われないと、電子部品3 は傾斜し、一方のパッド
2 と端子4 との間隙S がS1と大きく、他方の間隙S がS2
と小さくなる。In this case, unless the arrow P is pressed directly above the spacer 11, the electronic component 3 tilts and one pad
2 has a large gap S between terminal 4 and S1, and the other gap S is S2.
Becomes smaller.
【００１３】したがって、半田付けによる半田の量が異
なり、不均一な半田付けにより、前述のような熱膨張に
よって亀裂が生じるなど問題を有していた。更に、この
ようなスペーサ11を形成するためには、基板の製造工程
に於いてスペーサ11を形成する余分な工程が加わること
でコストアップとなる問題を有していた。Therefore, there is a problem in that the amount of solder due to soldering is different and the uneven thermal soldering causes cracks due to the above-mentioned thermal expansion. Further, in order to form such a spacer 11, there is a problem that an extra step of forming the spacer 11 is added in the manufacturing process of the substrate, resulting in an increase in cost.
【００１４】そこで、本発明では、電子部品の半田付け
を容易にし、かつ、品質の向上を図ること共に、コスト
ダウンを図ることを目的とする。Therefore, it is an object of the present invention to facilitate the soldering of electronic parts, improve the quality, and reduce the cost.
【００１５】[0015]
【課題を解決するための手段】図１は本発明の原理説明
図であり、図１に示すように、基板1 の表面1Aに配設さ
れたパッド2 と、電子部品3 の底面3Aに形成された端子
4 とを半田付けによって固着することで該電子部品3 を
該基板1 に実装する電子部品の実装構造であって、所定
の前記端子4 を前記パッド2 に対応させることで前記電
子部品3 を前記表面1Aに押圧した時、該端子3 と該パッ
ド2 との間に平行な所定の間隔S が保持されるよう該底
面3Aの複数の箇所を支持する支持パターン5 が該表面1A
に配設されるように、また、前記支持パターン5 が前記
表面1Aに配設されたダミーパターン6 と、該ダミーパタ
ーン6 の上層に積層されたソルダーレジスト7 と、該ソ
ルダーレジスト7 の上層に更に積層されるマーキング8
とによって形成されるように構成する。FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1, pads 2 arranged on the surface 1A of a substrate 1 and a bottom surface 3A of an electronic component 3 are formed. Terminal
4 is a mounting structure of an electronic component in which the electronic component 3 is mounted on the substrate 1 by fixing the electronic component 3 to the pad 2 by soldering the electronic component 3 to the pad 2. When pressed against the surface 1A, the support pattern 5 supporting a plurality of locations on the bottom surface 3A is maintained so that a predetermined parallel spacing S is maintained between the terminal 3 and the pad 2.
In addition, the support pattern 5 is provided on the surface 1A, the dummy pattern 6 is provided on the surface 1A, the solder resist 7 is laminated on the dummy pattern 6, and the solder resist 7 is provided on the solder resist 7. Further stacked markings 8
And is formed by.
【００１６】このように構成することによって前述の課
題は解決される。The above-mentioned problems can be solved by such a configuration.
【００１７】[0017]
【作用】即ち、所定の端子4 をパッド2 に対応させるこ
とで電子部品3 を基板1 の表面1Aに押圧した時、端子3
とパッド2 との間に平行な所定の間隔S が保持されるよ
う電子部品3 の底面3Aの複数の箇所を支持する支持パタ
ーン5 が基板1 の表面1Aに配設されるように、しかも、
支持パターン5 がダミーパターン6 と、ソルダーレジス
ト7 と、マーキング8 とによって形成されるようにした
ものである。Function: That is, when the electronic component 3 is pressed against the surface 1A of the substrate 1 by making the predetermined terminal 4 correspond to the pad 2, the terminal 3
The support pattern 5 for supporting a plurality of locations on the bottom surface 3A of the electronic component 3 is arranged on the front surface 1A of the substrate 1 so that a predetermined parallel distance S is maintained between the pad 2 and the pad 2, and
The support pattern 5 is formed by the dummy pattern 6, the solder resist 7, and the marking 8.
【００１８】したがって、電子部品を位置決めすること
で押圧する箇所が電子部品3 の中央でない箇所を押圧し
ても、電子部品が傾斜することがないように支持するこ
とが行え、従来のような端子とパッドとの間に形成され
る間隙に差が生じることを防ぐことができ、品質の向上
が図れ、また、支持パターン5 は、基板1 を製造する製
造工程に於けるダミーパターン6 と、ソルダーレジスト
7 と、マーキング8 とによって形成されるため、特に、
支持パターン5 を形成するための製造工程を新たに追加
することなく、通常の基板の製造工程によって容易に形
成することが行え、コストダウンが図れることになる。Therefore, by positioning the electronic component, it is possible to support the electronic component so that the electronic component does not tilt even if the position to be pressed is not the center of the electronic component 3. It is possible to prevent a gap from being formed between the pad and the pad, which improves quality, and the support pattern 5 is formed by the dummy pattern 6 and the solder in the manufacturing process of manufacturing the substrate 1. Resist
Since it is formed by 7 and the marking 8,
Without adding a new manufacturing process for forming the support pattern 5, the supporting pattern 5 can be easily formed by a normal substrate manufacturing process, and the cost can be reduced.
【００１９】[0019]
【実施例】以下本発明を図２および図３を参考に詳細に
説明する。図２は本発明による一実施例の説明図で、
(a) は側面図,(b1) は基板の平面図,(b2) は(b1)のA-A
断面図, 図３の(a)(b)(c) は本発明の支持パターンの製
造工程図である。全図を通じて、同一符号は同一対象物
を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to FIGS. FIG. 2 is an explanatory view of an embodiment according to the present invention,
(a) is a side view, (b1) is a plan view of the substrate, (b2) is the AA of (b1).
Sectional views and FIGS. 3 (a), 3 (b) and 3 (c) are manufacturing process diagrams of the support pattern of the present invention. Throughout the drawings, the same reference numerals denote the same objects.
【００２０】図３の(a) に示すように、基板1 には導電
材より成るダミーパターン6 と、ダミーパターン6 を覆
うように積層された絶縁材より成るソルダーレジスト7
と、ソルダーレジスト7 に塗布された白色のペイントよ
り成るマーキング8 とによって形成された支持パターン
5 を設け、支持パターン5 によって電子部品3 の底面1A
を均一に保持することで、電子部品3 の端子4 と基板1
の表面1Aに形成されたパッド2 との間に半田付けを行う
ための間隙S が形成されるようにしたものである。As shown in FIG. 3A, the substrate 1 has a dummy pattern 6 made of a conductive material, and a solder resist 7 made of an insulating material laminated so as to cover the dummy pattern 6.
And the support pattern formed by the markings 8 made of white paint applied to the solder resist 7.
5 is provided, and the bottom surface 1A of the electronic component 3 is
By holding the terminals evenly, the terminals 4 of the electronic component 3 and the board 1
A gap S 2 for soldering is formed between the pad 2 and the pad 2 formed on the surface 1A.
【００２１】また、パッド2 は(b1)(b2)に示すように、
基板1 の表面1Aを覆うように積層されたソルダーレジス
ト7 から露出されるように形成され、支持パターン5 は
パッド2 の配列された箇所を避けるように、しかも、電
子部品3 の底面3Aの領域内に配設され、支持パターン5
によって電子部品3 の底面3Aが少なくとも3 箇所で支持
されるように形成されている。The pad 2 is, as shown in (b1) and (b2),
The support pattern 5 is formed so as to be exposed from the solder resist 7 laminated so as to cover the front surface 1A of the substrate 1, and the support pattern 5 is formed so as to avoid the portion where the pads 2 are arranged, and the area of the bottom surface 3A of the electronic component 3. Arranged in the support pattern 5
Is formed so that the bottom surface 3A of the electronic component 3 is supported at at least three places.
【００２２】したがって、電子部品3 を矢印P のように
基板1 の表面1Aに押圧しても、電子部品3 が傾斜するこ
とがないので、常に、端子4 とパッド2 との間に所定の
間隙S の形成が行え、前述のような半田鏝による半田に
際して、半田付けの量が不均一となることを避けること
ができる。Therefore, even if the electronic component 3 is pressed against the surface 1A of the substrate 1 as shown by the arrow P, the electronic component 3 does not incline, so that a predetermined gap is always provided between the terminal 4 and the pad 2. S can be formed, and it is possible to avoid uneven soldering amount when soldering with the soldering iron as described above.
【００２３】また、このような支持パターン5 の形成
は、図３の(a) に示すように、先づ、基板1 の表面1Aに
導電材によるパッド2 を形成する時、同時にダミーパタ
ーン6の形成を行う。Further, as shown in FIG. 3 (a), the formation of such a support pattern 5 is performed at the same time when the pad 2 made of a conductive material is formed on the surface 1A of the substrate 1 at the same time as the dummy pattern 6 is formed. Form.
【００２４】次に、基板1 の表面を覆う絶縁材による厚
みt1のソルダーレジスト7 の積層に際しては、ダミーパ
ターン6 はソルダーレジスト7 によって完全に覆われる
ようにし、パッド2 はソルダーレジスト7 から露出され
るようにする。Next, when laminating the solder resist 7 having a thickness t1 with the insulating material covering the surface of the substrate 1, the dummy pattern 6 is completely covered with the solder resist 7, and the pad 2 is exposed from the solder resist 7. To do so.
【００２５】最後に、白色のペイントによる厚みt2のマ
ーキング8 の塗布は、電子部品3 の実装位置決めとなる
マークと同時に、ダミーパターン6 の上層にマーキング
8 の塗布を行うことによって形成を行うことができる。Finally, the application of the marking 8 having the thickness t2 by the white paint is performed on the upper layer of the dummy pattern 6 at the same time as the mark for positioning the electronic component 3 is mounted.
The formation can be performed by applying 8 times.
【００２６】したがって、支持パターン5 を形成するた
めの特別な工程を製造工程に新たに追加することなく、
通常の製造工程によって支持パターン5 の形成を行うこ
とができる。Therefore, without adding a special process for forming the support pattern 5 to the manufacturing process,
The support pattern 5 can be formed by a normal manufacturing process.
【００２７】この場合、ソルダーレジスト7 およびマー
キング8 の厚みt1およびt2は約10〜20μm であり、ダミ
ーパターン6 の高さはパッド2 の高さH1と同じになるた
め、端子4 とパッド2 との間には約20〜40μm の間隙が
形成され、半田付けによる半田代を十分に確保すること
が行え、均一な半田付けを行うことができる。In this case, the thicknesses t1 and t2 of the solder resist 7 and the marking 8 are about 10 to 20 μm, and the height of the dummy pattern 6 is the same as the height H1 of the pad 2. A gap of about 20 to 40 μm is formed between them, so that a sufficient soldering margin can be secured by soldering, and uniform soldering can be performed.
【００２８】[0028]
【発明の効果】以上説明したように、本発明によれば、
ダミーパターンと、ソルダーレジストと、マーキングと
よりなる支持パターンを基板に形成し、電子部品の底面
を均一に支持することでパッドと端子との間には常に、
半田代となる所定の間隙が形成され、特に、半田鏝によ
って半田付けを行う場合、均一な品質を得ることができ
る。As described above, according to the present invention,
A dummy pattern, a solder resist, and a support pattern consisting of markings are formed on the substrate, and the bottom surface of the electronic component is evenly supported so that there is always a space between the pad and the terminal.
A predetermined gap that serves as a soldering margin is formed, and particularly when soldering is performed with a soldering iron, uniform quality can be obtained.
【００２９】したがって、従来のようなスペーサを設け
る場合に比較して、製造の工数が削減されることでコス
トダウが図れ、しかも、品質の向上が図れ、実用的効果
は大である。Therefore, as compared with the case where the conventional spacer is provided, the number of manufacturing steps is reduced, so that the cost can be reduced, the quality can be improved, and the practical effect is great.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明による一実施例の説明図FIG. 2 is an explanatory diagram of an embodiment according to the present invention.
【図３】 本発明の支持パターンの製造工程図FIG. 3 is a manufacturing process diagram of a support pattern of the present invention.
【図４】 従来の説明図FIG. 4 is a conventional explanatory diagram
１ 基板 ２ パッド ３ 電子部品 ４ 端子 ５ 支持パターン ６ ダミーパター
ン ７ ソルダーレジスト ８ マーキング 1A 表面 3A 底面1 substrate 2 pad 3 electronic component 4 terminal 5 support pattern 6 dummy pattern 7 solder resist 8 marking 1A surface 3A bottom surface
Claims (2)
(2) と、電子部品(3) の底面(3A)に形成された端子(4)
とを半田付けによって固着することで該電子部品(3) を
該基板(1) に実装する電子部品の実装構造であって、 所定の前記端子(4) を前記パッド(2) に対応させること
で前記電子部品(3) を前記表面(1A)に押圧した時、該端
子(3) と該パッド(2) との間に平行な所定の間隔(S) が
保持されるよう該底面(3A)の複数の箇所を支持する支持
パターン(5) が該表面(1A)に配設されることを特徴とす
る電子部品の実装構造。1. A pad disposed on a surface (1A) of a substrate (1)
(2) and terminals (4) formed on the bottom surface (3A) of the electronic component (3)
A mounting structure for an electronic component, in which the electronic component (3) is mounted on the substrate (1) by fixing and by fixing the electronic component (3) to the pad (2). When the electronic component (3) is pressed against the surface (1A) with the bottom surface (3A) so that a predetermined parallel distance (S) is maintained between the terminal (3) and the pad (2). The mounting structure of the electronic component is characterized in that the supporting pattern (5) for supporting a plurality of points of (1) is provided on the surface (1A).
前記表面(1A)に配設されたダミーパターン(6) と、該ダ
ミーパターン(6) の上層に積層されたソルダーレジスト
(7) と、該ソルダーレジスト(7) の上層に更に積層され
るマーキング(8) とによって形成されることを特徴とす
る電子部品の実装構造。2. A dummy pattern (6) in which the support pattern (5) according to claim 1 is disposed on the surface (1A), and a solder resist laminated on the dummy pattern (6).
A mounting structure for an electronic component, which is formed by (7) and a marking (8) further laminated on the solder resist (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12657092A JPH05327163A (en) | 1992-05-20 | 1992-05-20 | Mounting structure of electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12657092A JPH05327163A (en) | 1992-05-20 | 1992-05-20 | Mounting structure of electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05327163A true JPH05327163A (en) | 1993-12-10 |
Family
ID=14938439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12657092A Withdrawn JPH05327163A (en) | 1992-05-20 | 1992-05-20 | Mounting structure of electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05327163A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08250890A (en) * | 1995-03-09 | 1996-09-27 | Nec Corp | Hybrid integrated circuit device |
| JPH0923051A (en) * | 1995-05-29 | 1997-01-21 | Sgs Thomson Microelectron Sa | Micromodule tobe used as surface mounting type package |
| JPH10242386A (en) * | 1996-02-23 | 1998-09-11 | Denso Corp | Surface-mount-type semiconductor package, transducer assembly, and surface-mount-type unit |
| EP1791406A1 (en) * | 2005-11-28 | 2007-05-30 | Delphi Technologies, Inc. | Method of forming a composite standoff on a ciruit board |
| JP2009278121A (en) * | 2009-07-10 | 2009-11-26 | Suzuka Fuji Xerox Co Ltd | Printed circuit board device |
| CN103369832A (en) * | 2012-04-03 | 2013-10-23 | 恩斯迈电子(深圳)有限公司 | Circuit board |
| JP2017505991A (en) * | 2014-01-13 | 2017-02-23 | アウト カーベル マネージメントゲゼルシャフト ミット ベシュレンクテル ハフツング | Printed circuit board, circuit, and method for manufacturing the circuit |
| JP2018120991A (en) * | 2017-01-26 | 2018-08-02 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| WO2021215879A1 (en) * | 2020-04-23 | 2021-10-28 | 엘지이노텍 주식회사 | Circuit board |
-
1992
- 1992-05-20 JP JP12657092A patent/JPH05327163A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08250890A (en) * | 1995-03-09 | 1996-09-27 | Nec Corp | Hybrid integrated circuit device |
| JPH0923051A (en) * | 1995-05-29 | 1997-01-21 | Sgs Thomson Microelectron Sa | Micromodule tobe used as surface mounting type package |
| JPH10242386A (en) * | 1996-02-23 | 1998-09-11 | Denso Corp | Surface-mount-type semiconductor package, transducer assembly, and surface-mount-type unit |
| EP1791406A1 (en) * | 2005-11-28 | 2007-05-30 | Delphi Technologies, Inc. | Method of forming a composite standoff on a ciruit board |
| JP2009278121A (en) * | 2009-07-10 | 2009-11-26 | Suzuka Fuji Xerox Co Ltd | Printed circuit board device |
| CN103369832A (en) * | 2012-04-03 | 2013-10-23 | 恩斯迈电子(深圳)有限公司 | Circuit board |
| JP2017505991A (en) * | 2014-01-13 | 2017-02-23 | アウト カーベル マネージメントゲゼルシャフト ミット ベシュレンクテル ハフツング | Printed circuit board, circuit, and method for manufacturing the circuit |
| JP2018120991A (en) * | 2017-01-26 | 2018-08-02 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| JP2022003688A (en) * | 2017-01-26 | 2022-01-11 | 三菱電機株式会社 | Manufacturing method for semiconductor device |
| WO2021215879A1 (en) * | 2020-04-23 | 2021-10-28 | 엘지이노텍 주식회사 | Circuit board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990803 |