JPH05326917A - Optical semiconductor device - Google Patents

Optical semiconductor device

Info

Publication number
JPH05326917A
JPH05326917A JP4127517A JP12751792A JPH05326917A JP H05326917 A JPH05326917 A JP H05326917A JP 4127517 A JP4127517 A JP 4127517A JP 12751792 A JP12751792 A JP 12751792A JP H05326917 A JPH05326917 A JP H05326917A
Authority
JP
Japan
Prior art keywords
shielding film
light
light shielding
hole
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4127517A
Other languages
Japanese (ja)
Other versions
JP3172253B2 (en
Inventor
Keiji Mita
恵司 三田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12751792A priority Critical patent/JP3172253B2/en
Publication of JPH05326917A publication Critical patent/JPH05326917A/en
Application granted granted Critical
Publication of JP3172253B2 publication Critical patent/JP3172253B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To perform degassing and light shielding at the same time by providing through hole 5 in an interlayer insulating film around a penetrating hole in a light shielding film, surrounding the peripheral part of the penetrating hole with the connecting part of the light shielding film and a second light shielding film, cutting a part of the connecting part so as to form a degassing path, and bending the path. CONSTITUTION:Through holes are provided around a penetrating hole 43 in a light shielding film 42. The peripheral part of the penetrating hole 43 is surrounded with a connecting part 45 of the light shielding film and a second light shielding film 44. A part of the connecting part 45 is cut so as to form a degassing path 46. The path 46 is bent and snaked. Thus, the gas generated in a polyimide resin is discharged to the outside by way of the path 46 and the penetrating hole 43. Meanwhile, a second light shielding film 44 is provided under the penetrating hole 43. Since the path is bent, light does not go out to the outside from the region surrounded with the connecting part 45 since the light has the rectilinear propagating property. In this way, the degassing and the light shielding can be made compatible at the same time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はホトダイオードをバイポ
ーラICとを一体化した光半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device in which a photodiode is integrated with a bipolar IC.

【0002】[0002]

【従来の技術】受光素子と周辺回路とを一体化してモノ
リシックに形成した光半導体装置は、受光素子と回路素
子とを別個に作ってハイブリッドIC化したものと異な
り、コストダウンが期待でき、また、外部電磁界による
雑音に対して強いというメリットを持つ。
2. Description of the Related Art An optical semiconductor device in which a light-receiving element and a peripheral circuit are integrated to form a monolithic device can be expected to reduce costs, unlike a hybrid IC in which a light-receiving element and a circuit element are separately formed. , It has a merit that it is strong against noise caused by an external electromagnetic field.

【0003】このような光半導体装置の従来の構造とし
て、例えば特開平1−205564号公報に記載された
ものが公知である。これを図11に示す。同図におい
て、(1)はP型の半導体基板、(2)はP型のエピタ
キシャル層、(3)はN型のエピタキシャル層、(4)
はP+型分離領域、(5)はN+型拡散領域、(6)はN
+型埋め込み層、(7)はP型ベース領域、(8)はN+
型エミッタ領域である。ホトダイオード()はP型エ
ピタキシャル層(2)とN型エピタキシャル層(3)と
のPN接合で形成し、N+型拡散領域(5)をカソード
取出し、分離領域(4)をアノード取出しとしたもので
ある。NPNトランジスタ(10)はP型エピタキシャ
ル層(2)とN型エピタキシャル層(3)との境界に埋
め込み層(6)を設け、N型エピタキシャル層(3)を
コレクタとしたものである。そして、基板(1)からの
オートドープ層(11)によって加速電界を形成し、空
乏層より深部の領域で発生したキャリアの移動を容易に
したものである。
As a conventional structure of such an optical semiconductor device,
For example, as described in Japanese Patent Laid-Open No. 1-205564
Things are known. This is shown in FIG. In the figure
(1) is a P-type semiconductor substrate, and (2) is a P-type epitaxial substrate.
Axial layer, (3) is N type epitaxial layer, (4)
Is P+Mold separation area, (5) is N+Type diffusion region, (6) is N
+Type buried layer, (7) P type base region, (8) N type+
It is a mold emitter region. Photodiode (9) Is P-type
The epitaxial layer (2) and the N-type epitaxial layer (3)
PN junction of+Cathode type diffusion region (5)
With the take-out / separation area (4) as the anode take-out
is there. NPN transistor (10) Is P-type epitaxy
Buried at the boundary between the rule layer (2) and the N-type epitaxial layer (3)
The embedded layer (6) is provided, and the N-type epitaxial layer (3) is formed.
It was intended as a collector. And from the substrate (1)
The auto-doping layer (11) creates an accelerating electric field,
Easy movement of carriers generated in regions deeper than the depletion layer
It was done.

【0004】斯る装置は、光信号を受光する必要性か
ら、前記光信号の波長の光が通過できる樹脂にてモール
ドされる。また、NPNトランジスタ(10)等の領域
でも光入射によって光生成キャリアが発生し、このキャ
リアが寄生効果や誤動作を招く。そのためICチップに
は、ホトダイオード()部分のみに光が照射される手
段を拠す必要がある。
Since such a device needs to receive an optical signal, it is molded with a resin that allows passage of light having the wavelength of the optical signal. In addition, photo-generated carriers are also generated in the region of the NPN transistor ( 10 ) or the like due to the incidence of light, and this carrier causes a parasitic effect or malfunction. Therefore, it is necessary to provide the IC chip with a means for irradiating light only to the photodiode ( 9 ) portion.

【0005】上記手段として最も簡便な方法は、多層配
線技術を利用したAl配線層を遮光膜として用いる方法
である。すなわち単層又は多層構造で素子間接続を行っ
た後、ポリイミド系樹脂による層間絶縁膜を介してIC
チップ全面にAl膜を形成し、このAl膜のホトダイオ
ード()部分を開口して光入射用の窓としたものであ
る。
The simplest method as the above means is to use an Al wiring layer using a multilayer wiring technique as a light shielding film. That is, after connecting elements with a single-layer or multi-layer structure, ICs are formed through an interlayer insulating film made of a polyimide resin.
An Al film is formed on the entire surface of the chip, and a photodiode ( 9 ) portion of this Al film is opened to form a window for light incidence.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、ポリイ
ミド系樹脂の上を一定面積以上の大きさのAl膜で被覆
すると、後のAlアロイ工程等の加熱(300〜400
℃)によってAl膜がふくれる現象が発生することが知
られている。このふくれは、ポリイミド系樹脂が吸湿性
であることから、樹脂に水分が付着し、その水分が熱処
理によって蒸発することに起因すると考えられている。
そのため、Al膜で被う場合はある面積毎にガス抜き穴
を設ける必要がある(特公昭58−46853号に詳し
い)。一方、ガス抜き穴を設ければ当然そこから光が入
射し、不要部で光生成キャリアが生成されて寄生効果、
誤動作の要因になる。
However, when the polyimide resin is coated with an Al film having a size larger than a certain area, heating (300 to 400) in the subsequent Al alloy process or the like is performed.
It is known that the phenomenon that the Al film swells due to (° C.). It is considered that this blister is caused by the fact that the polyimide-based resin is hygroscopic, so that water adheres to the resin and the water is evaporated by heat treatment.
Therefore, when covering with an Al film, it is necessary to provide a gas vent hole for each certain area (see Japanese Patent Publication No. 58-46853). On the other hand, if a gas vent hole is provided, light will naturally enter from there, and photo-generated carriers will be generated in unnecessary portions, resulting in a parasitic effect,
It may cause malfunction.

【0007】[0007]

【課題を解決するための手段】本発明は上述した従来の
欠点に鑑み成されたもので、遮光膜(42)の貫通孔
(43)の周囲にスルーホールを設けて貫通孔(43)
の周囲を遮光膜(42)と第2の遮光膜(44)との接
続部(45)で囲み、接続部(45)の一部を切ってガ
ス抜き用の通路(46)を形成し、この通路(46)を
屈曲させることによって、入射光の遮光と層間絶縁膜
(41)のガス抜きとを両立させた構造を提供するもの
である。
The present invention has been made in view of the above-mentioned conventional drawbacks, and a through hole is provided around the through hole (43) of the light shielding film (42) to form the through hole (43).
Is surrounded by a connecting portion (45) between the light-shielding film (42) and the second light-shielding film (44), and a part of the connecting portion (45) is cut to form a degassing passage (46), By bending the passage (46), it is possible to provide a structure in which the shielding of the incident light and the degassing of the interlayer insulating film (41) are compatible with each other.

【0008】[0008]

【作用】本発明によれば、貫通孔(43)を囲む接続部
(45)を切って通路(46)を設けたので、ポリイミ
ド樹脂で発生したガスは通路(46)を通って貫通孔
(43)より外に排出される。その一方で、貫通孔(4
3)の下に第2の遮光膜(44)を設け、通路を屈曲さ
せることにより、光が直進性を有するので、接続部(4
5)で囲まれた領域から外へ抜けることがない。
According to the present invention, since the passage (46) is provided by cutting the connecting portion (45) surrounding the through hole (43), the gas generated by the polyimide resin passes through the passage (46) and the through hole (46). 43) is discharged to the outside. On the other hand, through holes (4
By providing the second light-shielding film (44) under 3) and bending the passage, the light has a straight traveling property.
There is no escape from the area surrounded by 5).

【0009】[0009]

【実施例】以下に本発明の一実施例を図面を参照しなが
ら詳細に説明する。先ず図8を用いて全体の概略を説明
する。図8はホトダイオード(21)とNPNトランジ
スタ(22)とを組み込んだICの断面図である。同図
において、(23)はP型の単結晶シリコン半導体基
板、(24)は基板(23)上に気相成長法によりノン
ドープで積層した厚さ15〜20μの第1のエピタキシ
ャル層、(25)は第1のエピタキシャル層(24)上
に気相成長法によりリン(P)ドープで積層した厚さ4
〜6μの第2のエピタキシャル層である。基板(23)
は一般的なバイポーラICのものより不純物濃度が低い
40〜60Ω・cmの比抵抗のものを用い、第1のエピ
タキシャル層(24)はノンドープで積層することによ
り、積層時で1000Ω・cm以上、拡散領域を形成す
るための熱処理を与えた後の完成時で200〜1500
Ω・cmの比抵抗を有する。第2のエピタキシャル層
(25)は、リン(P)を10 15〜1016cm-3程ドー
プすることにより、0.5〜3.0Ω・cmの比抵抗を
有する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will now be described with reference to the drawings.
Will be described in detail. First, the overall outline is explained using FIG.
To do. Figure 8 shows a photodiode (21) And NPN Transi
Star (22) Is a cross-sectional view of an integrated circuit (IC). Same figure
(23) is a P-type single crystal silicon semiconductor substrate
Plate, (24) is non-deposited on the substrate (23) by vapor phase epitaxy
First epitaxy with a thickness of 15-20 μ, laminated with dope
Layer (25) on the first epitaxial layer (24)
Thickness of 4 (P) doped by vapor phase epitaxy
˜6 μ second epitaxial layer. Board (23)
Has lower impurity concentration than that of general bipolar IC
Using the one with a specific resistance of 40-60 Ω · cm,
The axial layer (24) is a non-doped laminated layer.
Form a diffusion region of 1000 Ω · cm or more when laminated
200-1500 at the time of completion after heat treatment for
It has a specific resistance of Ω · cm. Second epitaxial layer
(25) is the phosphorus (P) 10 15-1016cm-3Hodo
The specific resistance of 0.5 to 3.0 Ω · cm by
Have.

【0010】第1と第2のエピタキシャル層(24)
(25)は、両者を完全に貫通するP +型分離領域(
)によってホトダイオード(21)形成部分とNPN
トランジスタ(22)形成部分とに電気的に分離され
る。この分離領域(26)は、基板(23)表面から上
下方向に拡散した第1の分離領域(27)と、第1と第
2のエピタキシャル層(24)(25)の境界から上下
方向に拡散した第2の分離領域(28)と、第2のエピ
タキシャル層(25)表面から形成した第3の分離領域
(29)から成り、3者が連結することで第1と第2の
エピタキシャル層(24)(25)を島状に分離する。
First and second epitaxial layers (24)
(25) is P that completely penetrates both +Mold separation area (Two
6) By a photodiode (21) Forming part and NPN
Transistor (22) Electrically separated from the forming part
It This separation area (26) Is above the substrate (23) surface
A first separation region (27) diffused downwardly,
Above and below the boundary between the two epitaxial layers (24) and (25)
Directionally diffused second isolation region (28) and a second epi region
Third separation region formed from the surface of the axial layer (25)
It consists of (29), and by connecting the three parties, the first and second
The epitaxial layers (24) and (25) are separated into islands.

【0011】ホトダイオード(21)部の第2のエピタ
キシャル層(25)表面には、ホトダイオード(21
のカソード取出しとなるN+型拡散領域(30)を形成
する。N+型拡散領域(30)を第1の島領域の略全面
に拡大すると、カソードの取出し直列抵抗を低減でき
る。N+型拡散領域(30)上の酸化膜は部分的に開口
され、この開口部を覆うようにしてシリコン表面に直に
接触する反射防止膜(31)を形成する。反射防止膜
(31)は膜厚400〜1000Åのシリコン窒化膜
(SiN)と膜厚4000〜7000Åのシリコン酸化
膜(SiO2)から成る。反射防止膜(31)の一部は
除去され、除去された部分にコンタクトホールを介して
カソード電極(32)がN+型拡散領域(30)にオー
ミック接触する。また、分離領域(26)をホトダイオ
ード(21)のアノード側低抵抗取出し領域として、ア
ノード電極(33)が分離領域(26)の表面にコンタ
クトする。
On the surface of the second epitaxial layer (25) of the photodiode ( 21 ) portion, the photodiode ( 21 ) is formed.
An N + type diffusion region (30) is formed, which serves as a cathode extraction region. When the N + type diffusion region (30) is expanded over substantially the entire area of the first island region, the extraction series resistance of the cathode can be reduced. The oxide film on the N + type diffusion region (30) is partially opened, and an antireflection film (31) that directly contacts the silicon surface is formed so as to cover the opening. The antireflection film (31) is composed of a silicon nitride film (SiN) having a film thickness of 400 to 1000Å and a silicon oxide film (SiO 2 ) having a film thickness of 4000 to 7000Å. A part of the antireflection film (31) is removed, and the cathode electrode (32) makes ohmic contact with the N + type diffusion region (30) through the contact hole in the removed portion. Further, the isolation region ( 26 ) is used as the anode-side low resistance extraction region of the photodiode ( 21 ), and the anode electrode (33) contacts the surface of the isolation region ( 26 ).

【0012】NPNトランジスタ(22)部の第1と第
2のエピタキシャル層(24)(25)の境界部には、
+型の埋め込み層(34)が埋め込まれている。埋め
込み層(34)上方の第2のエピタキシャル層(25)
表面には、NPNトランジスタ(22)のP型のベース
領域(35)、N+型のエミッタ領域(36)、および
+型のコレクタコンタクト領域(37)を形成する。
各拡散領域上には1層目の配線層による電極配線(3
8)がコンタクトホールを介してオーミック接触する。
尚、前記アノード電極(32)とカソード電極(33)
は1層目の配線層によるものである。その上にはPIX
等からなる層間絶縁膜(39)と2層目の電極配線(4
0)を設ける。電極配線(38)(39)が絶縁膜上を
延在することによって各素子を電気接続し、ホトダイオ
ード(21)が光信号入力部を、NPNトランジスタ
22)が他の素子と共に信号処理回路を構成する。
At the boundary between the first and second epitaxial layers (24) and (25) of the NPN transistor ( 22 ) part,
An N + type buried layer (34) is buried. Second epitaxial layer (25) above the buried layer (34)
A P-type base region (35), an N + -type emitter region (36), and an N + -type collector contact region (37) of the NPN transistor ( 22 ) are formed on the surface.
The electrode wiring (3
8) makes ohmic contact through the contact hole.
The anode electrode (32) and the cathode electrode (33)
Is due to the first wiring layer. PIX on it
An interlayer insulating film (39) made of the like and the second layer electrode wiring (4
0) is provided. The electrode wirings (38) and (39) extend over the insulating film to electrically connect the respective elements, and the photodiode ( 21 ) forms an optical signal input section and the NPN transistor ( 22 ) forms a signal processing circuit together with other elements. Constitute.

【0013】電極配線(40)上はPIX(日立化成:
商品名)等のポリイミド系樹脂による膜厚1.0〜2.
0μの層間絶縁膜(41)が覆い、層間絶縁膜(41)
上に3層目Al膜による遮光膜(42)を形成する。遮
光膜(42)の上は再度ポリイミド系樹脂から成るジャ
ケット・コートが被覆する。遮光膜(42)は、ホトダ
イオード(21)部以外の殆どの領域を覆うと共に、大
体一定間隔でスリット状の貫通孔(43)が設けられ
る。貫通孔(43)は10μ×10μ程度の大きさを有
し、遮光膜(42)が300μ×300μ以上の面積で
連続することのないように多数箇所に設けられる。
The PIX (Hitachi Chemical:
A film thickness of a polyimide resin such as (trade name) 1.0-2.
The 0 μ interlayer insulating film (41) covers and the interlayer insulating film (41)
A light-shielding film (42) made of a third-layer Al film is formed thereon. The light-shielding film (42) is again covered with a jacket coat made of polyimide resin. The light-shielding film (42) covers most of the region other than the photodiode ( 21 ) part, and slit-shaped through holes (43) are provided at regular intervals. The through-hole (43) has a size of about 10 μ × 10 μ, and is provided at a large number of places so that the light-shielding film (42) does not continue in an area of 300 μ × 300 μ or more.

【0014】遮光膜(42)の貫通孔(43)の下部に
は、2層目の電極配線(40)によって貫通孔(43)
をふさぐ第2の遮光膜(44)を形成する。第2の遮光
膜(44)は、貫通孔(43)の大きさより大きく60
μ×70μ程の大きさに形成され、それは素子間接続を
行う電極配線(40)の一部であっても、素子間接続に
関与しないダミーの配線であっても良い。
Below the through hole (43) of the light shielding film (42), the through hole (43) is formed by the electrode wiring (40) of the second layer.
Forming a second light-shielding film (44). The second light shielding film (44) is larger than the size of the through hole (43) by 60.
It is formed to have a size of about μ × 70 μ, and it may be a part of the electrode wiring (40) for connecting the elements or a dummy wiring not involved in the connection between the elements.

【0015】そして、ホトダイオード(21)上の層間
絶縁膜(39)(41)と遮光膜(42)、およびジャ
ケット・コートが光入射のために除去され、全体のチッ
プはシリコン酸化膜と同等の光屈折率を有し且つ光信号
の波長の光を通過するようなエポキシ系樹脂にてモール
ドされる。ホトダイオード(21)は、カソード電極
(32)に+5Vの如きVCC電位を、アノード電極(3
3)にGND電位を印加した逆バイアス状態で動作させ
る。このような逆バイアスを与えると、ホトダイオード
21)の第1と第2のエピタキシャル層(24)(2
5)の境界から空乏層が拡がり、第1のエピタキシャル
層(24)が高比抵抗層であることから特に第1のエピ
タキシャル層(24)中に大きく拡がる。その空乏層は
基板(23)に達するまで容易に拡がり、厚さ20〜2
5μの極めて厚い空乏層を得ることができる。そのた
め、ホトダイオード(21)の接合容量を低減し、高速
応答を可能にする。
Then, the interlayer insulating films (39) (41) and the light-shielding film (42) on the photodiode ( 21 ) and the jacket coat are removed for light incidence, and the entire chip is equivalent to the silicon oxide film. It is molded with an epoxy resin that has a light refractive index and allows light of the wavelength of the optical signal to pass through. The photodiode ( 21 ) applies a V CC potential such as + 5V to the cathode electrode (32) and the anode electrode (3).
It is operated in the reverse bias state in which the GND potential is applied to 3). When such a reverse bias is applied, the first and second epitaxial layers (24) (2) of the photodiode ( 21 ) are
The depletion layer spreads from the boundary of 5), and since the first epitaxial layer (24) is a high resistivity layer, the depletion layer particularly spreads greatly in the first epitaxial layer (24). The depletion layer spreads easily until it reaches the substrate (23) and has a thickness of 20-2.
An extremely thick depletion layer of 5μ can be obtained. Therefore, the junction capacitance of the photodiode ( 21 ) is reduced and high-speed response is enabled.

【0016】続いて、本願の特徴とする貫通孔(43)
部の詳細を説明する。図1は貫通孔(43)部を示す平
面図、図2は図1のAA線断面図である。貫通孔(4
3)の下部に2層目の電極配線(40)による第2の遮
光膜(44)が貫通孔(43)をふさぐように配置さ
れ、その周囲の層間絶縁膜(41)にはスルーホールを
設ける。このスルーホールを通して遮光膜(42)と第
2の遮光膜(44)とがコンタクトして接続部(45)
を形成する。接続部(45)は貫通孔(43)を取り囲
むように(図示斜線部)形成され、その一部は切断され
ている。切断した部分はポリイミド系層間絶縁膜(4
1)が連続する部分となり、層間絶縁膜(41)で発生
したガスが図示矢印の如き経路で通過することのできる
通路(46)となる。通路(46)の途中は接続部(4
5)が突出しており、突出させることによって通路(4
6)を蛇行、屈曲させ、通路(46)の入口から貫通孔
(43)までが一直線に結べないようなパターン形状と
している。
Subsequently, the through hole (43) which is a feature of the present invention
The details of the section will be described. 1 is a plan view showing the through hole (43) portion, and FIG. 2 is a sectional view taken along the line AA of FIG. Through hole (4
A second light-shielding film (44) formed by the electrode wiring (40) of the second layer is arranged under the layer 3) so as to close the through hole (43), and a through hole is formed in the surrounding interlayer insulating film (41). Set up. The light-shielding film (42) and the second light-shielding film (44) are in contact with each other through the through hole to make a connection portion (45).
To form. The connection part (45) is formed so as to surround the through hole (43) (hatched part in the drawing), and a part thereof is cut. The cut portion is a polyimide-based interlayer insulating film (4
1) becomes a continuous portion, and becomes a passage (46) through which the gas generated in the interlayer insulating film (41) can pass through the path shown by the arrow. In the middle of the passage (46), the connecting portion (4
5) is protruding, and the passage (4
6) is meandered and bent to have a pattern shape so that the entrance of the passage (46) and the through hole (43) cannot be connected in a straight line.

【0017】このようなパターン形状によれば、層間絶
縁膜(41)で発生したガスは通路(45)を通って貫
通孔(43)から逃げることができるので、Alのふく
れ現象を防止できる。一方、光はガスと異り直進性を有
するから、貫通孔(43)を通過した光は通路(46)
が屈曲していることによって通路(46)の外に出るこ
とができない。まして、下には第2の遮光膜(44)が
存在するので、シリコン基板(23)にまで達すること
はない。このように、本願はガスと光の性質に着目し
て、ガス抜きと遮光を同時に行うことができるものであ
る。
According to such a pattern shape, the gas generated in the interlayer insulating film (41) can escape from the through hole (43) through the passage (45), so that the blistering phenomenon of Al can be prevented. On the other hand, since light has a straight-line property unlike gas, light passing through the through hole (43) passes through the passage (46).
Bending prevents the person from getting out of the passageway (46). Furthermore, since the second light-shielding film (44) exists below, it does not reach the silicon substrate (23). As described above, the present application focuses on the properties of gas and light, and can simultaneously perform degassing and light shielding.

【0018】尚、接続部(45)のパターンは図1に示
したものに限られることはない。要はガスが通過できる
通路を確保できると同時に、光が外にもれないように通
路が屈曲していれば済む。このバリエーションを図3〜
図7に示した。全て本願の作用効果が得られるパターン
である。
The pattern of the connecting portion (45) is not limited to that shown in FIG. The point is that a passage through which gas can pass can be secured, and at the same time, the passage must be bent to prevent light from leaking outside. This variation is shown in Figure 3 ~
It is shown in FIG. All are patterns in which the effects of the present application can be obtained.

【0019】[0019]

【発明の効果】以上に説明した通り、本発明によればポ
リイミド系樹脂によって層間接続を行い、ホトダイオー
ド部以外の領域を遮光膜(42)で被覆した光半導体装
置において、ガス抜きと余分な光の遮光を同時に行うこ
とのできる有益なものである。
As described above, according to the present invention, in an optical semiconductor device in which interlayer connection is made of a polyimide resin and a region other than the photodiode portion is covered with a light shielding film (42), degassing and excess light are prevented. This is useful because it can simultaneously shield the light.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を説明するための平面図である。FIG. 1 is a plan view for explaining the present invention.

【図2】図1のAA線断面図である。FIG. 2 is a cross-sectional view taken along the line AA of FIG.

【図3】別の実施例を示す平面図である。FIG. 3 is a plan view showing another embodiment.

【図4】別の実施例を示す平面図である。FIG. 4 is a plan view showing another embodiment.

【図5】別の実施例を示す平面図である。FIG. 5 is a plan view showing another embodiment.

【図6】別の実施例を示す平面図である。FIG. 6 is a plan view showing another embodiment.

【図7】別の実施例を示す平面図である。FIG. 7 is a plan view showing another embodiment.

【図8】本発明を説明するための断面図である。FIG. 8 is a cross-sectional view for explaining the present invention.

【図9】従来例を説明するための断面図である。FIG. 9 is a cross-sectional view for explaining a conventional example.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 同一基板上に光信号入力用のホトダイオ
ードと信号処理回路用のトランジスタとを形成し、前記
ホトダイオードの領域を除く領域を遮光膜で覆い、前記
遮光膜より下層の配線層で前記トランジスタを結線する
と共に、前記遮光膜と前記配線層との間をポリイミド系
の絶縁膜で層間絶縁した光半導体装置において、 前記遮光膜に貫通孔を多数設け、該貫通孔の下には下層
の配線層で第2の遮光膜を形成し、 前記貫通孔の周囲の層間絶縁膜にスルーホールを設けて
前記貫通孔の周囲を前記遮光膜と前記第2の遮光膜の接
続部で囲み、 前記接続部はその一部が切れてガス抜き用の通路を形成
すると共に、前記通路を屈曲させたことを特徴とする光
半導体装置。
1. A photodiode for inputting an optical signal and a transistor for a signal processing circuit are formed on the same substrate, a region except the region of the photodiode is covered with a light shielding film, and a wiring layer lower than the light shielding film is used. In an optical semiconductor device in which a transistor is connected and interlayer insulation is performed between the light-shielding film and the wiring layer with a polyimide-based insulating film, a large number of through holes are provided in the light-shielding film, and a lower layer is formed below the through-holes. A second light-shielding film is formed of a wiring layer, a through-hole is provided in an interlayer insulating film around the through hole, and the periphery of the through-hole is surrounded by a connecting portion between the light-shielding film and the second light-shielding film, An optical semiconductor device, wherein a part of the connecting portion is cut to form a passage for degassing, and the passage is bent.
【請求項2】 前記遮光膜と前記下層の配線層はAl又
はAl−Siであることを特徴とする請求項1記載の光
半導体装置。
2. The optical semiconductor device according to claim 1, wherein the light shielding film and the underlying wiring layer are made of Al or Al—Si.
【請求項3】 前記第2の遮光膜は回路素子間の結線を
行う電極配線であることを特徴とする請求項1記載の光
半導体装置。
3. The optical semiconductor device according to claim 1, wherein the second light shielding film is an electrode wiring for connecting the circuit elements.
【請求項4】 前記第2の遮光膜はダミーの電極配線で
あることを特徴とする請求項1記載の光半導体装置。
4. The optical semiconductor device according to claim 1, wherein the second light shielding film is a dummy electrode wiring.
JP12751792A 1992-05-20 1992-05-20 Optical semiconductor device Expired - Fee Related JP3172253B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12751792A JP3172253B2 (en) 1992-05-20 1992-05-20 Optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12751792A JP3172253B2 (en) 1992-05-20 1992-05-20 Optical semiconductor device

Publications (2)

Publication Number Publication Date
JPH05326917A true JPH05326917A (en) 1993-12-10
JP3172253B2 JP3172253B2 (en) 2001-06-04

Family

ID=14961974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12751792A Expired - Fee Related JP3172253B2 (en) 1992-05-20 1992-05-20 Optical semiconductor device

Country Status (1)

Country Link
JP (1) JP3172253B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156520A (en) * 1998-11-19 2000-06-06 Matsushita Electric Ind Co Ltd Light receiving element and manufacture thereof
JP2001144317A (en) * 1999-11-15 2001-05-25 Sharp Corp Light receiving element with built-in circuit
JP2001309240A (en) * 2000-01-21 2001-11-02 Symagery Microsystems Inc Analog storage device for cmos array

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156520A (en) * 1998-11-19 2000-06-06 Matsushita Electric Ind Co Ltd Light receiving element and manufacture thereof
JP2001144317A (en) * 1999-11-15 2001-05-25 Sharp Corp Light receiving element with built-in circuit
JP2001309240A (en) * 2000-01-21 2001-11-02 Symagery Microsystems Inc Analog storage device for cmos array
JP4727045B2 (en) * 2000-01-21 2011-07-20 ハルサキ・テクノロジーズ,リミテッド・ライアビリティ・カンパニー Analog storage device for CMOS array
US8537242B2 (en) 2000-01-21 2013-09-17 Harusaki Technologies, Llc Host interface for imaging arrays

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