JPH05326886A - Memory device - Google Patents

Abstract

PURPOSE:To enhance a memory device in degree of integration by a method wherein two gate electrode wirings to serve as the gate electrodes of a pair of transistors are made to overlap each other on an element isolating insulating film through the intermediary of an insulating film. CONSTITUTION:An element isolating insulating film 2 is selectively formed on a P-type silicon substrate 12, and active regions 1 demarcated as surrounded by the element isolating insulating film 2 are arranged in matrix. A first gate electrode wiring 34 is formed of a first polysilicon layer constituting a gate electrode 14 of a transistor formed on the right side of the active region 1 and a word line 24 on an interlayer insulating film 8. Then, a second gate electrode wiring 44 is formed of a second polysilicon layer constituting a gate electrode 14 of a transistor formed on the left side of the active region 1 and a word line 24 on the interlayer insulating film 8, and the gate electrode wirings 34 and 44 are made to overlap each other through the intermediary of an insulating film 5 on the interlayer insulating film 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a layout structure of gate electrode wirings in a dynamic random access memory (DRAM) device.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional DRAM device.
(A) is a plan view and (B) is a cross-sectional view taken along line BB of (A). In order to avoid complication, only the element isolation insulating film 2, the active region 1 and the gate electrode wiring 4 are shown in (A).

An element isolation insulating film 2 is selectively formed on a P-type silicon substrate 12, and a plurality of active regions 1 of a semiconductor substrate surrounded by the element isolation insulating film 2 are arranged in a matrix. Transistors of a pair of DRAM cells are formed in each of the active regions 1, and a gate electrode wiring 4 is formed on the active region 1 to be the gate electrode portion 14 of the transistor and on the element isolation insulating film 2 to be a word line portion 24. . The transistor has a gate electrode portion 14 on the gate insulating film 3 and a pair of N-type source and drain regions 13 and 13, and the MOS-type capacitance that is combined with this transistor to form a DRAM cell is N-type. One of the source and drain regions and the contact portion 1
A lower electrode 11 connected at 5 and extending over the interlayer insulating film 8, a capacitive insulating film 9, and an upper electrode 10 formed in common to each cell and to which a fixed potential is applied form a stack type capacitor.

Then, a pair (two) of gate electrode wirings 4 serving as the gate electrode portions 14 of the pair of transistors formed in the active regions 1 adjacent to each other in the Y direction serve as the word line portions 24 and the element isolation insulating film 2 is formed. They extend parallel to each other.

[0005]

As described above, in the conventional memory device, a pair (2) is formed on the element isolation insulating film 2.
Main) gate electrode wiring 4 is a word line portion 2 of the same layer level
Since it extends parallel to each other as 4, the dimension S in the X direction between the active regions 1 and 1 becomes large, that is, the width in the X direction of the element isolation insulating film 2 becomes large, which hinders the improvement of the integration degree. Was occurring.

[0006]

A feature of the present invention is that an element isolation insulating film is selectively formed on a semiconductor substrate, and a plurality of active regions of the semiconductor substrate surrounded by the element isolation insulating film are divided into a plurality of active regions. A memory having a pair of transistors of dynamic memory cells arranged in each of the active regions, the gate electrode wiring being a gate electrode portion of the transistor on the active region and a word line portion on the element isolation insulating film. In the device, the two gate electrode wirings, which become the gate electrode portions of the pair of transistors in the active region, overlap each other on the element isolation insulating film with an insulating film interposed therebetween.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 shows a DRAM device according to an embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is FIG.
It is sectional drawing of the BB part of (A) of FIG. In addition, in order to avoid complexity, in FIG.
Only the gate electrode wirings 34 and 44 are shown.

A so-called LOC is formed on the P-type silicon substrate 12.
The element isolation insulating film 2 is selectively formed by the OS technique,
A plurality of active regions 1 of the semiconductor substrate surrounded by the element isolation insulating film 2 and partitioned are arranged in a matrix. As shown in FIG. 1A, the active region 1 is a staggered staggered arrangement in the Y direction to enhance the degree of integration.

Transistors of a pair of DRAM cells are formed in each of the active regions 1. In the sectional view (B) of FIG. 1, a transistor formed on the right side of one active region 1 and a capacitance coupled to the transistor are shown on the left side of the figure,
A transistor formed on the left side of the active region 1 located adjacent to the right side of the active region in the X direction via the interlayer insulating film 2 and a capacitance coupled thereto are shown on the right side of the figure.

Each of the transistors has a gate electrode portion 14 on the gate insulating film 3 and a pair of N-type source and drain regions 13 and 13, and a MOS-type capacitor that is combined with this transistor to form a DRAM cell. Is the lower electrode 11 of the third polysilicon layer which is connected to one of the N-type source and drain regions 13 at the contact portion 15 and extends over the interlayer insulating film 8 and the capacitor insulating film 9. A stack type capacitor is formed from the upper electrode 10 of the fourth polysilicon layer which is commonly formed in each cell and to which a fixed potential is applied. Further, in the drawing, the bit line connected to the other region 13 of the N type source and drain regions is omitted.

In this embodiment, the first gate electrode wiring 34, which constitutes the gate electrode portion 14 of the transistor formed on the right side of one active region 1 and constitutes the word line portion 24 on the interlayer insulating film 8, is formed into the first gate electrode wiring 34. A second gate electrode wiring 44 which is formed of the first polysilicon layer and constitutes the gate electrode portion 14 of the transistor formed on the left side of the same active region 1 and constitutes the word line portion 24 on the interlayer insulating film 8. Is formed of a second polysilicon layer, and both of them are superposed on each other with the insulating film 5 interposed therebetween.

[0013]

As described above, according to the present invention, since the two gate electrode wirings 34 and 44 overlap each other on the inter-layer insulating film 8 with the insulating film 5 interposed therebetween, the planar shape is one. Therefore, the dimension T in the X direction between the active regions 1 and 1 is
Becomes smaller. As a result, the width of the element isolation insulating film 2 in the X direction is narrowed, the integration degree is improved, and the size of the memory chip can be reduced.

[Brief description of drawings]

1A and 1B are diagrams showing a memory device according to an embodiment of the present invention, FIG. 1A being a plan view and FIG. 1B being a cross-sectional view taken along the line BB of FIG.

FIG. 2 is a diagram showing a conventional memory device, FIG.
Is a plan view, and (B) is a cross-sectional view taken along the line BB of (A).

[Explanation of symbols]

 1 Active Region 2 Element Isolation Insulation Film 3 Gate Insulation Film 4, 34, 44 Gate Electrode Wiring 5 Insulation Film 8 Interlayer Insulation Film 9 Capacitance Insulation Film 10 Capacitance Upper Electrode 11 Capacitance Upper Electrode 12 Silicon Substrate 13 Source and Drain Region 14 Gate electrode portion of gate electrode wiring 15 Contact portion 24 Word line portion of gate electrode wiring

Claims (1)

[Claims] 1. An element isolation insulating film is selectively formed on a semiconductor substrate, a plurality of active regions of the semiconductor substrate surrounded by the element isolation insulating film are arranged, and a pair of active regions is formed in each of the active regions. Dynamic memory cell transistors are formed, and a pair of transistors in the active region is formed in a memory device having a gate electrode wiring that becomes a gate electrode portion of the transistor on the active region and becomes a word line portion on the element isolation insulating film. 2. The memory device according to claim 1, wherein the two gate electrode wirings serving as respective gate electrode portions are overlapped with each other on the element isolation insulating film via an insulating film.