JPH05326877A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a method of manufacturing a semiconductor device, where a first capacitor electrode formed inside a trench and a connection diffusion layer adjacent to the trench are electrically connected high in controllability on the side wall of the trench. CONSTITUTION:A trench forming first oxide film 5 and an element isolating oxide film 2 are etched, then a side wall 41 of silicon nitride film is formed, and a trench H is formed using the side wall 41 as a mask. The inner wall of the trench H is oxidized for the formation of an capacitor isolating oxide film 6, and then the side wall 41 is etched back, whereby the side wall 41 is left only on the side of the element isolating oxide film 2. Furthermore, a resist 7 is etched back, whereby the oxide film 6 on the base of the trench H is covered, then the oxide film 6 is anisotropically etched, and the substrate is exposed on the side of a connection diffusion layer 4 for forming a contact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a structure in which a capacitor electrode for memory is embedded in a trench groove dug in a semiconductor substrate, and more particularly to a semiconductor device having improved trench groove processing accuracy. The present invention relates to a method of manufacturing a device.

[0002]

33 to 42 are sectional views showing a conventional method of manufacturing a semiconductor device, wherein 1 is a Si substrate, 2 is an element isolation oxide film formed on a Si substrate 1, and 3 is a Si substrate. 1
A resist mask provided above, 4 is a diffusion layer for connection formed on the Si substrate 1, 5 is a first oxide film formed on the Si substrate 1, and 6 is formed in a hole H of the Si substrate 1. Oxide film for capacitor isolation, 7 is a resist embedded in the hole H, 8 is a first electrode of the capacitor formed in the hole H, 9
Is a capacitor dielectric film formed inside the first electrode 8, 1
0 is the second electrode formed inside the capacitor dielectric film 9,
Reference numeral 11 is a second oxide film formed on the second electrode 10, 12 is a third oxide film formed on the side surface of each of the layers 5, 9, 10 and 11, 13 is a gate oxide film formed on the Si substrate, 14
Is a gate electrode formed on the gate oxide film 13, and 15 is a source / drain formed on the Si substrate 1.

First, the manufacturing process up to the formation of the sectional structure shown in FIG. 33 will be described. The Si substrate 1 is oxidized only in a desired region by a selective oxidation method to form an element isolation oxide film 2. Subsequently, after applying the resist mask 3, a predetermined region is opened by a lithographic method to obtain the sectional structure shown in FIG.

Next, an n-type impurity such as arsenic or phosphorus is formed by the ion implantation method to form the diffusion layer 4 for connection, and then the resist mask is removed to obtain the sectional structure shown in FIG.

Next, the first oxide film 5 is deposited by the CVD method (chemical vapor deposition method) or the like to obtain the sectional structure of FIG.

Next, after patterning a resist as a dry etching mask material by a lithography method or the like, a first oxide film 5 and an element isolation oxide film (S _i O ₂ ) are formed.
2 and the Si substrate 1 are processed by a dry etching method,
The Si substrate is anisotropically processed until the holes H having a desired depth are formed, and the resist is removed to obtain the sectional structure shown in FIG.

Next, when it is processed by a thermal oxidation method or the like, the exposed portion of Si inside the hole H as a trench is oxidized to form an oxide film 6 for isolating a capacitor, after which a resist 7 is applied, Is partially removed by a dry etching method and the resist 7 buried up to a predetermined position of the hole H is retracted to obtain a sectional structure shown in FIG.

Next, by wet etching, the first
The three types of oxide films including the oxide film 5, the element isolation oxide film 2 and the capacitor isolation oxide film 6 are removed by a predetermined thickness to obtain the cross-sectional structure shown in FIG.

Next, after depositing the first electrode 8 made of a material such as polycrystalline Si (polysilicon) containing n-type impurities by the CVD method or the like, the flat electrode is removed by the dry etching method to form holes. When left only on the side surface of H, the sectional structure shown in FIG. 39 is obtained.

Next, a capacitor dielectric film 9 made of a material such as a Si nitride film or a Si oxide film, a second electrode 10 made of polysilicon or the like, and a second oxide film 1 made of a Si oxide film or the like.
3 layers consisting of 1 and 1 are sequentially deposited by the CVD method or the like.
Then, the resist as a dry etching mask material is patterned by a lithography method or the like, and the above 3
After the layer is anisotropically processed by the dry etching method, the resist is removed to obtain the sectional structure shown in FIG.

Next, the third oxide film 1 made of a Si oxide film or the like.
2 is deposited by the CVD method or the like, the third oxide film 12 is removed at the flat portion by the dry etching method, and is left at the vertical step portion. Then, the Si substrate 1 is oxidized by a thermal oxidation method or the like to form a gate oxide film 13 to obtain the cross-sectional structure shown in FIG.

Finally, a gate electrode 14 made of polysilicon or the like is deposited by the CVD method or the like, and a resist as a dry etching mask material is patterned by the lithography method or the like. Then, the gate electrode 14 is anisotropically processed, and n-type impurities such as arsenic and phosphorus are injected into the Si substrate 1 by an ion implantation method to form the source / drain 15 of the MOS transistor. Then, the resist is removed to obtain the final sectional structure shown in FIG.

Next, the operation of each part will be described. The capacitor element for the memory includes a first electrode 8 and a second electrode 10.
The transistor element is composed of the gate electrode 14 and the source / drain 15 in the Si substrate 1. These are connected as designed through the connecting diffusion layer 4 in the Si substrate 1 and function as a semiconductor memory element.

Moreover, the first electrode 8 and the source / drain 1
The connection 5 is made through the connection diffusion layer 4 formed on the side surface of the hole H of the Si substrate 14, so that the structure is suitable for miniaturization and high integration of the semiconductor memory element.

[0015]

As described above, the conventional method of manufacturing a semiconductor device is such that the thick resist 7 buried in the hole H is moved back to a predetermined position by a dry etching method to isolate the capacitor in a subsequent process. This is a process designed to prevent the Si substrate 1 other than the connection diffusion layer 4 from being exposed during the wet etching of the oxide film 6.
However, the controllability of the film thickness at the time of applying the resist 7 is generally poor, and the film thickness of the resist 7 required for filling is very large, so that the variation in the film thickness is also large. Therefore, there is a great risk that the connection diffusion layer 4 is not fully exposed at the time of finishing, or the Si substrate 1 other than the connection diffusion layer 4 is exposed, and the yield in semiconductor device manufacturing is significantly reduced. It was a factor.

An object of the present invention is to realize a semiconductor device manufacturing in which a higher-accuracy processing is realized and a yield is improved than that achieved in order to solve the above problems.

[0017]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a side of a trench formed in a Si substrate is distinguished from a side of a connection diffusion layer and a side of an isolation oxide film. As a method for converting the side wall, the side wall of the Si nitride film is left only on the separation side.

The method of manufacturing a semiconductor device according to a second aspect of the present invention is a method for differentiating the side of the diffusion layer for connection from the side of the isolation oxide film in the side wall of the trench formed in the Si substrate. , The side wall of the Si oxide film is dropped to the middle of the separation side.

The method of manufacturing a semiconductor device according to a third aspect of the present invention is a method for differentiating the side of the connection diffusion layer and the side of the isolation oxide film among the sidewalls of the trench formed in the Si substrate. A conductive film is formed on the insulating film, and then wet is used.

The method of manufacturing a semiconductor device according to a fourth aspect of the present invention is a method of differentiating the side of the diffusion layer for connection from the side of the isolation oxide film in the sidewall of the trench formed in the Si substrate. , The selective oxidation utilizing the Si nitride film and the wet are used together.

[0021]

According to the present invention, the film thickness of the Si nitride film and the film thickness of the Si oxide film for differentiating between the diffusion layer for connection and the oxide film for isolation are different from the diameter of the hole formed in the Si substrate. It is small, and the processing accuracy when forming those sidewalls is excellent.

[0022]

【Example】

Example 1. 1 to 3 are cross-sectional views in schematic steps showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention, and 1 to 15 are the same as those described above. 40
Is a resist mask provided on the first oxide film 5, and 41 is a nitride film sidewall that is a sidewall of each of the films 2 and 5. The drawings will be described below.

First, an element isolation oxide film 2 is formed in a desired region on a Si substrate 1 by a selective oxidation method, and a desired resist mask 3 pattern is formed by a well-known lithography method (FIG. 1). Next, the connection diffusion layer 4 is formed by ion-implanting n-type impurities such as arsenic and phosphorus and removing the resist mask 3 (FIG. 2). Also, CVD
The first oxide film 5 is deposited by the method (FIG. 3). The above steps of FIGS. 1 to 3 are the same as those described above.

Next, a resist mask 40 is opened by a lithography method so as to extend over the element isolation oxide film 2 and the connection diffusion layer 4, and then the first oxide film 5 and the element isolation oxide film 2 are anisotropically formed. A hole is formed by a reactive etching (FIG. 4).
Next, a Si nitride film (Si ₃ N ₄ ) is deposited by the CVD method, and the entire surface is etched back by anisotropic etching, so that the side walls of the first oxide film 5 and the element isolation oxide film 2 are formed. A nitride film sidewall 41 is formed (FIG. 5).

Subsequently, the Si substrate 1 is anisotropically etched using the oxide film 5 and the nitride film sidewall 41 as a mask to form a trench H (FIG. 6), and the inside of the trench H is exposed by a thermal oxidation method. The Si substrate 1 thus formed is oxidized (FIG. 7). At this time, the portion covered with the nitride film sidewall 41 is not oxidized.

Next, the nitride film side wall 41 on the connection diffusion layer 4 side is removed by anisotropic etching so that the nitride film side wall 41 on the element isolation oxide film 2 side remains by a desired thickness. The etching is completed (FIG. 8).

Next, a resist 7 is accumulated on the bottom of the trench H for protection during etching. This is resist 7
This can be done by resist etch back after applying. After that, the upper portion of the oxide film 6 for isolating the capacitor formed by thermal oxidation on the side of the diffusion layer 4 for connection is etched by anisotropic etching (FIG. 9). After that, the resist 7 in the trench H is removed. By the above method, only the sidewall of the trench H of the connection diffusion layer 4 can be selectively opened.
Hereinafter, FIGS. 10 to 13 are similar to the conventional manufacturing method corresponding to FIGS. 39 to 42, and therefore will not be described here.

As described above, according to the first embodiment, by utilizing the difference in etching rate between the nitride film sidewall 41 made of the Si nitride film and the capacitor isolation oxide film 6 made of the Si oxide film, the connection The exposed portion of the diffusion layer 4, that is, the contact area can be increased. Further, the control of the height of the nitride film sidewall is easy because the initial film thickness is small, and the processing accuracy can be improved.

Example 2. 14 to 19 are sectional views in a schematic process showing a second embodiment of the method for manufacturing a semiconductor device according to claim 2 of the present invention, and 50 is a Si nitride film formed on the first oxide film 5. .. The drawings will be described below.

First, similarly to the first embodiment, after forming the element isolation oxide film 2 and the connection diffusion layer 4, the first oxide film 5 and the Si nitride film 50 are sequentially deposited by the CVD method (FIG. 1).
4).

Next, a resist mask 40 is opened by a lithography method so as to extend over the element isolation oxide film 2 and the connection diffusion layer 4, and then the Si nitride film 50, the first oxide film 5 and the element isolation oxide film are formed. 2 is opened by anisotropic etching (FIG. 15).

Further, the Si substrate 1 is anisotropically etched to form a trench H having a desired depth (FIG. 16). After that, a capacitor isolation oxide film 6 is deposited by the CVD method, and subsequently, a resist 7 is accumulated on the bottom of the trench by applying a resist and etching the resist (FIG. 17).

Further, the capacitor isolation oxide film 6 is formed of Si.
Etching is performed by a process having selectivity with the nitride film 50, etching is stopped when the diffusion layer 4 for connection on the sidewall of the trench H is exposed, and part of the oxide film 2 for element isolation is exposed. Remove 7. By the above method, only the sidewall of the trench H of the connection diffusion layer 4 can be selectively opened. Since the manufacturing method of FIGS. 18 and 19 is the same as the conventional manufacturing method corresponding to FIGS. 39 and 40, description thereof will not be given here.

As described above, according to the second embodiment, the formation flow of the exposed portion of the connection diffusion layer 4 becomes relatively simple by forming the oxide film 6 for separating the capacitor on the entire surface and etching back. Therefore, the number of steps is smaller than in the conventional case and high-precision machining is possible.

Example 3. 20 to 23 are sectional views in schematic steps showing a third embodiment of the method for manufacturing a semiconductor device according to claim 3 of the present invention. Also in this case, similarly to the second embodiment, the trench H is formed and the CVD is performed. After depositing the oxide film 6 for capacitor isolation by the method, polycrystalline S that will become the first electrode 8
By depositing the i film and further performing anisotropic etching, a sidewall made of the first electrode 8 is formed (FIG. 2).
0).

Next, by applying the resist 7 and etching back the resist 7, the resist 7 is accumulated at the bottom of the trench H (FIG. 21). Then, using wet etching, S
The etching of the first oxide film 5 on the i-substrate 1 is stopped when the connection diffusion layer 4 on the sidewall of the trench H is exposed and the oxide film 2 for element isolation is exposed partway, and the resist 7 at the bottom of the trench H is removed. Remove (FIG. 22).

Further, after removing the Si nitride film 50, another polycrystalline Si film, that is, the first electrode 80 is deposited and anisotropically etched to form sidewalls (FIG. 2).
3). By the above method, the trench H of the connection diffusion layer 4 is formed.
Only the side wall portion is selectively opened, and the first electrode 8 of the capacitor is formed.
Can be connected with. Although not shown, the manufacturing process is the same as the conventional manufacturing method.

As described above, according to the third embodiment, by using, for example, wet etching at the time of opening the contact of the connection diffusion layer 4, contamination at the contact portion can be reduced.

Example 4. 24 to 32 are sectional views in schematic steps showing a fourth embodiment of the method for manufacturing a semiconductor device according to claim 4 of the present invention, and 44 is a contact region of the connection diffusion layer 4. The drawings will be described below. First, since the steps of FIGS. 24 to 26 are as described above,
It will not be explained here. Then, in FIG. 27, a resist mask (pattern) 40 is formed by a well-known transfer technique so as to extend over the element isolation oxide film 2 and the connection diffusion layer 4, and then the first oxide film 5 and the element isolation layer 40 are formed. Anisotropic etching is stored for half of the film thickness of the oxide film 2 for use. As a result, the element isolation oxide film 2 is formed so as to expose the n-type diffusion layer 4 with a film thickness 2 of about half left.

Next, as shown in FIG. 28, a Si nitride film is deposited by the CVD method, and anisotropic etching is performed on the Si nitride film under the condition that the Si substrate 1 has high selectivity. 1
A nitride film sidewall 41 is formed on the sidewalls of the oxide film 5 and the element isolation oxide film 2. In this case, anisotropic etching over-etching is performed so that the element isolation oxide film 2 does not remain on the Si surface in the trench opening portion.

Next, as shown in FIG. 29, the first oxide film 5, the element isolation oxide film 2 and the nitride film sidewall 41.
Using the as a mask, the Si substrate is anisotropically etched to form a trench H.

Then, as shown in FIG. 30, the exposed Si substrate 1 inside the trench H is oxidized by a thermal oxidation method to form a junction contact region with the connection (n-type) diffusion layer 4 at the sidewall of the trench H. An oxide film 6 for capacitor isolation having a thickness including the film thickness of 11 and the film thickness for separating the Si substrate 1 of the first electrode 8 formed inside the trench H is formed.

Then, as shown in FIG. 31, the Si nitride film sidewall 41 used as the oxidation resistant mask is removed by isotropic etching having selectivity with respect to each of the oxide films 5, 2 and 6.

Further, in FIG. 32, the oxide film 6 for separating the capacitor of the first electrode 8 from the Si substrate 1 is formed in the trench H by isotropic etching having selectivity with respect to the Si substrate 1, for example, hydrofluoric acid. Under-etching is performed on the thick oxide film 6 for isolating the capacitor H in the trench H so that it remains on the side wall and bottom. Thereby, the contact region 44 for joining the connecting diffusion layer 4 and the first electrode 8 can be selectively formed. The following manufacturing method is similar to the conventional example.

As described above, according to the fourth embodiment, by utilizing the wet etching at the time of opening the contact,
Contamination can be reduced as in the third embodiment. Further, by thickening the oxide film 6 for separating the capacitor, the etching back method of the resist 7 is not used at all, so that there is no possibility that the wetting liquid may soak due to the poor adhesion of the resist.

[0046]

As described above, according to the present invention, in the step of resist etch back, the oxide film at the bottom of the trench may be hidden and controlled so that the upper portion of the side wall of the trench is exposed. The margin is improved.
Moreover, since the initial film thickness is small, the side wall is controlled.
It is easier to control than the resist etch back method, and there is an effect that a semiconductor device manufacturing method in which the yield in the semiconductor manufacturing process is significantly improved can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 2 is a cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 3 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 4 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 5 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 6 is a cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 7 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 8 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 9 is a cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 10 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 11 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 12 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 13 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

FIG. 14 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 15 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 16 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 17 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 18 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 19 is a cross-sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to claim 2 of the present invention.

FIG. 20 is a cross-sectional view showing a third embodiment of the method for manufacturing a semiconductor device according to claim 3 of the present invention.

FIG. 21 is a cross-sectional view showing a third embodiment of the method for manufacturing a semiconductor device according to claim 3 of the present invention.

FIG. 22 is a cross-sectional view showing a third embodiment of the method for manufacturing a semiconductor device according to claim 3 of the present invention.

FIG. 23 is a sectional view showing Embodiment 3 of the method for manufacturing a semiconductor device according to Claim 3 of the present invention.

FIG. 24 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 25 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 26 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 27 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 28 is a cross-sectional view showing a fourth embodiment of the method of manufacturing a semiconductor device according to claim 4 of the present invention.

FIG. 29 is a cross-sectional view showing a fourth embodiment of the method for manufacturing a semiconductor device according to claim 4 of the present invention.

FIG. 30 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 31 is a sectional view showing Embodiment 4 of the method for manufacturing a semiconductor device according to Claim 4 of the present invention.

FIG. 32 is a cross-sectional view showing a fourth embodiment of the method for manufacturing a semiconductor device according to claim 4 of the present invention.

FIG. 33 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 34 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 35 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 36 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 37 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 38 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 39 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 40 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 41 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 42 is a cross-sectional view showing the method of manufacturing the conventional semiconductor device.

[Explanation of symbols] 1 Si substrate 2 Oxide film for blocking separation 4 Diffusion layer for connection 5 First oxide film 6 Oxide film for capacitor separation 7 Resist 8 First electrode 9 Capacitor dielectric film 10 Second electrode 11 Second oxide film 41 Nitride film sidewall 44 Contact region 50 Si nitride film 80 Another first electrode H trench

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor device in which a connection diffusion layer and a memory capacitor are formed on a Si substrate to connect the two to each other, the method comprising: forming an element isolation insulating film on the Si substrate; Forming the connecting diffusion layer on the surface layer of the Si substrate adjacent to the insulating film for isolation, and depositing a first insulating film on the entire surface of the insulating film for element isolation and the connecting diffusion layer. A step of opening the first insulating film and the element isolation insulating film in a desired pattern to expose a region including a surface of the connection diffusion layer, and the element isolation insulating film in the exposed region And a step of forming an insulating film sidewall made of a material different from that of the first insulating film on a sidewall of the first insulating film, the Si insulating film using the first insulating film and the insulating film sidewall as a mask. Substrate to desired depth Anisotropic etching to form a trench, a step of oxidizing the Si substrate forming side and bottom surfaces of the trench to form an oxide film for capacitor isolation, and an insulating film on the side of the diffusion layer for connection. Selectively removing sidewalls by anisotropic etching, and removing the upper portion of the capacitor isolation oxide film on the side of the diffusion layer for connection by anisotropic etching to remove the diffusion layer for connection from the trench sidewall. And a step of exposing the semiconductor device, the manufacturing method of the semiconductor device. 2. A method for manufacturing a semiconductor device in which a connection diffusion layer and a memory capacitor are formed on a Si substrate to connect the two to each other, the method comprising: forming an element isolation insulating film on the Si substrate; Forming the connecting diffusion layer on the surface layer of the Si substrate adjacent to the insulating film for isolation, and a first insulating film and a heterogeneous insulating film on the entire surface of the insulating film for element isolation and the connecting diffusion layer. And a step of exposing the region including the surface of the diffusion layer for connection by opening the first insulating film, the heterogeneous insulating film and the insulating film for element isolation into a desired pattern. Using the element isolation insulating film, the first insulating film, and the heterogeneous insulating film as a mask, anisotropically etching the Si substrate to a desired depth to form a trench, and forming a trench on the entire surface including the inner wall of the trench. The different insulation A step of forming a capacitor isolation insulating film made of a material different from that of the film, and applying a resist to the trench inner wall,
A step of leaving the resist only on the bottom of the trench by etching, and a step of removing the upper part of the capacitor isolation insulating film by anisotropic etching to expose the connection diffusion layer on the trench sidewall. A method for manufacturing a semiconductor device, comprising: 3. A method for manufacturing a semiconductor device in which a connection diffusion layer and a memory capacitor are formed on a Si substrate to connect the two, and a step of forming an element isolation insulating film on the Si substrate; Forming the connecting diffusion layer on the surface layer of the Si substrate adjacent to the insulating film for isolation, and a first insulating film and a heterogeneous insulating film on the entire surface of the insulating film for element isolation and the connecting diffusion layer. And a step of exposing the region including the surface of the diffusion layer for connection by opening the first insulating film, the heterogeneous insulating film and the insulating film for element isolation into a desired pattern. Using the element isolation insulating film, the first insulating film, and the heterogeneous insulating film as a mask, anisotropically etching the Si substrate to a desired depth to form a trench, and forming a trench, and the entire surface including the inner wall of the trench. Said heterogeneity A step of forming a capacitor isolation insulating film of a material different from that of the edge film, and depositing a conductor film on the capacitor isolation insulating film in the trench, and anisotropically etching to form a sidewall made of the conductor film. A step of forming a resist, a step of applying a resist and leaving a resist only on the bottom of the trench by etching, and a step of removing the upper part of the capacitor isolation insulating film by wet etching or anisotropic etching to remove the connection diffusion layer from the trench sidewall. A method of manufacturing a semiconductor device, comprising: 4. A method for manufacturing a semiconductor device in which a connection diffusion layer and a memory capacitor are formed on a Si substrate and the two are connected to each other, the method comprising the steps of forming an element isolation insulating film on the Si substrate; Forming the connecting diffusion layer on the surface layer of the Si substrate adjacent to the insulating film for isolation, and depositing a first insulating film on the entire surface of the insulating film for element isolation and the connecting diffusion layer. And a step of completely opening the first insulating film using a desired resist mask pattern and leaving the element isolation insulating film left, and the isolation insulating film and the first insulating film. Since the oxidation-resistant insulating film sidewall made of a material different from that of the first insulating film is formed on the side wall of the film, the isolation insulating film is eliminated and S
a step of etching until the i surface is exposed; a step of anisotropically etching the Si substrate to a desired depth using the first insulating film and the insulating film sidewall as a mask to form a trench; The Si substrate on the side wall and the bottom surface of the trench is oxidized using the insulating film sidewall as a mask pattern, and the thickness of the diffusion layer for connection at the same time as the connection contact diameter, the polysilicon for filling in the trench, and the Si substrate. A step of forming a capacitor isolation insulating film having a film thickness including a film thickness necessary for insulation with, and a step of selectively removing the insulating film sidewall with respect to the first insulating film, The capacitor isolation oxide film is selectively isotropically etched with respect to the Si substrate to expose the connection diffusion layer above the trench to form a contact region. And a step of forming the insulating film for exposing the connection diffusion layer on the sidewall of the trench and for forming the polysilicon for the first electrode to be formed next and the Si substrate at the same time. And a method for manufacturing a semiconductor device.