JPH05326869A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor memory device, where the semiconductor memory device can be prevented from deteriorating in yield due to the positional deviation of a mask. CONSTITUTION:A through-hole 39 used for contact with a bit line and a through- hole 49 used for contact with a storage node are provided to an interlayer insulating film 41 through a photolithography technique. Thereafter, a bit line 45 electrically connected to a source/drain region 35a through the intermediary of the through-hole 39 is formed, and a capacitor storage node 55 electrically connected to a source/drain region 35b through the intermediary of the through- hole 49 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of forming a through hole and a structure manufactured by the method.

[0002]

2. Description of the Related Art In recent years, the demand for semiconductor memory devices has expanded rapidly due to the remarkable spread of information equipment such as computers. Further, functionally, it is required to have a large-scale storage capacity and be capable of high-speed operation.
Along with this, technological developments relating to high integration of semiconductor memory devices and high-speed response or high reliability are being advanced.

Among semiconductor memory devices, DRAM (Dynamic) is used as a memory device capable of random input / output of stored information.
Random Access Memory).
Generally, a DRAM is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input / output with the outside.

FIG. 31 is a block diagram showing a structure of a general DRAM. In FIG. 31, the DRAM 1000
Is a memory cell array 1100 for accumulating a data signal of memory information, a row and column address buffer 1200 for externally receiving an address signal for selecting a memory cell forming a unit memory circuit, and the address signal Row decoder 1300 and column decoder 1 for designating a memory cell by decoding
400, a sense refresh amplifier 1500 that amplifies and reads a signal stored in a designated memory cell, a data-in buffer 1600 and a data-out buffer 1700 for data input / output, and a clock generator 1800 that generates a clock signal. And, are included.

A memory cell array 1100 occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for accumulating unit storage information in a matrix. FIG. 32 shows an equivalent circuit diagram of 4 bits of the memory cells forming the memory cell array 1100. The illustrated memory cell has one MOS (Meta).
1 shows a so-called one-transistor / one-capacitor type memory cell including an oxide semiconductor transistor 1900 and one capacitor 2000 connected to the transistor 1900. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and is widely used for large capacity DRAM.

FIG. 33 is a cross-sectional structural view of a memory cell of a conventional DRAM. Source / drain regions 3a and 3b are formed on the main surface of semiconductor substrate 1 with a space provided therebetween. Gate electrodes 5a and 5b are formed on the main surface of semiconductor substrate 1 with a space provided therebetween. 7 is a field oxide film. An interlayer insulating film 9 is formed on the main surface of semiconductor substrate 1.

A through hole 27 reaching the source / drain region 3a and a through hole 25 reaching the source / drain region 3b are formed in the interlayer insulating film 9. Bit lines 11 are formed on the interlayer insulating film 9. The bit line 11 is a source / source through the through hole 27.
It is electrically connected to the drain region 3a. An interlayer insulating film 13 and an insulating film 31 are formed so as to cover the bit line 11.

A storage node 15 is formed on the interlayer insulating film 9.
Are formed. Storage node 15 is electrically connected to source / drain region 3b through through hole 25. A dielectric film 17 is formed on the surface of the storage node 15. A cell plate 19 is formed on the dielectric film 17. The cell plate 19 is formed on the entire surface of the semiconductor substrate 1. An interlayer insulating film 21 is formed on the cell plate 19. Interlayer insulating film 21
Wirings 23a, 23b, and 23c are formed on the top of the wiring with a space between them.

A method of manufacturing the conventional DRAM memory cell shown in FIG. 33 will be described below. As shown in FIG. 34,
Through holes 27 reaching the source / drain regions 3a are formed in the interlayer insulating film 9 by using the photolithography technique. As shown in FIG. 35, a polycrystalline silicon film 29 is formed on the interlayer insulating film 9, and an interlayer insulating film 13 is formed on the polycrystalline silicon film 29. Predetermined patterning is applied to the interlayer insulating film 13 using a photolithography technique.

As shown in FIG. 36, the polycrystalline silicon film 29 is processed into the bit line 11 by etching the polycrystalline silicon film 29 using the interlayer insulating film 13 as a mask. As shown in FIG. 37, the insulating film 31 is formed on the entire main surface of the semiconductor substrate 1, and then anisotropic dry etching is performed on the entire surface of the insulating film 31 to etch the deposited portion of the insulating film 31 or more. Insulating film 31 only on the side wall of 11
Remains. As a result, the bit line 11 is insulated from other wiring.

As shown in FIG. 38, the through hole 25 reaching the source / drain region 3b is formed by using the photolithography technique. As shown in FIG. 39, a polycrystalline silicon film is formed on the entire main surface of semiconductor substrate 1, and the polycrystalline silicon film is processed by photolithography to form storage node 15. From the state of FIG. 39 to FIG.
The description of the steps up to the state 3 will be omitted.

[0012]

As described above, conventionally, the through holes 25 and 27 have been formed by using the photolithography technique. Although there is a process of mask alignment in the photolithography technique, in this mask alignment process, the displacement of the mask inevitably occurs even if any good device is used. Therefore, the through holes 25 and 27 are surely formed on the source / drain regions 3a and 3b by setting the dimensions of the source / drain regions 3a and 3b to be equal to or larger than a predetermined value in consideration of the positional deviation.

However, as the structure of the capacitor is further reduced,
The dimensions of the source / drain regions 3a and 3b have been reduced. Therefore, the through holes 25 and 27 may not be formed on the source / drain regions 3a and 3b due to the displacement of the mask.

The present invention has been made to solve the above conventional problems. An object of the present invention is to provide a method of manufacturing a semiconductor memory device, which can prevent the yield of the semiconductor memory device from decreasing due to the displacement of the mask.

Another object of the present invention is to provide a semiconductor memory device capable of preventing a reduction in the yield of the semiconductor memory device due to the displacement of the mask.

[0016]

A first aspect of the present invention is a method of manufacturing a semiconductor memory device in which charges are stored in a capacitor to store information, which is formed on a main surface of a semiconductor substrate with a space provided therebetween. The first and second impurity regions, and the first
Forming an insulating layer covering the first and second impurity regions on the main surface of a semiconductor substrate having a gate electrode formed on the main surface between the impurity region and the second impurity region; A step of simultaneously forming a first through hole reaching the first impurity region and a second through hole reaching the second impurity region in the layer, and electrically forming the first through hole in the first impurity region via the first through hole. The method includes the step of forming a bit line to be connected, and the step of forming a storage node of a capacitor electrically connected to the second impurity region through the second through hole.

A second aspect of the present invention is a semiconductor memory device for storing charges by accumulating charges in a capacitor, wherein a semiconductor substrate having a main surface and a main surface formed with a space therebetween. First and second impurity regions, a gate electrode formed on the main surface between the first impurity region and the second impurity region, and a first through hole formed on the main surface and reaching the first impurity region. And an insulating layer having a second through hole reaching the second impurity region, a bit line formed on the insulating layer and electrically connected to the first impurity region through the first through hole, and the insulating layer And a storage node of a capacitor which is electrically connected to the second impurity region through the second through hole, and the first and second semiconductor chips. The distance between the first through hole and the second through hole of the first semiconductor chip is the same as the distance between the first through hole and the second through hole of the second semiconductor chip.

[0018]

In the past, through holes for bit line contacts and through holes for storage node contacts were separately formed. The probability that a through hole will not be formed at a desired position due to the displacement of the mask is 1
If it is set to / 2, the probability that the through hole is formed at a desired position becomes 1/2. Considering this probability, the probability that two through holes are formed at desired positions in the conventional method is 1/4. On the other hand, according to the first aspect of the present invention, the first through hole which is the through hole for the bit line contact and the second through hole which is the through hole for the storage node contact are simultaneously formed. Therefore, the probability that both through holes are formed at desired positions is halved.

A second aspect of the present invention is the first aspect of the present invention.
A semiconductor memory device manufactured by using the above aspect. According to a first aspect of the present invention, a first through hole which is a through hole for a bit line contact and a second through hole which is a through hole for a storage node contact are simultaneously formed. In the second aspect, the distance between the first through hole and the second through hole is the same for all semiconductor chips.

[0020]

【Example】

(First Embodiment) FIG. 1 is a sectional view of a memory cell of a DRAM manufactured by using the first embodiment of the present invention. Source / drain regions 35a and 35b are formed on main surface 34 of semiconductor substrate 33 with a space provided therebetween. Also, the main surface 3
4, a gate electrode 37a, which is a word line with a space between
37b is formed. Source / drain region 35
An interlayer insulating film 41 is formed on the main surface 34 so as to cover the a, 35b and the gate electrodes 37a, 37b. Through holes 39 reaching the source / drain regions 35a and through holes 49 reaching the source / drain regions 35b are formed in the interlayer insulating film 41.

A bit line 45 is formed on the interlayer insulating film 41. Bit line 45 is made of, for example, doped polycrystalline silicon alone or a polycrystalline silicon on which a refractory metal is formed. Bit line 45 is electrically connected to source / drain region 35a through through hole 39. An interlayer insulating film 47 and an insulating film 69 are formed so as to cover the bit line 45.

The storage node 5 is formed on the interlayer insulating film 41.
5 is formed. A polycrystalline silicon film 65 is embedded in through hole 49, and polycrystalline silicon film 65 is electrically connected to source / drain region 35b and storage node 55. Reference numeral 47 denotes an interlayer insulating film, which is left without being completely removed during manufacturing.

A dielectric film 57 is formed on the surface of the storage 55. A cell plate 59 is formed on the dielectric film 57.
Are formed. An interlayer insulating film 61 is formed on the cell plate 59. The wiring 6 is formed on the interlayer insulating film 61.
3a, 63b, 63c are formed with a space between them.

A method of manufacturing the memory cell of the DRAM shown in FIG. 1 will be described below. As shown in FIG.
Through hole 39 using photolithography technology,
49 were formed simultaneously. As shown in FIG. 3, the main surface 34
A polycrystalline silicon film 65 and an interlayer insulating film 47 were sequentially formed on the entire surface of the. A resist 67 was formed on the interlayer insulating film 47, and the resist 67 was subjected to predetermined patterning.

As shown in FIG. 4, the interlayer insulating film 47 was selectively removed by etching using the resist 67 as a mask to remove the resist 67. The interlayer insulating film 47 is left at the through hole 49 as well because it is difficult to etch because this portion is recessed and it is deposited relatively thicker than other portions, so overetching must be done too much. For example, the interlayer insulating film 47 remains. As shown in FIG. 5, the polycrystalline silicon film 65 was selectively removed by etching using the interlayer insulating film 47 as a mask to form the bit line 45. Since the interlayer insulating film 47 is also present in the through hole 49, the polycrystalline silicon film 65 is formed in the through hole 49.
Remained.

As shown in FIG. 6, an insulating film 69 is formed on the entire main surface 34. Then, the insulating film 69 is entirely etched, and the insulating film 6 is formed on the side wall of the bit line 45 as shown in FIG.
9 left. Although the interlayer insulating film 47 remains on the polycrystalline silicon film 65 in FIG. 7, it may be removed by increasing the amount of overetching. As shown in FIG. 8, a polycrystalline silicon film is formed on the entire main surface 34, and the polycrystalline silicon film is subjected to predetermined patterning by using a photolithography technique, whereby storage node 55 is formed.
Formed. After that, the state shown in FIG. 1 was obtained using a normal method.

(Second Embodiment) In the first embodiment, the interlayer insulating film 47 remains on the polycrystalline silicon film 65 filled in the through hole 49 as shown in FIG. It is the second embodiment that reliably removes.

After the step shown in FIG. 7 of the first embodiment, a resist 71 was formed on the entire main surface 34 as shown in FIG. 9, and the resist 71 was subjected to predetermined patterning. And Figure 1
As shown in 0, the interlayer insulating film 47 was removed using the resist 71 as a mask, and then the resist 71 was removed. Then, the storage node 55 was formed as shown in FIG. 11 using the same method as in the first embodiment.

(Third Embodiment) In the second embodiment, a special process is added to remove the interlayer insulating film 47 remaining in the through holes 49. However, a polycrystalline silicon film used as a material for the bit line is formed. By reducing the diameter of the through hole 49 or increasing the thickness of the polycrystalline silicon film at the time of formation, it is possible to perform the process described in the second embodiment.
The interlayer insulating film 47 does not remain in the through hole 49. This will be explained below. Through hole 39, as shown in FIG.
A polycrystalline silicon film 73 was formed on the interlayer insulating film 41 provided with 49. The diameter of the through hole 49 is smaller than that of the first embodiment. Therefore, the polycrystalline silicon film 73 is buried in the through hole 49. Figure 1
As shown in FIG. 3, the interlayer insulating film 47 was formed on the polycrystalline silicon film 73, and the interlayer insulating film 47 was subjected to predetermined patterning by using the photolithography technique. When the interlayer insulating film 47 is etched by this photolithography technique, the etching is performed stronger than in the first embodiment, and the through hole 4
The interlayer insulating film 47 is not left on the surface of the insulating film 9.

As shown in FIG. 14, the polycrystalline silicon film 73 is removed by etching using the interlayer insulating film 47 as a mask.
The polycrystalline silicon film 73 is used as the bit line 45. Since the thickness of the polycrystalline silicon film 73 in the portion of the through hole 49 is relatively larger than that of the other portions, the polycrystalline silicon film 73 remains in the through hole 49. Then, as shown in FIG. 15, the insulating film 69 and the storage node 55 were formed using the same method as in the first embodiment.

(Fourth Embodiment) In the third embodiment, the diameter of the through hole 49 is reduced or the thickness of the polycrystalline silicon film that is the material of the bit line is increased so that the interlayer insulating film is formed in the through hole 49. However, even if the diameter of the through hole 49 is increased or the polycrystalline silicon film that is the material of the bit line is formed thin, the interlayer insulating film does not remain in the through hole 49. It is possible to This will be explained below. As shown in FIG. 16, the through holes 39, 49 are formed in the interlayer insulating film 41.
After the formation of the polycrystalline silicon film 75, the polycrystalline silicon film 75
Are formed extremely thick so that the through holes 39 and 49 are filled with the polycrystalline silicon film 75. Then, when the entire surface of the polycrystalline silicon film 75 is anisotropically etched, the portions of the polycrystalline silicon film 75 inside the through holes 39 and 49 are relatively thicker than the other portions. It became such a structure.

As shown in FIG. 17, a polycrystalline silicon film and an interlayer insulating film 47 are sequentially formed on the entire main surface 34, and the polycrystalline silicon film is removed by etching using the interlayer insulating film 47 as a mask to form bit lines 45. .. The polycrystalline silicon film, which is the material of the bit line 45, can be formed thin because it is not necessary to fill the through holes 39 and 49. Therefore, according to the fourth embodiment, there is an effect that the step difference can be reduced. As shown in FIG. 18, the insulating film 69 and the storage node 55 were formed in the same manner as in the first embodiment.

(Fifth Embodiment) The fifth embodiment of the present invention will be described below. As shown in FIG. 19, the through hole 3
A polycrystalline silicon film 77 is formed on the interlayer insulating film 41 on which the layers 9 and 49 are formed, and an interlayer insulating film 79 is formed on the polycrystalline silicon film 77. It was patterned. As shown in FIG. 20, the polycrystalline silicon film 77 was removed by etching using the interlayer insulating film 79 as a mask to form the bit line 45. Since the interlayer insulating film 79 is also present on the through hole 49, the polycrystalline silicon film 77 remains in the through hole 49. Then, the interlayer insulating film 79 was removed.

As shown in FIG. 21, a thick interlayer insulating film 81 was deposited on the entire main surface 34, and the entire surface was etched back. As shown in FIG. 22, a through hole 83 was formed in the interlayer insulating film 81 by using the photolithography technique. Since the dimension of polycrystalline silicon film 77 is larger than the dimension of source / drain region 35b, through hole 83 is formed on polycrystalline silicon film 77 even if a slight mask shift occurs. Next, as shown in FIG. 23, a polycrystalline silicon film was formed on the entire main surface 34 and subjected to predetermined patterning to form storage node 85.

(Sixth Embodiment) In the first embodiment, the insulating film is etched when forming the insulating film 69 as shown in FIG. 7, but a polycrystalline silicon film which is an electrode connected to the storage node is used. 65 exposed and the interlayer insulating film 41
It is not easy for mass production to stop the etching without excessively shaving. Therefore, it can be easily stopped by using the sixth embodiment. This will be explained below.

As shown in FIG. 24, interlayer insulating film 41 was formed on main surface 34, and silicon nitride film 87 was formed on interlayer insulating film 41. Then, the through holes 39 and 49 were simultaneously formed by using the photolithography technique. Figure 25
As shown in, a polycrystalline silicon film 65 was formed on the main surface 34, and an interlayer insulating film 47 was formed on the polycrystalline silicon film 65. Then, a resist 67 was applied on the interlayer insulating film 47, and the resist 67 was subjected to predetermined patterning.

As shown in FIG. 26, the interlayer insulating film 67 was selectively removed by etching using the resist 67 as a mask. Then, the resist 67 was removed. Through hole 49
However, the interlayer insulating film 47 remains for the same reason as in the first embodiment. As shown in FIG. 27, the polycrystalline silicon film 65 is selectively removed by etching using the interlayer insulating film 47 as a mask to form the bit line 45. Since the interlayer insulating film 47 is also present at the through hole 49, the through hole 49
The polycrystalline silicon film 65 remains inside.

As shown in FIG. 28, an insulating film 69 is formed on the entire main surface 34. As shown in FIG. 29, the insulating film 69
Was entirely etched to leave the insulating film 69 only on the side wall of the bit line 45. Since the silicon nitride film 87 is present on the inter-layer insulation film 41, the inter-layer insulation film 41 is formed during this etching.
Can't be scraped. Since the interlayer insulating film 41 is not scraped, the etching time can be lengthened, and therefore the interlayer insulating film 47 does not remain on the polycrystalline silicon film 65. Then, as shown in FIG. 30, the storage node 55 was formed in the same manner as in the first embodiment.

[0039]

According to the first aspect of the present invention, since the first through hole which is the through hole for the bit line contact and the second through hole which is the through hole for the storage node contact are formed at the same time, The probability that the first and second through holes are formed at desired positions is higher than in the conventional case, and therefore the yield of the semiconductor memory device can be improved.

Further, due to the structural feature that the storage node is located above the bit line, according to the conventional method, the depth of the through hole for the storage node contact is larger than the depth of the through hole for the bit line contact. Will grow. However, according to the first aspect of the present invention, since the first through hole and the second through hole are formed at the same time, the through hole for the contact of the storage node can be made shallower than before. Therefore, according to the first aspect of the present invention, the aspect ratio of the through hole for the bit line contact can be reduced, and the conductive layer can be easily embedded in the through hole.

Since the second aspect of the present invention is manufactured by using the first aspect, it is possible to prevent the yield of the semiconductor memory device from being lowered due to the displacement of the mask.

[Brief description of drawings]

FIG. 1 is a DRA manufactured by using a first embodiment of the present invention.
It is sectional drawing of the memory cell of M.

FIG. 2 is a sectional view showing a first step of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of the first embodiment of the present invention.

FIG. 4 is a sectional view showing a third step of the first embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth step of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a fifth step of the first embodiment of the present invention.

FIG. 7 is a sectional view showing a sixth step of the first embodiment of the present invention.

FIG. 8 is a sectional view showing a seventh step of the first embodiment of the present invention.

FIG. 9 is a sectional view showing a first step of the second embodiment of the present invention.

FIG. 10 is a sectional view showing a second step of the second embodiment of the present invention.

FIG. 11 is a sectional view showing a third step of the second embodiment of the present invention.

FIG. 12 is a sectional view showing a first step of the third embodiment of the present invention.

FIG. 13 is a sectional view showing a second step of the third embodiment of the present invention.

FIG. 14 is a sectional view showing a third step of the third embodiment of the present invention.

FIG. 15 is a sectional view showing a fourth step of the third embodiment of the present invention.

FIG. 16 is a sectional view showing a first step of the fourth embodiment of the present invention.

FIG. 17 is a sectional view showing a second step of the fourth embodiment of the present invention.

FIG. 18 is a sectional view showing a third step of the fourth embodiment of the present invention.

FIG. 19 is a sectional view showing a first step of the fifth embodiment of the present invention.

FIG. 20 is a sectional view showing a second step of the fifth embodiment of the present invention.

FIG. 21 is a sectional view showing a third step of the fifth embodiment of the present invention.

FIG. 22 is a sectional view showing a fourth step of the fifth embodiment of the present invention.

FIG. 23 is a sectional view showing a fifth step of the fifth embodiment of the present invention.

FIG. 24 is a sectional view showing a first step of the sixth embodiment of the present invention.

FIG. 25 is a sectional view showing a second step of the sixth embodiment of the present invention.

FIG. 26 is a sectional view showing a third step of the sixth embodiment of the present invention.

FIG. 27 is a sectional view showing a fourth step of the sixth embodiment of the present invention.

FIG. 28 is a sectional view showing a fifth step of the sixth embodiment of the present invention.

FIG. 29 is a sectional view showing a sixth step of the sixth embodiment of the present invention.

FIG. 30 is a sectional view showing a seventh step of the sixth embodiment of the present invention.

FIG. 31 is a block diagram of a DRAM.

FIG. 32 is an equivalent circuit diagram of a memory cell.

FIG. 33 is a cross-sectional view of a conventional DRAM memory cell.

FIG. 34 is a cross-sectional view showing a first step of a method for manufacturing a conventional DRAM memory cell.

FIG. 35 is a sectional view showing a second step of the method for manufacturing the memory cell of the conventional DRAM.

FIG. 36 is a sectional view showing a third step of the method for manufacturing the memory cell of the conventional DRAM.

FIG. 37 is a cross-sectional view showing a fourth step of the method for manufacturing the memory cell of the conventional DRAM.

FIG. 38 is a sectional view showing a fifth step of the method for manufacturing the memory cell of the conventional DRAM.

FIG. 39 is a sectional view showing a sixth step of the method for manufacturing the memory cell of the conventional DRAM.

[Explanation of symbols]

 33 semiconductor substrate 34 main surface 35a, 35b source / drain regions 37a, 37b gate electrodes 39, 49 through hole 41 interlayer insulating film 45 bit line 55 storage node

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device in which electric charges are stored in a capacitor to store information, comprising: a first and a second impurity region formed on a main surface of a semiconductor substrate with a space therebetween; A gate electrode formed on the main surface between the first impurity region and the second impurity region; and the first surface on the main surface of the semiconductor substrate.
And a step of forming an insulating layer covering the second impurity region, and simultaneously forming in the insulating layer a first through hole reaching the first impurity region and a second through hole reaching the second impurity region. And a step of forming a bit line electrically connected to the first impurity region through the first through hole, and electrically connected to the second impurity region through the second through hole. Forming a storage node of the capacitor described above. 2. A semiconductor memory device for accumulating charges in a capacitor to store information, comprising: a semiconductor substrate having a main surface; and first and second impurity regions formed on the main surface with a space therebetween. A gate electrode formed on the main surface between the first impurity region and the second impurity region; a first through hole formed on the main surface and reaching the first impurity region; An insulating layer having a second through hole reaching the second impurity region; a bit line formed on the insulating layer and electrically connected to the first impurity region through the first through hole; A first and a second semiconductor chip having a storage node of the capacitor formed on the insulating layer and electrically connected to the second impurity region through the second through hole; The distance between the first through hole and the second through hole of the first semiconductor chip is the same as the distance between the first through hole and the second through hole of the second semiconductor chip. , Semiconductor memory device.