JPH05326728A - Wiring pattern structure in semiconductor device - Google Patents

Abstract

PURPOSE:To form wiring pattern structure in semiconductor device, which has a little restriction on the applicable positions by which the increase in electric resistance is avoided without fail. CONSTITUTION:Within the title semiconductor device, the first interlayer films 1 as underneath films are formed so as to provide the first wiring patterns 21-23 thereon. Besides, the second interlayer films are formed extending over the whole surface above the first interlayer films 1 so as to form the second wiring patterns 41. The first wiring patterns 21-23 and the second wiring patterns 41 are formed on the positions orthogonal to one another. Furthermore, the widened parts 5a, 5b are formed on both sides of these second wiring patterns 41 corresponding to the parts having flatly intersecting patterns such as the parts at relatively wider intervals of the first wiring patterns 21-23 (between pattern 22 and pattern 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving a wiring pattern structure in a semiconductor device.

[0002]

2. Description of the Related Art As is well known, LSIs are required to have high speed, low power consumption and high degree of integration, and in order to fulfill these requirements, miniaturization of circuit patterns is an essential technique. Is becoming In logic LSIs such as micro computers and memory LSIs such as dynamic RAMs and static RAMs, the minimum circuit pattern size (pattern size) is, for example, 1.0 to 1.2 μm.
It is miniaturized from about one to about 0.8 μm,
In the future, it is becoming necessary to form finer circuit patterns of about 0.5 to 0.6 μm or less.

At the same time as the miniaturization of such circuit patterns progresses, the formation of wiring patterns for each LSI is also referred to as so-called multi-layer wiring from a one-layer structure to a two-layer structure or a three-layer structure. The multi-layered technology has been promoted, and this technology has become very important, and this technology is becoming indispensable for realizing future demands.

In particular, the minimum circuit pattern size is 0.5
It is said that in an LSI that requires the formation of a circuit pattern of approximately 0.6 μm or finer than that, it is necessary to form a wiring pattern having a multilayer structure.

FIG. 5 shows a wiring pattern of a commonly used multilayer structure. 5A is a top view, FIG. 5B is a cross-sectional view, and FIG. 5C is a perspective view. In each figure, 51 is, for example, a first interlayer film containing a silicon oxide film (hereinafter abbreviated as SiO ₂ film) as a main component, and 52 is a metal film or a polycrystalline film on the first interlayer film 51. It is a first wiring pattern formed of a silicon film.

Reference numeral 53 is a second interlayer film which is formed on the entire surfaces of the first interlayer film 51 and the first wiring pattern 52, and which has, for example, a SiO ₂ film as a main component. Reference numeral 54 is a second wiring pattern formed of a thin film containing a metal such as aluminum as a main component. In the example shown in this figure,
The second wiring pattern 54 is orthogonal to the first wiring pattern 52, but depending on the circuit pattern, there are portions where the same pattern is repeated and portions where irregular patterns are arranged.

The thickness of the first wiring pattern 52 is, for example,
The thickness of the second wiring pattern 54 is, for example, about 4000 to 12000Å, and the thickness of the first interlayer film 51 is, for example, 150.
It is about 0 to 10000Å, and the thickness of the second interlayer film 53 is generally about 3000 to 15000Å.

By adopting such a multilayer wiring structure, it is expected that the degree of freedom in pattern layout will be increased when designing a circuit pattern, and that it will greatly contribute to speeding up and high integration of LSI. At the same time, the increase in the degree of freedom will significantly reduce the design man-hours. However, such a conventional multilayer wiring structure also has the technical problems described below.

[0009]

That is, in the multilayer wiring structure shown in FIG. 5, the first wiring pattern 52
When the second interlayer film 53 is formed on the upper portion of the first wiring pattern 52, a surface step 53a is formed obliquely above the corner of the first wiring pattern 52. Then, when the second wiring pattern 54 is formed on the second interlayer film 53 with the surface step 53a generated,
A surface step 54a having a further increased step is formed in a portion corresponding to the surface step 53a.

The generation of such a step is caused by the wiring pattern 5
2 and 54 are usually formed by a sputtering method or a CVD method, and a thin film formed by such a method is greatly influenced by the shape of the base, and the surface step 54
In the part a, the film thickness is about 40 compared to the other parts.
It will be about 70%.

Further, as shown in FIG. 5, in particular, in a portion where the distance between the first wiring patterns 52 is relatively large, two surface steps 53b are connected diagonally above the corners of the pattern 52, and this occurs. The second wiring pattern 54 formed on the upper part becomes a groove-like surface step 54b having a considerably deep groove, and the film thickness is further reduced at the surface step 54b.
It becomes about 0 to 60%, and such a decrease in film thickness is further magnified as the number of layers of the wiring structure increases.

By the way, when the film thickness of the wiring pattern is reduced as described above, the electric resistance is increased at that portion, and this increase is relatively affected, for example, in an LSI in which the minimum dimension of the wiring pattern is around 0.8 μm. However, the degree of integration is increased and, for example, the minimum dimension of the wiring pattern is 0.5 to 0.6.
An LSI having a size of about μm or less causes a very big problem.

That is, when the electric resistance of the wiring pattern increases, the transmission speed of the electric signal becomes slower. In particular, since the wiring pattern having a fine dimension is usually used as a signal wiring, the resistance increases locally. If there are multiple points,
Even if the delay is small at one location, if delay occurs at multiple locations, it cannot be ignored.

To solve the problem of such a surface step, for example, in Japanese Unexamined Patent Publication No. 2-128449, a dummy pattern having a thickness similar to the wiring film thickness is provided in a region where wiring is not formed. , A technique of flattening the pattern on the upper layer side has been proposed, but in this solution, there is a constraint between the wirings located on both sides of the dummy pattern and the width of the dummy pattern itself, which can be actually applied. The places are greatly limited.

The present invention has been made in view of the problems of the prior art as described above, and an object thereof is a semiconductor in which an increase in electric resistance is surely eliminated without restricting application places. It is to provide a pattern structure in a device.

[0016]

In order to achieve the above object, the first invention has a plurality of wiring patterns formed in layers vertically with an interlayer film interposed therebetween, and these wiring patterns are flat. In the pattern structure of the semiconductor device that intersects with each other as viewed from above, a widened portion is formed in at least one of the wiring patterns formed in layers so as to correspond to the intersecting portion.

A second aspect of the invention is a pattern in a semiconductor device, which has a plurality of wiring patterns formed in layers vertically with an interlayer film interposed therebetween, and these wiring patterns intersect in a plan view. In the structure, a deforming portion that equalizes the intervals between the wiring patterns corresponding to the intersecting portions is formed on the lower layer side of the wiring patterns formed in layers.

Furthermore, the third invention has a plurality of wiring patterns which are formed in layers vertically with an interlayer film interposed therebetween, and
In a pattern structure in a semiconductor device in which these wiring patterns intersect with each other in a plan view, a low resistance substance is filled in a thin portion generated at the intersection on an upper layer side of the wiring pattern formed in layers. Is characterized by.

[0019]

According to the first aspect of the present invention, the widened portion is formed in either one of the upper and lower layers corresponding to the intersection of the wiring patterns where the surface step is generated. Providing a widened portion on the pattern directly increases the cross-sectional area of the wiring pattern on the upper layer side, while forming a widened portion on the wiring pattern on the lower layer side reduces the surface step and indirectly connects the wiring on the upper layer side. The cross-sectional area of the pattern becomes large.

In this case, if the widened portions are appropriately combined in the wiring patterns of the upper and lower layers in consideration of the restriction of the pattern layout, the places where the widened portions can be formed are widened and the degree of freedom is increased.

Further, according to the second aspect of the present invention, the deformed portion for equalizing the intervals between the wiring patterns is formed on the lower layer side in correspondence with the intersection of the wiring patterns where the surface step is generated. Is alleviated.

Further, according to the third invention, since the low resistance material is filled in the thin portion where the surface step is generated, it is possible to compensate for the reduction in the thickness of the wiring pattern.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a wiring pattern structure in a semiconductor device according to the present invention. In the semiconductor device shown in the figure, as a base, for example, a first interlayer film 1 containing a SiO ₂ film as a main component is used.
There are formed, on the upper, for example, a metal or polycrystalline silicon is deposited in a film form by a CVD method or the like, by an etching process, is provided first wiring pattern 2 ₁ to 2 ₃ formed in a predetermined shape Has been.

Further, above the first interlayer film 1 and the first wiring patterns 2 ₁ to 2 _{3 over} the entire surface, for example, S
A second interlayer film 3 containing an iO ₂ film as a main component is formed. Then, on the second interlayer film 3, in the same manner as the first wiring pattern 2, for example, a thin film-shaped second wiring pattern 4 containing a metal such as aluminum as a main component is formed.
_1, 4 ₂ are formed.

In this embodiment, the first wiring pattern 2 _1-
2 ₃ is a pair of patterns 2 _1, 2 ₂ located on the left side of the figure
Are formed in parallel at relatively narrow intervals, and the remaining pattern 2
₃ orthogonal, formed in parallel at a relatively large distance between the pattern 2 _2, a first wiring pattern 2 ₁ to 2 ₃ second wiring patterns 4 _1, 4 ₂ and is, across the second interlayer film 3 The basic part of the wiring structure is
This is the same as the conventional type shown in FIG.

In the multilayer wiring structure having such a positional relationship, the second wiring pattern 4 ₁ ,
4 ₂ corresponds to a portion where the patterns intersect in a plan view such as a portion (between the pattern 2 ₂ and the pattern 2 ₃ ) in which the distance between the first wiring patterns 2 ₁ to 2 ₃ is relatively large. As described above, a portion where the film thickness is locally thin occurs.

Therefore, in the embodiment shown in FIG.
Widened portions 5a and 5b are formed on both sides of the pattern 4 ₁ so as to correspond to portions where the film thickness of the second wiring pattern 4 ₁ is locally thin. When such widened portions 5a and 5b are formed, the cross-sectional area of the second wiring pattern 41 is partially increased in this portion, the electric resistance is reduced, and the increase in the electric resistance due to the surface step can be reduced. .. Widened portion 5a,
The width and the length of 5b are set to various sizes depending on the degree of the surface step difference which varies depending on the thickness of the first wiring pattern 2 and the thickness of the second interlayer film 3, for example.

In the embodiment shown in FIG. 1 (b), the distance between the first wiring patterns 2 _{2 and} 2 ₃ is relatively large, and the surface step corresponding to this portion has a deep groove shape so that the electric resistance is reduced. since an increase that is more pronounced than the increase in other portions is predicted, the second wiring patterns 4 ₁ enlarged portion 5b on both sides only position corresponding to the portion ', 5b' provided to other portions Forms a widened portion 5a 'only on one side of the pattern 4 ₁ .

In the embodiment shown in FIG. 1 (c), the second wiring patterns 4 _1, 4 ₂ are formed perpendicular to the upper portions of the first wiring patterns 2 ₁ -2 _{3 so that} the two wirings are closely and parallel to each other. and which, widened portion 5 to each of the second wiring patterns 4 _1, 4 ₂ does not face portion
a '' and 5b '' are formed. In this case, the width and length of the widened portion 5b ″ are determined by the second wiring patterns 4 _1, 4 ₂
It can be determined corresponding to the interval between.

[0030] Figure 2 shows another embodiment of the present invention, in this example, also forms the widened portion 6a and the deformed portion 6b to the first wiring pattern 2 ₁ to 2 _3, the first wiring pattern Two
It is shown that the equalization of the intervals between _{1 and} 2 ₃ reduces the reduction in the thickness of the second wiring patterns 4 _{1 and} 4 ₂ formed on the upper portion thereof.

In the embodiment shown in FIG. 2 (a), the widened portions 6a protruding from both sides are formed in the portions where the first wiring patterns 2 _{2 and} 2 ₃ have relatively large intervals. This embodiment is effective when the second wiring patterns 4 _{1 and} 4 ₂ are not shown, but other patterns are close to each other, and the widened portion cannot be formed in the second wiring patterns 4 _{1 and} 4 _2. ..

In the embodiment shown in FIG. 2B, a deformation 6b having substantially the same width is formed in one of the patterns 2 ₃ in a portion where the distance between the first wiring patterns 2 _{2 and} 2 ₃ is relatively large, and the deformation portion is formed. By bringing 6b close to the other pattern 2 ₂
The intervals between the wiring patterns 2 _{1 to} 2 ₃ are equalized to prevent the reduction in the thickness occurring in the second wiring patterns 4 _{1 and} 4 ₂ .

FIG. 3 shows yet another embodiment,
In this embodiment, as in the case shown in FIG. 2 (a), the second wiring pattern 4 _1, 4 ₂ and close the other pattern, the second wiring patterns _41, 42 widening portion ₂ is This is an example that is effective when it cannot be formed, and the first wiring pattern 2 ₁
A trapezoidal widened portion 6c that protrudes outward is formed at the same time, and in the portion between the first wiring patterns 2 _{2 and} 2 ₃ where the distance between the wiring patterns is relatively large, the pattern 2 ₃ is close to the pattern 2 ₂ side. The deformed portion 6d is formed, and the deformed portion 6d is formed.
And the portion where the original pattern 2 ₃ is connected, when adopting the pattern shape shown in FIG. 3 forming the second wiring patterns 4 _1, 4 ₂ and oblique widening portion 6e in plan view , the second wiring patterns 4 _1, 4 ₂ without providing a deformation such as widening portion, can be significantly reduced, reducing the thickness due to the surface step. Incidentally, not shown detailed drawing, the widened portion and the deformed portion of the above-described embodiment the first and second wiring patterns 2 ₁ -
Proper combination of 2 _3, 4 _{1 and} 4 ₂ makes it possible to effectively exert the effect of the present invention because the degree of freedom becomes extremely large depending on the combination even if there are restrictions on the layout of the wiring pattern.

FIG. 4 shows another embodiment of the present invention. While each of the above embodiments were intended to provide a widened portion or deformation unit to either the first or the second wiring patterns 2 ₁ to 2 _3, 4 _1, 4 _2, in this embodiment, the wiring pattern It is possible to eliminate the decrease in the thickness of the pattern due to the step difference on the surface without changing the above.

FIG. 4A is a top view of the wiring pattern of this embodiment, and FIG. 4B is a sectional view thereof. In this embodiment, the lower first wiring patterns 2 ₁ to 2 ₃ are formed by a usual method, and the second interlayer film 3 is formed thereon. Next, a thin film containing a metal such as aluminum as a main component, which will be the second wiring pattern, is formed by a sputtering method to a thickness of, for example, about 1500 to 10000Å, and on top of this, for example, a polycrystalline silicon film or tungsten,
Low resistance material of high melting point metal film such as titanium, molybdenum,
For example, a thickness of about 1500 to 15000Å is formed by the CVD method, and then anisotropic etching is performed on the entire surface, and etching back is performed.

The second wiring patterns 4 _{1 and} 4 ₂ formed by the above-mentioned processing have a sidewall-shaped or groove-shaped polycrystalline silicon film or a high melting point metal film or the like in a portion where a surface step is generated. The resistance materials 7a and 7b are left in the state, and the low resistance materials 7a and 7b compensate for the decrease in the pattern thickness due to the surface step, and prevent the increase of the electric resistance.

In the embodiment shown in FIG. 4, since the pattern is not changed, the layout of the circuit pattern is not restricted, and more particularly in the case of a semiconductor device in which higher integration is more strictly required. The effect of can be expected.

[0038]

As described above in detail, the first aspect of the present invention is provided.
According to the configuration, the widened portion can be provided at the location where the local film thickness of the wiring pattern having a fine dimension is reduced, in accordance with the degree of the reduction and the circuit pattern layout in the vicinity thereof. Therefore, the increase in wiring resistance due to the surface step can be solved relatively easily.

According to the second aspect of the present invention, the shape of the wiring pattern on the lower layer side is deformed as necessary to equalize the pattern intervals, thereby reducing the surface step, and therefore the material of the wiring pattern. Unlike the case where the surface step is reduced by changing the film forming conditions, changing the film forming conditions, or changing the film thickness or film quality of the interlayer film, the process can be performed without changing the manufacturing process.

Further, according to the structure of claim 3, the problem of the surface step can be avoided without adding any restriction to the layout of the circuit pattern only by adding two steps.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a pattern structure in a semiconductor device according to the present invention.

FIG. 2 is a plan view showing another embodiment of the same pattern structure.

FIG. 3 is a plan view showing another embodiment of the same pattern structure.

FIG. 4 is a plan view and a cross-sectional view showing still another embodiment of the same pattern structure.

5A and 5B are a plan view and a cross-sectional view showing an example of a pattern structure in a conventional semiconductor device.

[Explanation of symbols]

1 first interlayer film 2 ₁ to 2 ₃ the first wiring pattern 3 and the second interlayer film 4 _1, 4 ₂ second wiring patterns 5a, 5a ', 5a''wide section 5b, 5b', 5b '' widened portion 6a, 6c, 6e Widened part 6b, 6d Deformed part 7a, 7b Low resistance material

Claims (3)

[Claims] 1. A pattern structure in a semiconductor device, which has a plurality of wiring patterns formed in layers vertically with an interlayer film sandwiched therebetween, and these wiring patterns intersect in a plan view. 2. A wiring pattern structure in a semiconductor device, wherein a widened portion is formed in at least one of the wiring patterns formed in the above so as to correspond to the intersecting portion. 2. In a pattern structure in a semiconductor device, which has a plurality of wiring patterns formed in a layered manner with an interlayer film interposed therebetween and these wiring patterns intersect in a plan view, A wiring pattern structure in a semiconductor device, characterized in that a deforming portion for equalizing the intervals between the wiring patterns is formed on the lower layer side of the wiring pattern formed in (1) to correspond to the intersecting portions. 3. A pattern structure in a semiconductor device, which has a plurality of wiring patterns formed in layers vertically with an interlayer film sandwiched therebetween, and these wiring patterns intersect in a plan view. A wiring pattern structure in a semiconductor device, wherein a low resistance material is filled in a thin portion generated at the intersecting portion on an upper layer side of the wiring pattern formed in.