JPH05326664A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide a compound semiconductor having a CV pattern in which the junction capacitance of a Schottky electrode of an actual MES-FET to be manufactured on a board can be accurately measured and an ohmic electrode is not required in the case of measurement and manufacturing steps can be reduced. CONSTITUTION:Schottky electrodes 3, 4 are formed in a pectinated shape in equal length to that of a gate electrode 6 of a MES-FET 11 and in width twice as wide as a width of the electrode 5 on an active layer 2 formed on a semi- insulating GaAs board 1, and a bias is applied between the electrodes 3 and 4 to measure the junction capacitance of either the Schottky electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high speed compound semiconductor device used in communication equipment and information processing equipment, and more particularly to a metal-semiconductor contact field effect transistor (hereinafter referred to as "MES") using gallium arsenide (GaAs) as a substrate. -FET "
(Hereinafter referred to as)) for a compound semiconductor device suitable for measuring CV characteristics.

[0002]

2. Description of the Related Art FIG. 5 is a view showing a sectional structure of a so-called CV pattern formed for measuring CV characteristics in a conventional compound semiconductor device. As shown, CV
The pattern portion 20 is in direct contact with the active layer 22 on the GaAs substrate 21 and the active layer 22 and the n ⁺ layer 25 formed by selectively implanting silicon ions or the like into the semi-insulating GaAs substrate 21, for example. A Schottky electrode 23 formed of a refractory metal such as tungsten silicide (WSi);
The ohmic electrode 26 is made of AuGe or the like and is in contact with the ⁺ layer 25. On the surface of the GaAs substrate 21 other than the CV pattern portion 20, the same active layer 22, n ⁻ layer 24, and n ⁺ layer as those described above are formed.
Layer 25, Schottky electrode 23, ohmic electrode 26
The MES-FET 30 is formed by the gate electrode 27 having a length of 1 μm and formed at the same time.

[0003]

In the CV pattern formed to measure the CV characteristic, the Schottky electrode 23
In order to accurately measure the junction capacitance of the active layer 22 immediately below,
An area of at least about 1 × 10 ^-4 cm ² is required.
However, the conventional CV pattern portion 20 described above has 100
An ME that is actually used as a device and is formed in a square with a square of 200 μm and a rectangle of 200 μm and 100 μm.
It is significantly different from the shape of the fine Schottky gate electrode of the S-FET.

The MES-FET, which is an actual device, has a junction capacitance of several hundreds of hemtofarads at most if the gate length is 1.0 μm and the channel width is 50 μm. I can't. Therefore, the capacitance is evaluated on the order of several tens of pico-orders by enlarging each side of the CV pattern to increase the area as described above. Therefore, there is a problem in that it may not be possible to reproduce the effect peculiar to the fine pattern, such as the fluctuation of the carrier concentration distribution of the active layer 22 (the so-called edge effect) due to the distortion of the pattern edge portion generated during the heat treatment after the implantation. It was

Further, since the conventional CV pattern portion 20 is formed by forming a diode element composed of a pair of electrodes of the Schottky electrode 23 and the ohmic electrode 26,
At least two steps, that is, the step of forming the Schottky electrode 23 and the step of forming the ohmic electrode 26 were required, and measurement could only be performed after the ohmic electrode 26 was formed.

Therefore, an object of the present invention is to accurately measure the junction capacitance of a Schottky electrode of an actual MES-FET manufactured on a substrate, and the ohmic electrode is not required for the measurement, and the manufacturing process is also possible. Less C
An object of the present invention is to provide a compound semiconductor having a V pattern. Further, by configuring the element for measuring the CV characteristic as a diode type, the C between Schottky and Schottky is
C in a Schottky forward bias condition that cannot be evaluated by V
Another object is to provide a compound semiconductor capable of measuring V characteristics.

[0007]

According to a first aspect of the present invention, there is provided a compound semiconductor device comprising: an active layer of the same type as that of a compound semiconductor substrate on which a Schottky gate field effect transistor or the like is formed. Two or more Schottky electrodes are formed, and at least one of the Schottky electrodes is formed with a width that is twice or less the width of the gate electrode in the Schottky gate field effect transistor.

According to another aspect of the compound semiconductor device of the present invention, the Schottky electrode and the ohmic electrode are formed on the same active layer as the active layer of the compound semiconductor substrate on which the Schottky gate field effect transistor and the like are formed, and the Schottky electrode and the ohmic electrode are formed. The key electrode is formed to have a width not more than twice the width of the gate electrode in the Schottky gate field effect transistor.

[0009]

According to the structure of claim 1, at least one of the Schottky electrodes is formed with a width not more than twice the width of the gate electrode in the Schottky gate field effect transistor. Since the effect of is applied to half of the joint surface, it is possible to accurately measure the joint capacitance. If a voltage is applied between the two Schottky electrodes and the junction capacitance of one of the electrodes is measured, either one of the electrodes becomes forward biased, and CV measurement can be performed without the need for an ohmic electrode.

According to the structure of claim 2, it is possible to obtain the capacitance under the Schottky electrode in the forward bias state of the diode, which cannot be evaluated by the Schottky / Schottky type element according to the structure of claim 1, and the Schottky gate can be obtained. It is possible to evaluate the characteristics of the field-effect transistor faithfully and measure the junction capacitance.

[0011]

FIG. 1 is a diagram showing a manufacturing process of a compound semiconductor according to an embodiment of the present invention. First, semi-insulating GaAs.
For example, Si ions are selectively implanted into the substrate 1 by an ion implantation method at an acceleration voltage of 40 keV and a concentration of 5 × 10 ¹² cm ⁻² to form an active layer 2 (FIG. 3A).

Next, a refractory metal such as WSi is vapor-deposited on the entire surface of the substrate 1 to a thickness of 20000 Å, and then the Schottky electrode 3 and The Schottky electrode 4 has a length of 1 μm,
Width 100 μm (channel width 5 of normal MES-FET
20 μm each) to form 20 combs. At the same time, the Schottky electrode 5, which will be the gate of the MES-FET, is also formed (FIG. 7B).

Next, using the Schottky electrode 3 and the Schottky electrode 4 as a mask, 50 keV, 4 × 10 ¹² cm ^-2
Under the above conditions, Si ions are implanted to form the n ⁻ layer 6, and further, selectively under the conditions of 100 keV and 1 × 10 ¹³ cm ^−2.
Ions are implanted to form the n ⁺ layer 7 (FIG. 7C).
Next, an NSG film having a thickness of 600 Å is deposited on the entire surface to form an insulating film 8, and then, for activation of the injection layers of the active layer 2, n ⁻ layer 6 and n ⁺ layer 7, for example, arsine is used. 8 in the atmosphere
Annealing is performed at 20 ° C. for 15 minutes ((d) in the figure).

Next, the insulating film 8 is removed with hydrofluoric acid to complete the CV pattern portion 10 (FIG. 8E). After that, the MES-FET 11 used for the device is completed by forming the ohmic electrode 9 by vapor deposition of metal such as AuGe and sintering.
The compound semiconductor device according to the example has a conventional CV
Rather than increasing the accuracy of the junction capacitance measurement by enlarging each side of the pattern to increase the area, the Schottky electrodes 3 and 4 are shaped to match the actual device as described above, thereby achieving accurate junction. It enables the measurement of capacity. This is because the Schottky electrodes 3 and 4 are MES-FETs.
The width of the gate electrode 5 is equal to or less than twice the width of the gate electrode 5, and it is premised that the edge effect reaches half of the junction surface up to twice the actual pattern.

A voltage is applied between the Schottky electrodes 3 and 4 to measure the junction capacitance of the Schottky electrodes 3 or 4. This is because the CV measurement of the conventional diode structure can be performed under both forward bias and reverse bias DC bias conditions, whereas in the case of a Schottky junction device such as GaAs, the Schottky barrier is as low as 0.7V. Usually, the carrier concentration is evaluated by reverse bias. Therefore, when the capacitance is measured between the Schottky electrodes, one of them is forward biased, so that the CV measurement can be performed without the need for the ohmic electrode.

FIG. 2 is a sectional view showing the structure of a compound semiconductor which is another embodiment of the present invention. The manufacturing method is the same as that of the embodiment of FIG. 1, but the Schottky electrode 4 in FIG. 1 is replaced with the ohmic electrode 12. Also in this embodiment, similar to the embodiment of FIG. 1, it is possible to make a shape conforming to the actual device and perform accurate measurement. Also, in this embodiment, one of the electrodes is the ohmic electrode 12.
By applying a forward bias of about 0.3 V that does not exceed the Schottky barrier to the Schottky electrode 4, it is possible to measure the carrier concentration in a portion closer to the surface.

FIG. 3 (a) is a diagram showing the comparison results of the junction capacitances of the CV pattern in the above-mentioned embodiment, obtained for MES-FETs having different characteristics (those with remarkable edge effect and those without remarkable edge effect). (B) is a graph showing the distribution in the depth direction of the carrier concentration of the n layer calculated and calculated. FIG. 4A shows the result of the junction capacitance of the conventional CV pattern, and FIG. 4B is a graph showing the distribution in the depth direction of the carrier concentration of the n layer calculated and calculated. .. In each figure, the solid line is M with a large edge effect.
In ES-FET, the two-dot chain line is a MES with a small edge effect.
-Indicates a FET.

In these graphs, as shown in FIG. 4, the difference in MES-FET characteristics in the conventional CV pattern does not appear as the difference in CV characteristics or the difference in carrier concentration distribution, but as shown in FIG. It can be seen that in the CV patterns of the above-described examples, the difference appears as a difference in carrier concentration distribution. Moreover, the same carrier concentration distribution as that evaluated by the conventional diode structure is observed when measured with Schottky electrodes. By the way, in the case of the Schottky-Schottky type CV pattern, the junction capacitance can be measured only in the negative gate bias region of 0 V or less with the characteristic shown in FIG. Depletion type MES-
In the FET, since the operation gate bias region is mainly on the negative side, the purpose of carrier concentration evaluation can be sufficiently fulfilled.

[0019]

According to the compound semiconductor device of the present invention, at least one of the Schottky electrodes is formed to have a width not more than twice the width of the gate electrode in the Schottky gate field effect transistor. Accurate measurement of the junction capacitance is possible because the effect of the edge extends to half of the joint surface. In addition, since a voltage is applied between the two Schottky electrodes to measure the junction capacitance of one of the electrodes, either one of the electrodes becomes a forward bias, and the CV measurement can be performed without the need for an ohmic electrode. ..

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a compound semiconductor device which is an embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a compound semiconductor device according to another embodiment.

FIG. 3 is a diagram showing CV characteristics measured according to an example and a carrier concentration distribution thereof.

FIG. 4 is a diagram showing CV characteristics measured by a conventional example and carrier concentration distribution thereof.

FIG. 5 is a sectional view showing a configuration of a conventional compound semiconductor device.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 Active layer 3 Schottky electrode 4 Schottky electrode 5 Schottky electrode 6 n ^- layer 7 n ⁺ layer 8 Insulating film 9 Ohmic electrode 10 CV pattern part 11 MES-FET

Claims (2)

[Claims] 1. Two or more Schottky electrodes are formed on an active layer of the same kind as an active layer of a compound semiconductor substrate on which a Schottky gate field effect transistor or the like is formed, and at least one of the Schottky electrodes is A compound semiconductor device, wherein the compound semiconductor device is formed to have a width not more than twice a gate electrode width in a Schottky gate field effect transistor. 2. A Schottky electrode and an ohmic electrode are formed on the same active layer of a compound semiconductor substrate on which a Schottky gate field effect transistor or the like is formed, and the Schottky electrode is the Schottky gate. The width of the gate electrode in the field effect transistor is 2
A compound semiconductor device having a width not more than double.