JPH05325597A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the inspection time of a memory by selecting plural addresses at a time by an address selection part and then writing the same data in plural memories at a time. CONSTITUTION:A control part 6 controls the address selection part 2 provided between an address buffer part 1 and a column decoder part 3 according to information from a data buffer part 5. Consequently, the selection part 2 selects plural addresses at a time and writes the same data in plural memory cells of a memory part 7 at a time to shorten the time for writing to the memory part, thereby shortening the inspection time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of shortening a memory inspection time.

[0002]

2. Description of the Related Art Conventionally, as a test of a memory device, writing of a checker pattern, a march pattern or the like has been performed in order to test a leak between bits, between word lines or between bit lines.

FIG. 2 is a block diagram of a conventional memory device, which comprises an address buffer unit 1, a column decoder unit 3, a row decoder unit 4, a memory unit 7 and a data buffer unit 5.

The operation of the memory device configured as described above will be described. When performing a write test, an address is input to the address buffer unit 1 and a certain memory cell is selected, as in a known normal write operation.
It is output to the column decoder unit 3. Then, the data input to the column decoder unit 3 is written in the memory cells of the memory unit 7. By repeating this operation for all addresses,
The inspection pattern is written in all the memory cells of the memory unit 7.

[0005]

However, in the above-mentioned conventional device, as the memory capacity increases, the memory section 7 becomes larger.
Write time to all the memory cells is increased, the increase of inspection time becomes a problem, and a method of shortening the inspection time is required.

[0006]

In order to solve the above problems, the present invention provides an address buffer section, an address select section connected to the address buffer section, a decoder section connected to the address select section, A plurality of addresses of the memory, which includes a memory unit connected to the decoder unit, a data buffer unit connected to the memory unit, and a control unit for outputting a control signal to the address select unit according to information from the data buffer. Are collectively selected, and the data is written to the memory section.

[0007]

According to the present invention, with the above configuration, it is possible to collectively write the same data to a plurality of memory cells by selecting a plurality of addresses at a time.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a memory device according to an embodiment of the present invention.

The write control unit 6 receives the input signal T
The write inspection mode is set by S, and the control signal C1 is set by the information D1 of the data input from the data buffer unit 5.
Is output. The address select unit 2 outputs to the column decoder unit 3 so as to collectively select the addresses to which the same data is input by the control signal C1. Then, the same data is written from the data buffer unit 5 to all the memory cells of the memory unit 7 selected by the column decoder unit 3.

FIG. 3 shows a circuit diagram of an embodiment of the address select section 2 shown in FIG.

This embodiment is a circuit for shortening the writing of the checker pattern, all 1 pattern and all 0 pattern.

First, the checker pattern write inspection operation will be described. Checker pattern is 1
And 0s are arranged in a grid, so even columns are 1, 0, 1, 0
, The odd-numbered columns are 0, 1, 0, 1 ...

First, all the even-numbered columns X0, X2, X4 ..., Y0, Y1, Y2 ... Are selected by the control signals S1 and S2, and 1, 0, 1, 0 ...

Next, all odd-numbered columns X1, X3, X5 ..., Y0, Y1, Y2 ... Are selected by the control signals S2 and S3, and 0, 1, 0, 1 ...

The checker pattern is written in all the memory cells by the above-mentioned writing twice.

Second, the all 1 pattern and the all 0 pattern will be described. By the control signals S1, S2 and S3, all addresses X0, X1, X2, ..., Y0,
1 or 0 with Y1, Y2, ... Selected
The same data is written in all the memory cells by writing once by writing the data.

[0017]

According to the present invention, in the inspection of the memory device, by collectively selecting the memory cells in which the same data is written, the time is shortened because the data is written in all the memory parts, and the inspection time can be shortened. Is.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory device according to the present invention.

FIG. 2 is a block diagram of a memory device according to the related art.

FIG. 3 is a circuit diagram showing an embodiment of an address select unit of the present invention.

[Explanation of symbols]

 1 address buffer unit 2 address select unit 3 column decoder unit 4 row decoder unit 5 data buffer unit 6 write control unit 7 memory unit

Claims (1)

[Claims] 1. An address buffer section, an address select section connected to the address buffer section, a decoder section connected to the address select section, a memory section connected to the decoder section, and a memory section. And a control unit for outputting a control signal to the address select unit according to information from the data buffer, selecting a plurality of addresses of the memory at a time and writing the data to the memory unit. Memory device characterized by.