JPH04372799A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the increase of the test time of a memory cell information holding time, and to sharply shorten the test time, even when a memory capacity or the number of word lines are increased. CONSTITUTION:This device is equipped with a test mode entry circuit 7 which generates a control signal MS which is turned to an active level when a voltage beyond the normal voltage range of address signals A0-An is impressed on an address input terminal which inputs the specific bit An of address signals A0-An. And also, this device is equipped with a multi-selector 8 which simultaneously turns every plural word lines WLj to a selective level when the control signal MS is the active level.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, it relates to a dynamic semiconductor memory device.

0002

2. Description of the Related Art A conventional semiconductor memory device of this type will be explained with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory device.

This semiconductor memory device includes a plurality of word lines WLj for selecting a plurality of memory cells (MC11 to MC53) arranged in the row and column directions in predetermined units in the row direction;
A plurality of bit lines BLi that connect to predetermined units of memory cells in the column direction and transmit data to these memory cells.
a memory cell array 1 that writes and reads data to and from memory cells selected by word lines WLj and bit lines BLi; and a memory cell array 1 that inputs address signals A0 to An and outputs internal address signals X0 to Xm, Y0 to Yk, and an address input circuit 2 that outputs an inverted signal, a row decoder 3 that sets one of the plurality of word lines WLj to a selection level using internal address signals X0 to Xm and their inverted signals, and a row decoder 3 that outputs data on a bit line BLi. Sense amplification circuit 6 for amplification
, a column decoder 4 and a Y selector 5 that select predetermined data DT from and to the sense amplifier circuit 6 based on internal address signals Y0 to Yk and their inverted signals.

Next, a method for testing the memory cell information retention time of this semiconductor memory device will be explained.

Each memory cell MC on memory cell array 1
11 to MC53, as shown in FIG. 4, high level (H) and low level (L) are set to have opposite information to the memory cells of adjacent word lines, and to have the same information for the same word line. Then, one word line WL1 is selected and the information of the memory cells MC11 to MC13 connected to this word line WL1 is read out to the bit lines BL1, BL3, and BL5, amplified by sense amplifiers SA1, SA2, and SA3, and read out. The same information is rewritten into the memory cells that were previously written. Test whether the information of adjacent memory cells is retained even if the operation of selecting a word line and writing information to the memory cell again is repeated for a time approximately equal to the standard for memory cell information retention time. do. Since this operation is performed for all memory cells in the memory cell array 1, the time required for testing is approximately (memory cell information retention time) x (number of word lines), which is extremely long.

[0007]

[Problems to be Solved by the Invention] In the above-described conventional semiconductor memory device, when testing the memory cell information retention time, a time approximately equal to the memory cell information retention time is spent on all word lines WLj of the memory cell array 1. Since the configuration is such that the test is carried out in a single manner, the test time becomes long, and this test time increases as the number of memory capacity word lines increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which the test time does not increase even if the memory capacity increases and the test time can be shortened.

[0009]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of memory cells arranged in row and column directions, and a plurality of memory cells that select these memory cells in a predetermined unit in the row direction when at a selection level. a memory cell array comprising a word line and a plurality of bit lines transmitting data to a predetermined unit of memory cells in a column direction, and writing and reading data to and from memory cells selected by the word line and bit line; In a semiconductor memory device having a decoding circuit that sets a predetermined one of the plurality of word lines to a selected level by an address signal, a normal voltage range of the address signal is input to a specific address input terminal to which the address signal is input. a test mode entry circuit that generates a control signal that becomes active when a voltage exceeding the voltage is applied;
A multi-select circuit is provided to set a predetermined plurality of word lines to a selection level when the control signal is at an active level.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. The control signal MS becomes active level when a high voltage exceeding the normal voltage range of the control signal MS is applied.
A multi-selector 8 is provided between the address input circuit 2 and the row decoder 3 to select a predetermined plurality of word lines at a time when the control signal MS is at an active level. At the point.

In this embodiment, in the test mode, the same word line WL of the memory cell array 1 is
The multi-selector 8 writes the same data to the memory cells connected to the same bit line, and writes different data to the memory cells connected to the adjacent word line. The circuit sets the word line to the selection level to select the word line.

FIG. 2 shows a specific circuit example of the multi-selector 8 in the case of the data arrangement shown in FIG. 4.

In the case of the data arrangement as shown in FIG.
Since one pattern of data arrangement is repeated for every four word lines, it is necessary to set the selection level to one word line for every four word lines. Therefore, the multi-selector 8 selects the lower two of the address signals A0 to Ak as shown in FIG.
The circuit is configured such that the bit is enabled to select one of the four wires, and the other upper bits are all set to the active level when the control signal MS is at the active level, and all of each set of four wires are selected. That is, word line WL1 and word line WL1 simultaneously
5 becomes the selection level at the same time. Generally, the word line W
At the same time as L(a), (a=1, 2, 3, 4), word lines WL(a+4b), (b is a positive integer, and a+4b is less than or equal to the number of word lines) become the selection level at the same time.

With this configuration, the memory cell information retention time can be tested for all memory cells by simply changing the lower two bits of the address signals A0 to An four times. That is, the test time can be significantly reduced regardless of the memory capacity or the number of word lines.

[0017]

Effects of the Invention As explained above, the present invention has the advantage that when a voltage exceeding the normal voltage range of an address signal is applied to an address input terminal that inputs a specific bit of an address signal, a predetermined plurality of word lines are By adopting a configuration that includes a multi-selector that simultaneously selects each word line, the test time does not increase even if the memory capacity or the number of word lines increases, and the test time can be significantly shortened. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a multi-selector portion of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory device.

4 is a circuit diagram including an example of data arrangement of a memory cell array for explaining a test method for the semiconductor memory device shown in FIG. 3; FIG.

[Explanation of symbols]

1 Memory cell array 2 Address input circuit 3 Row decoder 4 Column decoder 5 Y selector 6 Sense amplifier circuit 7 Test mode entry circuit 8 Multi selector G1~Gn Logic gate IV0~IVm Inverter

Claims (2)

[Claims] 1. A plurality of memory cells arranged in the row and column directions, a plurality of word lines that select these memory cells in a predetermined unit in the row direction when at a selection level, and a memory in a predetermined unit in the column direction. A memory cell array includes a plurality of bit lines for transmitting data to the cells, and writes and reads data to and from memory cells selected by the word lines and bit lines; In a semiconductor memory device having a decoding circuit that sets a signal to a selected level, control becomes an active level when a voltage exceeding a normal voltage range of the address signal is applied to a specific address input terminal to which the address signal is input. A semiconductor memory device comprising: a test mode entry circuit that generates a signal; and a multi-select circuit that sets a predetermined plurality of word lines to a selection level when the control signal is at an active level. 2. In a test mode, the same data is written to the memory cells connected to the same word line of the memory cell array, and different data is written to the memory cells connected to the adjacent word line, and the multi-select circuit of,
2. The semiconductor memory device according to claim 1, further comprising a circuit that sets said word line to a selection level so as to select memory cells of the same data connected to the same bit line.