JPH05325550A - Substrate voltage generating circuit for mos dynamic ram - Google Patents

Abstract

PURPOSE:To improve the driveability of a substrate voltage by providing a transistor(TR) which controls a capacitor for substrate potential extraction and has its gate voltage controlled with a source voltage and the substrate voltage. CONSTITUTION:An input signal OSC is supplied to the gates of an MOSFET 4a and an MOSFET 5 and the level of the next stage is as high as the source voltage Vcc or substrate voltage. This level is received at the gate of an MOSFET 4b and an MOSFET 7 and at the time of electric charging, an MOSFET 6 is turned ON with the Vcc. At the time of electric discharging, on the other hand, the FET 6 is turned OFF with the substrate voltage and an MOSFET 3 is turned ON to apply a potential to GND. Thus, the source voltage Vcc and substrate voltage are utilized for the FET 6 which controls the capacitor 2 for substrate voltage extraction, so the driveability is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate voltage generating circuit for a MOS dynamic RAM.

[0002]

2. Description of the Related Art The structure of a conventional substrate voltage generating circuit for a MOS dynamic RAM will be described with reference to FIG. FIG. 3 is a circuit diagram showing a substrate voltage generation circuit of a conventional MOS dynamic RAM.

In FIG. 3, 2 is a capacitor, 3 and 6
Is an N-channel MOS transistor.

Next, the operation of the substrate voltage generating circuit of the conventional MOS dynamic RAM described above will be described. By alternately swinging the input signal OSC at Vcc and GND levels, the capacitor 2 is charged and discharged. When being charged, the N-channel MOS transistor 6 turns on,
The N-channel type MOS transistor 3 is turned off to pull out the potential from the substrate. When discharging, N-channel type MOS
The transistor 6 is turned off and the N-channel type MOS transistor 3 is turned on to pass a potential to GND. By repeating the above operation, the substrate potential is raised negatively.

[0005]

In the conventional MOS dynamic RAM substrate voltage generating circuit as described above, the N-channel MOS transistor 6 is turned on at the time of charging.
Is controlled by the substrate voltage, and in the case of a P-channel type MOS transistor, it is controlled by the potential on the capacitor side.
There is a problem that the driving capability is low because the level becomes lower than th (threshold value).

The present invention has been made in order to solve the above-mentioned problems, and a MOS capable of realizing a substrate voltage = -Vcc as well as improving the substrate voltage driving capability.
The object is to obtain a substrate voltage generation circuit for a dynamic RAM.

[0007]

A substrate voltage generating circuit for a MOS dynamic RAM according to the present invention comprises the following means. [1] A transistor which controls a substrate potential extracting capacitor and whose gate voltage is controlled by a power supply voltage and a substrate voltage.

[0008]

In the present invention, the substrate potential extracting capacitor is controlled by the transistor whose gate voltage is controlled by the power supply voltage and the substrate voltage.

[0009]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIG. 1 is a circuit diagram showing a first embodiment of the present invention, in which a capacitor 2, N-channel type MOS transistors 3 and 6 are the same as those of the conventional circuit described above.
In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 1 is an inverter, 4a and 4b are P channel type MOS transistors, 5 is an N channel type MOS transistor having a high threshold value, and 7 is a normal N type.
It is a channel type transistor.

Further, the P-channel type MOS transistor 4
The level formed by b and the N channel type MOS transistor 7 enters the gate of the N channel type MOS transistor 6, and the substrate voltage is connected to the drain side of the N channel type MOS transistors 5 and 7.

Next, the operation of the above-described first embodiment will be described. The input signal OSC is alternately swung at the Vcc and GND levels. The signal is inverted by the inverter 1 and received and charged / discharged in the capacitor 2.

During charging, the N-channel type MOS transistor 6 is turned on and the N-channel type MOS transistor 3 is turned on.
Is off.

On the other hand, the input signal OSC is a P channel type MO.
It is connected to the gates of the S-transistor 4a and the N-channel type MOS transistor 5, and the level of the next stage is the power supply voltage Vcc or the substrate voltage. This is received by the gates of the P-channel type MOS transistor 4b and the N-channel type MOS transistor 7, and the N-channel type MOS transistor 6 is turned on at Vcc during charging.

Similarly, at the time of discharging, the N-channel MOS transistor 6 is turned off by the substrate voltage, the N-channel MOS transistor 3 is turned on, and a potential is supplied to the GND.

The first embodiment of the present invention, as described above,
Since the power supply voltage (Vcc) and the substrate voltage are used for the N-channel MOS transistor 6 that controls the substrate voltage extracting capacitor 2, the N-channel MOS transistor 6 is turned on by the power supply voltage Vcc, and the threshold of the transistor is reached. There is an effect that the electric potential can be extracted from the substrate without lowering the value voltage and the drive capability can be increased.

Embodiment 2. Embodiment 2 of the present invention will be described with reference to FIG. 2 is a circuit diagram showing a second embodiment of the present invention, in which the inverters 1 to N-channel type MOS transistor 3 and N-channel type MOS transistor 6 are the same as those in the above-described first embodiment. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 2, 8a and 8b are P-channel type MOS transistors, the gate of which is connected to the first stage transistor 8a of the input signal OSC and the second stage of transistor 8b which is the inverted signal of the input signal OSC. ..

The sources of the N-channel MOS transistors 9a and 9b enter each other and are connected to the P-channel MOS transistors 8b and 8a. In addition, 10 is an inverter.

In the first embodiment described above, the control of the N-channel type MOS transistor 6 by the two stages of the inverter has been described. It controls the MOS transistor 6.

[0021]

As described above, according to the present invention, since the transistor for controlling the substrate potential extracting capacitor is provided and the gate voltage is controlled by the power supply voltage and the substrate voltage, the driving capability of the substrate voltage is improved and There is an effect that the substrate voltage = −Vcc can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a substrate voltage generation circuit of a conventional MOS dynamic RAM.

[Explanation of symbols]

 1 inverter 2 capacitor 3 N channel type MOS transistor 4a, 4b P channel type MOS transistor 5 N channel type MOS transistor 6 N channel type MOS transistor 7 N channel type MOS transistor 8a, 8b P channel type MOS transistor 9a, 9b N channel type MOS transistor 10 inverter

Claims (1)

[Claims] 1. A substrate voltage generation circuit for a MOS dynamic RAM, comprising a transistor for controlling a substrate potential extracting capacitor and having a gate voltage controlled by a power supply voltage and a substrate voltage.