JPH05324119A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor capable of improving a processing speed in the case of selective operation by clocks with the frequency of two kinds or more and capable of reducing power consumption to its minimum. CONSTITUTION:Either one of clocks CK1, CK2 is selected by an external switch 1 and the switched information is latched by a latch 2 and applied to a clock switch 3 and a TW control part 60 for controlling a period TW to be added for surely transferring data as a clock switching signal 5. Values for the period TW corresponding to the clocks CK1, CK2 are previously set in the TW control part 60 and a TW control forming part 61 in the TW control part 60 selects the period TW based upon an operation clock 4 and the clock switching signal 5 and outputs a ready signal based upon the period TW to a CPU 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a Japanese word processor or a personal computer that selectively operates with clocks of two or more kinds of frequencies, and more particularly to internal timing control of data transfer when switching clocks. ..

[0002]

2. Description of the Related Art Generally, an information processing device such as a Japanese word processor (word processor) or personal computer (personal computer) is a CPU (central processing unit) for processing data.
As a storage unit, a rewritable RAM (random access memory) or a read-only ROM (read only memory) is provided. Further, when an FDD (floppy disk drive device) or an HDD (hard disk drive device) is provided as an external storage device, a printer is provided as a recording device, and an RS232C interface or the like is provided as a communication means, a data input / output control unit is provided. Has an IO (input / output) control unit.

Data is exchanged between these microcomputers, the memory and the IO control unit by the response of the memory or IO control unit designated by the microcomputer via the data bus, the address bus and the control bus. The operation is performed based on the system clock that determines the operations of the microcomputer, the memory, and the IO control unit.

FIG. 13 shows, as an example, a timing chart of a memory read cycle in which a microcomputer fetches data from a memory in a V series microcomputer manufactured by NEC Corporation. In the clock period T1 which is the start of this read cycle, an address required for reading is set on the address bus from the microcomputer, and a signal for defining the bus state is set on the bus control bus.

Then, in the next period T2, when the read timing of the memory is in time, the ready OK is notified to the microcomputer, and in the next period T3, the microcomputer takes in the data. On the other hand, when the read timing of the memory is not in time in the period T2, the ready NG is notified to the microcomputer, and the period TW is added between the periods T3 and T4 until the ready OK is notified. The control signal is held in a constant state to ensure the data exchange with the memory and the IO control unit.
The same applies to memory write cycles, IO read cycles, and IO write cycles.

Here, the number of times of the period TW is determined in advance based on the time required to access the device of the memory and the IO control unit, and also depends on the frequency of the operation clock. In addition, there is known a system that selectively operates with operating clocks of two or more types of frequencies for the purpose of power saving and lowering of the operating power supply voltage. In such a system, the number of times of the period TW is increased. Is
It is set to a fixed value based on the maximum frequency of the operating clock.

[0007]

However, in the above-mentioned conventional information processing apparatus, the number of the period TW added to ensure the data exchange is set to a fixed value based on the maximum frequency. There is a problem that the processing time cannot be shortened when switching to the operation clock of the lower frequency.

When the standard operation clock frequency is set lower than the maximum frequency in advance and the operation block frequency is switched to this maximum frequency, the number of periods TW is also set to a fixed value based on the maximum frequency. Therefore, when the standard operation clock frequency is selected, the unnecessary period TW is generated, so that there is a problem that the processing speed in the standard time is reduced by the unnecessary period TW. Further, when the purpose of lowering the clock frequency is to reduce the power consumption, the memory and the I and
Since it takes a long time to access the O control unit, there is a problem that the power consumption cannot be reduced to the maximum.

In view of the above-mentioned conventional problems, the present invention can improve the processing speed and selectively reduce the power consumption when operating selectively with clocks of two or more types of frequencies. An object of the present invention is to provide an information processing device that can be used.

[0010]

In order to achieve the above object, the present invention has at least an information processing section, a storage section, and an input / output control section, and the information processing section, the storage section, and the input section. In an information processing device that transfers data to and from an output control unit based on one of operating clocks of two or more types of frequencies, a clock switching unit that switches the operating clock, and the operating clock is switched by the clock switching unit. In this case, the control means variably controls the number of clocks required at the start of data transfer.

[0011]

According to the present invention, the number of clocks required at the start of data transfer changes when the operating clocks of different frequencies are switched, so that the processing time is shortened when the operating clock of the lower frequency is switched. In addition, the power consumption can be reduced to the maximum.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a schematic configuration of an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a flowchart for explaining a processing sequence in the information processing apparatus shown in FIG.

In this embodiment, as an example, the clocks CK1 and CK2 having two kinds of frequencies are selectively operated, and the clocks CK1 and CK2 are selected by an external switch (SW) 1 for switching the operation clocks. To be done. The switching information of the external SW1 is latched by the system reset signal by the latch 2 so that the operation clock 4 is set before the system is started, and the data is reliably exchanged with the clock switch 3 as the clock switching signal 5. Is applied to the TW control unit 6 that controls the period TW that is added in order to operate. The clock switch 3 outputs the operation clock 4 selected from the clocks CK1 and CK2 by the clock switching signal 5 to the CPU 10 and the TW control unit 6.

The TW control unit 6 has clocks CK1,
Data of the period TW required at the start of data transfer is set according to CK2, and the TW control creation unit 6a of the TW control unit 6 is set.
Selects the period TW based on the operation clock 4 and the clock switching signal 5, and outputs a ready signal based on the period TW to the CPU 10.

An address bus 41, a data bus 42,
The bus control bus 43 includes the CPU 10, the TW control unit 6,
The memory 20 and the IO control unit 30 are connected. The memory 20 is, for example, a memory controller 21, a dynamic RAM (DRAM) 22, and a static RAM (S).
RAM) 23 and ROM 24, and the memory control unit 2
1 is connected to the bus control bus 43, and the DRAM 22 and S
The RAM 23 and the ROM 24 are connected to the address bus 41 and the data bus 42. The memory control unit 21 determines the address and RAS based on the control signal on the bus control bus 9.
The reading and writing of the DRAM 22 is controlled by the (row address strobe) signal and the CAS (column address strobe) signal, and the SRAM 23 and the ROM 24 are also controlled.
The reading and writing of is controlled by each control signal. I
The O control unit 30 performs control for inputting / outputting data to / from a device such as a printer or FDD or HDD.

In FIG. 2, a clock CK is generated by the external SW1.
The operation when 1 and CK2 are switched is shown. First, if the system is not in operation, is not in the reset release state, or is not powered on (step S1), the system is started, reset is released, or power is turned on (step S2), respectively. The operation clock 4 is determined, and the period TW is set by the TW control unit 6 (step S4). On the other hand, when the system is in operation, in the reset released state, and when the power is on (step S1), the operation clock 4 is determined after being reset (step S3), and the TW control unit 6 Thus, the period TW is set (step S4).

When the reset is released and the system is activated (step S5), the TW control creation unit 6a of the TW control unit 6 causes the TW control creation unit 6a of the memory 21 and the IO control unit 30 designated on the control bus 43. A ready signal is sent to the CPU 11 based on the access state, and the CPU 10 causes the memory 20 and the IO control unit 3 to operate based on the number of times of the period TW.
Access 0. If the system is not reset in step S3, the clock CK
1 and CK2 cannot be switched (step S7).

Therefore, according to the above embodiment, the number of times of the period TW can be switched according to the frequency of the operating clock, so that the processing time can be shortened when switching to the operating clock of the lower frequency, and , The power consumption can be reduced to the maximum.

FIG. 3 is a block diagram showing a schematic configuration of the second embodiment, and FIG. 4 is a flow chart for explaining a processing sequence in the second embodiment. In the first embodiment, the clocks CK1 and CK2 are switched by the hardware (TW control unit 6), but in the second embodiment, the operation clock C is used when the device stops operating.
It is configured such that K1 and CK2 are switched by the software of the CPU 10 to start the operation.

That is, in FIG. 3 and FIG. 4, after starting the system shown in steps S11 to S15 and before starting each processing of the system shown in step S18, the CPU
11 reads the state of the operation clock 4 (step S1
6) Write the data for setting the period TW corresponding to this state in the TW control register 62 of the TW control unit 60 (step S17). In this case, the value of the TW control register 62 at the time of system reset is not determined immediately after the period TW corresponding to the operation clock 4 is supplied, so that the system malfunction is prevented in order to prevent system malfunction. It is set to the maximum value that can be considered.

The operations shown in steps S11 to S13 and S19 are the same as the operations shown in steps S1 to S3 and S7 in FIG. 2, and therefore, if the system is not reset in step S13, the clock CK1,
CK2 cannot be switched (step S19). The operations shown in step S18 and step S6 in FIG. 2 are the same.

FIG. 5 is a block diagram showing a schematic configuration of the third embodiment, FIG. 6 is a flow chart for explaining a processing sequence in the third embodiment, and FIG. 7 is a switch change detecting unit of FIG. 8 is a block diagram showing a detailed configuration of the clock switching device of FIG. 5, FIG. 8 is a block diagram showing a detailed configuration of the clock switching device of FIG. 5, and FIG. 9 is a timing chart showing main signals in the clock switching device of FIG. In the third embodiment, as in the second embodiment, when the device is not operating, the operation clocks CK1 and CK2 are switched by the software of the CPU 10 to start the operation, and the device is in operation. In the case, the operation clock is CK1 and CK2 is CP
It is configured to be switched by the software of U10.

That is, steps S11 to S11 in FIG.
The operation shown in 18 is the same as that of the second embodiment. Then, when the system is not reset in step S13, the logical sum signal (OR gate 9) of the control signal 7 of the clock switching signal 5 and the reset signal from the IO control unit 30 in the system is applied as the gate signal of the latch 2. By doing so, the switching information of the external SW1 is similarly latched when the control signal 7 is generated.

Then, the switch switching detector 8 as shown in detail in FIG. 7 is reset by the control signal 7, the switch switching detector 8 detects the switching information of the external SW 1 and interrupts the CPU 10 (step S20). , C
The PU 10 first sets data for which the period TW is maximum in the TW control register 62 by this interrupt (step S21). Then, the switching signal of the external SW1 is latched by the control signal 7 of the clock switching signal 5 from the IO control unit 30 and the operation clock 4 is selected (step S22). Here, the control signal 7 must be in a logical state that becomes valid only when the clock switching signal 5 is taken in. For example, when it is valid at a high level, it is switched to a low level immediately after issuing a high level.

Then, as in steps S16 and S17, the CPU 10 reads the state of the operation clock 4 (step S23), and sets the data for setting the period TW corresponding to this state in the TW control section 60. The register 62 is written (step S24), the interrupt process is terminated, and the process returns to the normal process (step S25).

Here, the switch change detection unit 8 is shown in FIG.
As shown in FIG. 4, the external switch 1 can be constituted by an RC circuit for preventing chattering, a D latch, and a simple logic circuit such as an SR flip-flop. In this embodiment, the clocks CK1 and CK2 are in operation. However, there is a possibility that hazards may occur due to superposition when switching. Therefore, in the clock switch 3a of this embodiment, as shown in FIGS.
As shown in FIG.
The clock switching signal 5 is latched at the falling edge of (K0), and the Q output Q1 of the D latch 31 is provided on the clock CK1 side.
, The output Q2 of the D latches 32 and 33, and the E-OR gate 34 generate a gate signal (/ E1) (note that “/” means an inverted signal for convenience), and the gate signal (/ E1) is generated. / E1) and the AND gate 35 cut off the clock CK1 at the time of switching.

On the clock CK2 side, the D latch 31
(/ Q) output (/ Q1), the output Q3 of the D latches 36 and 37, and the E-OR gate 38.
E2) is generated, and the gate signal (/ E2) and the AND gate 39 block the clock CK2 at the time of switching. Therefore, as shown in FIG.
The outputs A1 and A2 of Nos. 5 and 39 do not overlap at the time of switching, and a hazard can be prevented.

Next, a fourth embodiment will be described. Figure 10
11 is a block diagram showing a schematic configuration of the fourth embodiment, FIG.
9 is a flowchart for explaining a processing sequence in the fourth embodiment. In addition to the function of the third embodiment, the fourth embodiment is configured to switch the operation clock by an internal operation when it is necessary to switch the operation clock depending on the processing content.

That is, in the circuit configuration shown in FIG. 10, in comparison with the third embodiment shown in FIG. 6, in the clock switching signal selection unit 14, the clock priority signal 12 from the IO control unit 30 causes the clock generated by the external switch 1 to operate. CPU (microcomputer) from switching signal 13 or IO control unit 30
The clock switching signal 11 of 10 is selected, and the selected clock switching signal 5 is applied to the clock switch 3a as a selection signal.

Further, in FIG. 11, steps S11 to S
The operation shown in 25 is the same as that of the third embodiment shown in FIG. 7, and the processing shown in steps S31 to S39 is step S1.
It is added as a process during operation shown in FIG. That is, in step S31, it is determined whether or not the operation clock 4 is switched based on the software during operation, and when it is switched, the process proceeds to step S32 and thereafter.

First, the CPU 11 writes data that maximizes the period TW into the TW control register 62 (step S32), sets the clock switching signal 11 (step S33), and then gives priority to the clock switching signal 11 to the clock priority signal. Set the signal 12 (step S3
3). Then, the state of the operation clock 4 is read, and the data for setting the period TW corresponding to this state is TW.
The data is written in the TW control register 62 of the control unit 60 (step S35), and normal processing is performed based on this new operation clock 4 (step S36).

Then, it is judged whether or not the clock switching signal 13 by the external switch 1 is prioritized based on the software under normal processing (step 37), and when the clock switching signal 13 is prioritized, the period TW is maximized. Data to be written in the TW control register 62 (step S3
8) Set the clock switching signal 13 (step S
39). Then, returning to step S16, the state of the operation clock 4 is read, and the data for setting the period TW corresponding to this state is written in the TW control register 62 of the TW control unit 60 (step S18). The normal processing is performed based on (step S3
6).

That is, in the fourth embodiment, the CPU
After outputting the clock switching signal 11, the signal 11 gives priority to the signal 11 by issuing the clock priority signal 12 that gives priority to the signal 11. The signals 11, 1
The issuing timing of 2 may be reversed, but the switching operation of the clock 4 may occur twice, so the order shown in FIG. 11 is preferable.

FIG. 12 shows a modification of the fourth embodiment,
When it is necessary to switch the operation clock depending on the processing content, the operation clock is configured to be switched only by the internal operation, and the configuration for switching by the external switch 1 is eliminated. Although the drawing of this processing sequence is omitted, it can be realized by removing the switching operation by the external switch 11 and the issuing operation of the clock priority signal 12 in FIG.

[0035]

As described above, the present invention has at least an information processing section, a storage section, and an input / output control section,
2 between the information processing unit, the storage unit, and the input / output control unit
In an information processing device that transfers data based on one of operation clocks of frequencies of different types or more, when the operation clock is switched by the clock switching means for switching the operation clock, and when the data transfer is started Since it has a control means for variably controlling the number of clocks required, it is possible to shorten the processing time when the operating clock is switched to the lower frequency, and it is possible to reduce the power consumption to the maximum.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart for explaining a processing sequence in the information processing device shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration of a second embodiment.

FIG. 4 is a flowchart illustrating a processing sequence according to a second embodiment.

FIG. 5 is a block diagram showing a schematic configuration of a third embodiment.

FIG. 6 is a flowchart illustrating a processing sequence according to a third embodiment.

FIG. 7 is a block diagram showing a detailed configuration of a switch change detection unit of FIG.

8 is a block diagram showing a detailed configuration of the clock switch shown in FIG.

9 is a timing chart showing main signals in the clock switch of FIG.

FIG. 10 is a block diagram showing a schematic configuration of a fourth embodiment.

FIG. 11 is a flowchart illustrating a processing sequence according to a fourth embodiment.

FIG. 12 is a block diagram showing a modification of the fourth embodiment.

FIG. 13 is a timing chart for explaining a processing sequence in a conventional information processing device.

[Explanation of symbols]

 1 External Switch 2 Latch 3,3a Clock Switcher 6,60 TW Control Section 8 Switch Switching Detection Section 10 CPU 14 Clock Switching Signal Selection Section 20 Memory 30 IO Control Section

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[Procedure amendment]

[Submission date] February 23, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

[0004] 1 4 an example figure shows a timing chart of the memory read cycle the microcomputer to fetch data from the memory in a V-series microcontrollers of NEC Corporation. In the clock period T1 which is the start of this read cycle, an address required for reading is set on the address bus from the microcomputer, and a signal for defining the bus state is set on the bus control bus.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

Next, a fourth embodiment will be described. Figure 10
11 is a block diagram showing a schematic configuration of the fourth embodiment, FIG.
And FIG. 12 is a flow chart for explaining the processing sequence in the fourth embodiment. In the fourth embodiment, in addition to the functions of the third embodiment, when it is necessary to switch the operation clock depending on the processing content,
It is configured to be switched by an internal operation.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Further, in FIG. 11, steps S11 to S
The operation shown in 25 is the same as that of the third embodiment shown in FIG. 7, and the processing shown in steps S31 to S39 in FIG. 12 is added as the processing during the operation shown in step S18. That is, in step S31, it is determined whether or not the operation clock 4 is switched based on the software during operation, and when it is switched, the process proceeds to step S32 and thereafter.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

[0034] Figure 1 3 shows a modification of the fourth embodiment,
When it is necessary to switch the operation clock depending on the processing content, the operation clock is configured to be switched only by the internal operation, and the configuration for switching by the external switch 1 is eliminated. Although the drawing of this processing sequence is omitted, it can be realized by removing the switching operation by the external switch 11 and the issuing operation of the clock priority signal 12 in FIG.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Brief explanation of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart for explaining a processing sequence in the information processing device shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration of a second embodiment.

FIG. 4 is a flowchart illustrating a processing sequence according to a second embodiment.

FIG. 5 is a block diagram showing a schematic configuration of a third embodiment.

FIG. 6 is a flowchart illustrating a processing sequence according to a third embodiment.

FIG. 7 is a block diagram showing a detailed configuration of a switch change detection unit of FIG.

8 is a block diagram showing a detailed configuration of the clock switch shown in FIG.

9 is a timing chart showing main signals in the clock switch of FIG.

FIG. 10 is a block diagram showing a schematic configuration of a fourth embodiment.

FIG. 11 is a flowchart illustrating a processing sequence according to a fourth embodiment.

FIG. 12 illustrates a processing sequence according to a fourth embodiment .
It is a flowchart for doing.

FIG. 13 is a block diagram showing a modification of the fourth embodiment.

FIG. 14 is a timing chart for explaining a processing sequence in a conventional information processing device.

[Explanation of Codes] 1 External switch 2 Latch 3, 3a Clock switcher 6,60 TW control unit 8 Switch switching detection unit 10 CPU 14 Clock switching signal selection unit 20 Memory 30 IO control unit

Claims (1)

[Claims] 1. An operation clock having at least two types of frequencies between the information processing unit, the storage unit, and the input / output control unit, the operating clock having at least an information processing unit, a storage unit, and an input / output control unit. In a data processing device for transferring data based on one of the above, a clock switching unit for switching the operation clock, and a variable number of clocks required at the start of data transfer when the operation clock is switched by the clock switching unit. An information processing apparatus, comprising: