JPH0531967B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronous circuit, particularly a method for making it possible to synchronize with either a reference signal from inside or outside the synchronous circuit. It concerns circuit improvements.

[Prior Art] Conventional synchronization circuits provided in image display devices, memory devices, etc. are configured as closed-loop automatic control systems for correcting jitter that occurs. FIG. 3 shows such a conventional synchronization circuit. An example of a circuit configuration is shown.

In the figure, 10 is a reference signal transmitter, 11 is a reference oscillator (hereinafter abbreviated as OSC), 12 is a 1/N frequency divider, 14 is a phase detection circuit, 16 is a low pass filter (LPF), and 18 is a voltage controlled oscillator ( 20 is a 1/M frequency divider.

This synchronization circuit is connected to the OSC installed inside the device.
A 1/N frequency divider 12 is connected to OSC11.
The internal reference signal transmitted from the oscilloscope is frequency-divided by 1/N. This frequency-divided reference signal S is supplied to the phase detection circuit 1.
Sent to 4.

On the other hand, the output signal transmitted from the VCO 18 is configured to be frequency-divided by 1/M by a 1/M frequency divider 20 and sent to the phase detection circuit 14.

Next, the operation of synchronizing the signal R, which is transmitted from the VCO 18 and frequency-divided by 1/M, with the reference signal S, which is frequency-divided by 1/N, by this synchronization circuit will be explained with reference to the timing chart in FIG. do.

Figure A shows the clock pulse of the reference signal S from the OSC 11 whose frequency has been divided by 1/N, and Figure B shows the clock pulse of the reference signal S from the VCO 18 whose frequency has been divided by 1/M.
shows the pulse of

The phase difference between the two pulses is detected by the phase detection circuit 14. The phase difference detection result is sent to the LPF 16 as a phase difference detection signal Δθ shown in FIG.

The phase difference detection signal Δθ is turned on at the rising edge of the pulse wave of the reference signal S in A of the same figure, and the signal R of B in the same figure is turned on.
indicates a pulse waveform that turns off at the rising edge of the pulse wave. In other words, the pulse waveform corresponds to the phase difference between the reference signal S and the signal R, and furthermore, the LPF16
The control voltage signal VI is integrated by passing through the control voltage signal VI shown in FIG. This control voltage signal VI is
Feedback is provided to VCO18.

The VCO 18 synchronizes the signal R with the reference signal R by changing the oscillation frequency in accordance with the difference between the voltage value VI and a predetermined reference voltage value. That is, the voltage value VI
Based on the characteristic that the frequency increases in response to a rise in the frequency, a follow-up operation is performed to gradually adjust the frequency and finally achieve synchronization.

[Problems to be Solved by the Invention] However, in the circuit configuration of the conventional synchronous circuit described above, in order to synchronize the signal R with the reference signal S from the internally provided OSC 11, the VCO 18
The oscillation frequency of the reference signal is simply changed in accordance with the change, and no consideration is given to synchronizing with other reference signals.

Therefore, with the diversification of uses of image display devices and the like, there has been a problem that it is not easy to synchronize with other reference signals, such as external reference signals.

The present invention was made to solve these problems, and an object of the present invention is to provide a synchronization circuit that can synchronize not only with an internally generated reference signal but also with an external reference signal.

[Means for Solving the Problems] In order to achieve the above object, the synchronous circuit according to the present invention has a reference signal transmitter that transmits an internal reference signal as a reference signal supply source to the phase detection circuit, as well as a reference signal transmitter that transmits an internal reference signal. An external reference signal input section for inputting a reference signal is provided, and first and second frequency dividing circuits are provided for frequency-dividing an output signal of a voltage controlled oscillator synchronized with the external reference signal input section in accordance with the internal and external reference signals. Furthermore, each signal is switched using a combination of an output signal frequency-divided by the first frequency divider circuit for the internal reference signal, and an output signal frequency-divided by the second frequency divider circuit for the external reference signal. The present invention is characterized in that a select switch is provided to supply the signal to the phase detection circuit, and the frequency dividing circuit is switched simultaneously in response to the switching of the reference signal.

[Operation] With the above configuration, the synchronization circuit according to the present invention can selectively supply the internal reference signal and the external reference signal to the phase detection circuit, and can also supply the output signal of the VCO to be synchronized with the reference signal. The frequency can be divided at different ratios to suit each reference signal.

Therefore, the output signal of the VCO can not only be synchronized with the internal reference signal, but also accurately and easily synchronized with other external reference signals having different frequencies.

[Embodiment] FIG. 1 is a diagram showing the overall configuration of a preferred embodiment of the present invention. Elements similar to those of the conventional synchronous circuit shown in FIG. omitted.

The operation of synchronizing the output signal of the VCO 18 with respect to the reference signal is similar to that of conventional circuits, but what is unique about the present invention is that first, an external reference signal input section is provided as a reference signal supply source. In this embodiment, an input terminal 22 for an external signal ExS of an arbitrary frequency is provided.

In addition to the 1/M frequency divider 20, a 1/L frequency divider 24 is provided as a frequency divider for dividing the output signal of the VCO 18 by a predetermined ratio and supplying the divided signal to the phase detection circuit 14. These frequency dividers are provided to divide the frequency of the output signal of the VCO 18 corresponding to each reference signal to facilitate the detection of the phase difference.The internal reference signal S1 transmitted from the reference signal transmitter 10
The signal output from the VCO 18 is passed through a 1/M frequency divider 20 to the phase detection circuit 14 in order to adapt the signal to the phase detection circuit 14.
A first frequency divider circuit is used to match the external reference signal S2 based on the external signal ExS.
A second frequency dividing circuit is used that sends the signal output from the VCO 18 to the phase detection circuit 14 via the 1/L frequency divider 24.

26 is a select switch and select signal
Switching between internal reference signal S1 and external reference signal S2 supplied to phase detection circuit 14 based on SEL and
Phase detection circuit 1 divides the output signal of VCO18
Switching is performed between the first frequency dividing circuit and the second frequency dividing circuit that supply the signals to 4.

That is, the reference signal selection switch 28 is switched between the output terminal 32 of the internal reference signal transmitter 10 and the external signal input terminal 22, and the frequency division circuit selection switch 30 is switched between the output terminal 34 of the first frequency division circuit and the external signal input terminal 22. and the output terminal 36 of the second frequency divider circuit.

FIG. 2 is a timing chart showing the operation of the present invention. When the select signal SEL is (a), the reference signal S3 supplied to the phase detection circuit 14 is the internal reference signal S1, which is supplied from the VCO 18. shows that the output signal R3 is the output signal R1 divided by 1/M, and when the select signal SEL is (b), the reference signal is switched to the external reference signal S2, and the output signal is divided by 1/L. This shows that the output signal R2 is switched to the output signal R2. The phase difference detection signal Δθ is also a pulse wave corresponding to switching between (a) and (b) of the select signal SEL.

Note that the operation in which the output signals R1 and R2 are synchronized with the reference signal is similar to the conventional operation shown in FIG.

Therefore, according to this embodiment, the internal
Since external switching is possible and switching of the frequency dividing circuit for the output signal to be synchronized is performed simultaneously in response to switching of the reference signal, synchronization with each reference signal can be performed accurately and quickly.

[Effects of the Invention] As explained above, according to the synchronous circuit according to the present invention, by switching the select switch,
It is possible to easily and accurately synchronize a predetermined output signal not only with an internal reference signal but also with an external reference signal having a different frequency, for example, with horizontal and vertical synchronization signals of a video signal in an image display device. Since synchronization with the signal from the image processing section of the personal computer can be easily achieved, it becomes possible to easily realize a superimpose function in which the personal computer video is displayed superimposed on the image.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a preferred embodiment of the present invention;
FIG. 2 is a timing chart showing the operation of the embodiment, FIG. 3 is a configuration diagram of a conventional synchronous circuit, and FIG. 4 is a timing chart showing the operation of the conventional synchronous circuit. 10...Reference signal transmitter, 11...OSC, 1
2, 20, 24... Frequency divider, 14... Phase detection circuit, 16... LPF, 18... VCO, 26... Select switch, 28, 30... Switch.

Claims (1)

[Claims] 1. A reference signal transmitter that transmits an internal reference signal;
a first frequency dividing circuit that divides the output signal from the voltage controlled oscillator by a predetermined ratio; a phase detection circuit that detects a phase difference between the output signal and the internal reference signal; and a phase difference detection signal from the phase detection circuit. In a synchronization circuit that feeds back a control voltage signal obtained by integrating the voltage to the voltage controlled oscillator and synchronizes the output signal with the internal reference signal by changing the frequency, the synchronization circuit includes an external reference signal input section that inputs an external reference signal; , a second frequency divider circuit that frequency divides the output signal at a frequency division ratio corresponding to the external reference signal; a first frequency divider circuit adapted to switch between the internal reference signal and the external reference signal; and a first frequency divider circuit corresponding to this switching; a select switch for selectively supplying each of the reference signals and the frequency-divided output signal corresponding thereto to the phase detection circuit by switching between the frequency divider circuit and the frequency divider circuit; A synchronous circuit characterized in that switching is performed simultaneously in response to switching of a reference signal.