JPH0531772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiple interrupt processing method suitable for use in relatively small-sized information processing devices such as personal computers.

[Technical background of the invention and its problems]

In many information processing devices, such as personal computers, whose control core is a microprocessor, input/output devices are driven by interrupts. It is well known that an interrupt control LSI is provided as a general-purpose peripheral device for processing this interrupt. The 8259A manufactured and sold by Intel Corporation in the United States is famous as this general-purpose peripheral device LSI. This LSI controls 8-level interrupt requests (interrupt lines) and automatically generates a CALL instruction as a vector address based on an interrupt response signal issued from a microprocessor.

On the other hand, personal computers generally allow the user to prepare and install an option board, and for this reason, one interrupt line is often left open.

By the way, when the interrupt input line of the interrupt controller is FULL, as shown in Figure 1, for example, the floppy disk controller (FDC)
It is common practice to share the interrupt line from the user's own option board (OB) with the interrupt line from the user's own option board (OB). By sharing the interrupt line, the option board is provided with a flip-flop for storing the occurrence of an interrupt, and interrupt processing is performed in accordance with the procedure shown in FIG. Details will be described later.

However, by performing this shared interrupt, the following problems occur. In other words, you may not want to accept interrupts from the other while processing one interrupt. For example, if an interrupt is received from an option board while data is being transferred from a floppy disk to main memory, the service for that option board will be interrupted. On the floppy disk side, processing time will be lost, and in some cases, data transferred to the main memory may be missing.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a multiple interrupt processing method that eliminates the above-mentioned drawbacks by selecting on the main routine side whether or not interrupts that occur asynchronously are necessary and performing exclusive processing. purpose.

[Summary of the invention]

The present invention inputs at least two interrupt factors that occur asynchronously for the same interrupt level, and in an interrupt processing device that shares the interrupt level, selects the interrupt factor that occurs asynchronously with priority and performs exclusive processing. This realizes multiple interrupt processing and eliminates the above-mentioned problems.

Specifically, we prioritize interrupt factors,
In the processing routine of the priority interrupt factor, processing of interrupts caused by other interrupt factors is prohibited, and
After processing the interrupt by this processing routine, if an interrupt caused by another interrupt factor has been set, dummy processing is performed for that interrupt factor to cancel the interrupt factor.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail using the drawings. FIG. 2 is a block diagram showing an example of the configuration of a personal computer to which the present invention is applied. In the figure, 11 is a microprocessor (CPU) which is the core of control, 12 is a main memory (MU), and 13 is an interrupt controller (INTC). The interrupt controller 13 is assumed to be the above-mentioned programmable interrupt controller Intel 8259A. or,
14 is a CRT controller (CRTC), 15 is a floppy disk controller (FDC), 16 is a fixed disk controller (FMKC), 17 is a car board and keyboard controller (KBC), 1
8 is a programmable interval timer (TIM) that generates an interrupt signal every 20 milliseconds, and 19 is an RS-
232C communication channel controller (CCU), 20
is an option board (OB). Each of these modules is commonly connected to an address/data bus 21.

Each of the modules 15 to 20 serving as an interrupt factor is connected to the interrupt controller 13 as shown in FIG. In this example, a floppy disk controller 15 and an option board 20 are connected to interrupt level 0 via an OR gate 22. The interrupt controller 13 controls interrupt requests of 8 levels (0 to 7) as described above, and controls the interrupt requests of the CPU 1.
A CALL command is automatically generated as a vector address based on an interrupt response signal issued from CPU 11, and a predetermined interrupt process is performed by sending an interrupt signal to CPU 11.

In the embodiment of the present invention, a register or flip-flop (not shown) is provided in the device configuration described above to identify the input interrupt factor, and each time an interrupt occurs, appropriate data or a corresponding A flag is set. This register or flip-flop is
It is intentionally not shown here because it may be allocated to the internal registers of 11 or the input/output registers built into each module. In the embodiment of the present invention, a program for interrupt processing shown as a flowchart in FIG. 4 is further added.

Hereinafter, the operation of the present invention will be explained in detail according to the flowchart shown in FIG. For reference, the processing procedure according to the conventional example is shown in FIG. First, at the beginning of the processing procedure, in the present invention, the option board 20
It is checked whether or not interrupts are prohibited. (Step) In the embodiment of the present invention, reception of interrupts issued from the option board 20 is prohibited in advance by turning on a built-in software flag by the main routine for the floppy disk 15 service, which should be processed with priority. ing. Therefore, according to the contents of this flag, the interrupt service (step) of the floppy disk 15 is activated. After this interrupt service is completed, if an interrupt issued from the option board 20 is set in the register or flip-flop, a routine for option board interrupt dummy READ is activated.
(Steps) This dummy routine is constructed with as few steps as possible to cancel the interrupt factor. For reference, FIG. 3 shows a processing procedure according to a conventional example. As can be seen from a comparison with this, steps are added in the present invention.

By the way, the program that controls the option board 20 has a processing method that waits until data processing on the floppy disk 15 is completed by referring to whether or not the above-mentioned flag (option board interrupt prohibition) is set. Needless to say.

In the embodiment of the present invention, only two types of multiple interrupts have been described, but even if there are three or more types of input/output devices to be managed, the same method can be used to adequately handle the case.

〔Effect of the invention〕

As explained above, according to the present invention, by selecting on the main routine side whether or not an interrupt that occurs asynchronously is necessary and performing exclusive processing, for example, an asynchronous interrupt from an option board can be generated in a floppy disk data processing routine. Interruptions can be avoided, thereby eliminating problems such as data loss during floppy disk data transfer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a connection state of an interrupt input to an interrupt controller, and FIG. 2 is a diagram showing an example of the configuration of a personal computer to which the present invention is applied.
FIG. 3 is a flowchart showing the processing procedure according to the conventional example, and FIG. 4 is a flowchart showing the processing procedure according to the present invention. 11...Microprocessor (CPU), 12...
...Main memory (MU), 13...Interrupt controller (INTC), 15...Floppy disk controller (FDC), 20...Option board.

Claims (1)

[Scope of Claims] 1. In an interrupt processing device that receives input of at least two interrupt factors that occur asynchronously for the same interrupt level and that shares the interrupt level, recognizes an interrupt that is issued based on the above-mentioned interrupt factor. means for setting necessary/unnecessary information for interrupt factors of the same interrupt level in the main routine; and means for prohibiting acceptance of interrupts due to interrupt factors set as unnecessary by the above setting means. and recognizes whether an interrupt has occurred due to the interrupt factor set as unnecessary by referring to the storage means, and
A multiple interrupt processing method characterized by comprising means for canceling an interrupt when the interrupt occurs.