JPH05316069A - Signal error detection system - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by providing a parity calculation section outputting 1st and 2nd parities from inputted parities, a stuff synchronization section outputting the 1st and 2nd parities and a main signal synchronizingly and a parity comparator section to the system. CONSTITUTION:A parity calculation section 100 in Figure (b) outputs a parity (c) as the result of parity calculation of signals a1-an in a main signal in a timing T1 at first as a parity P and then outputs a parity (d) as the result of calculation of signals b1-bn in a timing T2 as the parity P. A stuff synchronization section 200 outputs a parity PTY of main signals DT1-DTn as information synchronous with a clock CLK 2 from the parity P of the main signals D1-Dn. A parity comparator section 300 receiving two kinds of signals applies parity calculation again to the main signals similarly to the case with the calculation section 100. The result and the parity PTY being an output signal from the synchronization section 200 are compared and an error signal ER is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal erroneous detection system for monitoring an error in a stuff synchronizing section of digital communication.

[0002]

2. Description of the Related Art In a conventional signal erroneous detection method, a result of parity calculation is inserted into a vacant portion of a main signal, passed through a stuff synchronization section, and then parity is calculated again, and the parity value inserted into the main signal is compared to make an error. It was detecting.

In the conventional example of FIG. 2, description will be made assuming that n main signals are parallelized and processed by the stuff synchronizer.

In the timing extractor F1 which has received the n parallel signals D11 to Dn1 (hereinafter referred to as main signals) and the clock CL1, the parity calculators CAL1 to CALn, the parity inserter INS and their respective timing signals TM1.
I am making TM2. Using this timing, each of the main signals DD in the parity calculators CAL1 to CALn
The parity values P11 to Pn1 of 11 to DDn1 are calculated.

Further, the parity insertion unit INS inserts the parity values P11 to Pn1 into each of the main signals D11 to Dn1. Main signal D with this parity value inserted
11 to Dn1 are converted by the stuff synchronizer ST into main signals DT11 to DTn1 synchronized with the clock CL2.

Main signals DT11 to DTn1 and clock CL
In the timing extraction unit F2 that receives 2, the timings required by the parity separation unit DRP and the parity calculation unit CAL21 are extracted and the timings TM3 and TM4 are output. In the parity separation unit DRP, the main signal D is generated by the timing TM3.
Parity values included in T11 to DTn1 are separated and parity values OH11 to OHn1 are output.

In the parity calculator CAL21, the parity is calculated according to the timing TM4, and the parity values PTY11 ...
Output PTYn1. The parity comparison unit COP compares the parity values with each other (OH11 and PTY11, ...
, (OHn1 and PTYn1 are compared with each other) and the result is added and an error signal ERR is output. Therefore, by monitoring the error signal ERR, it is possible to detect the malfunction of the stuff synchronizer ST.

[0008]

In this conventional signal erroneous detection method, a timing extraction unit for inserting the result of parity calculation in the main signal and a timing for separating the parity value inserted in the main signal. An extraction circuit is required, and since n parity calculation units are required to perform parity calculation for each of the n main signals parallelized, there is a drawback that the circuit scale becomes large.

[0009]

According to the signal erroneous detection method of the present invention, a parity calculation is performed on n parallel signals included in a main signal at a first timing of a first clock, and a first parity value is calculated. And a parity calculator that calculates the parity of the signal at a second timing of the first clock and outputs the parity signal as a second parity value, the first and second parity values, and the main signal. A stuff synchronizer that outputs each in synchronism with two clocks, and a third parity calculation of the parallelized n signals included in the main signal.
And a parity comparison unit that compares the fourth parity value with the first and second parity values and outputs an erroneous signal.

[0010]

The present invention will be described below with reference to the drawings. 1A is a block diagram of an embodiment of the present invention, FIG.
(B) is a diagram for explaining the operation of the parity calculation unit of the present embodiment.

In this embodiment, at the first timing T1 of the first clock CLK1, the n parallel signals a1 to an contained in the main signals D1 to Dn are subjected to parity calculation to obtain a first parity value C. A parity calculation unit 1 that outputs the parity of n signals b1 to bn at the second timing T2 of the clock CLC1 and outputs the parity as the second parity value d.
00, the first and second parity values c and d, and the main signal DT1
To DTn in synchronization with the second clock CLK2, respectively, and the stuff synchronizer 200, and the main signals DT1 to DT1.
The third and fourth parity values c ′ and d ′ obtained by reparity calculation of the parallelized n signals included in Tn and the first
And a second parity value c, d, and outputs a false signal ER.

Next, the operation of this embodiment will be described. In FIG. 1B, the parity calculator 100 first outputs the parity value c as a parity value P, which is the result of the parity calculation of the signals a1 to an in the n main signals at the timing T1. At the next timing T2, the signal b is the same as T1.
The parity value d, which is the calculation result of 1 to bn, is set to the parity value P.
Output as. Other timings are serial 1
The parity value P of the book is output.

In the stuff synchronizer 200, main signals D1 to
The main signals DT1 to DTn and the parity value PTY are output as information in which Dn and the parity value P are synchronized with the clock CLK2. The parity comparison unit 300, which has received these two types of signals (main signal and parity value), first re-parity-calculates the main signal as in the parity calculation unit 100. This result is compared with the parity value PTY which is the output signal from the stuff synchronizer 200, and the error signal ER is output.

[0014]

As described above, the present invention calculates the parity of n parallel signals included in the main signal at the first timing of the first clock and outputs it as the first parity value. A parity calculator that calculates the parity of the signal at the first clock second timing and outputs the parity as a second parity value, and synchronizes the first and second parity values and the main signal with a second clock. And the parallel output of the stuff synchronizing section included in the main signal.
By having a parity comparison unit that compares the third and fourth parity values obtained by performing the parity calculation of the book signal again with the first and second parity values and outputs an erroneous signal, the stuff synchronization unit is prevented from malfunctioning. The configuration of the detection circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram (a) and a timing diagram (b) of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional signal erroneous detection method.

[Explanation of symbols]

 100 Parity calculation unit 200 Stuff synchronization unit 300 Parity comparison unit CLC1, 2 clocks D1 to Dn, DT1 to DTn Main signal ER False signal

Claims (1)

[Claims] 1. Parity calculation of n parallel signals included in a main signal at a first timing of a first clock is output as a first parity value, and a second parity of the first clock is output. A parity calculator for calculating the parity of the signal at a timing and outputting the parity as a second parity value;
And a stuff synchronizer that outputs the second parity value and the main signal in synchronization with the second clock, and a third parsed parity of n parallel signals included in the main signal. A signal erroneous detection method comprising: a parity comparison unit that compares a fourth parity value with the first and second parity values and outputs an erroneous signal.