JPH05315763A - Installation board device and its installation method - Google Patents

Abstract

PURPOSE:To prevent a decrease in quality of a board and to reduce a manufacturing cost by providing first wiring group in which wirings are allocated for a single wiring layer of the board and a second wiring group in which an intersection of the wirings is bypassed to the other wiring layer of the board to be allocated for a plurality of wiring layers. CONSTITUTION:A mounting board device has a plurality of ICs each having a plurality of inputs and a plurality of outputs and disposed in a plurality of rows each having (n) pieces of ICs on a board and wirings between the rows. The device has a first wiring group in which wirings for connecting output sides of the ICs of one row to input sides of the IC of the other row are allocated for a single wiring layer of the board. The device further has a second wiring group in which an intersection of the wirings for connecting the output side of the IC of one row to the input side of the IC of the other row is bypassed to the other wiring layer of the board to be allocated for the plurality of the wiring layers. The total number of the wiring layers is set to smaller than the (n) pieces of the layers. Thus, a decrease in quality of the board can be prevented, and a manufacturing cost can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board device mounted with an IC having a plurality of inputs and outputs and a mounting method for mounting the IC on a board.

[0002]

2. Description of the Related Art Recently, an ATM (Asynchronous Transfer Mode) switching network has been put into practical use as a network for realizing multimedia communication in which voice, data, still images, moving images, etc. are integrated.

In such an ATM switching network, information communication is performed using short packets having a fixed length called cells. In this case, the cells are output from the transmission side terminal at arbitrary timing, and other cells are output. It is multiplexed with the cell from the transmitting terminal and is sent to the intended receiving terminal via the ATM switch.

Usually, an ATM exchange is a unit switch IC.
6 are connected in multiple stages. For example, as shown in FIG.
# 11 having an input communication path and an 8-output communication path respectively
~ # 18 unit switch IC1 in the first row, # 21 ~ #
28 unit switches IC1 in the second row, # 31 to # 38
With the unit switch IC1 of No. 3 as the third column, a total of 24 unit switch ICs are used, and 64 input communication paths and 64
There is one that constitutes an ATM switch for an output communication path. In the ATM switch configured as described above, the wiring is performed on the multilayer printed circuit board. In this case, the wiring of each layer on the printed circuit board is assigned as follows.

FIGS. 7 and 8 show wiring between the unit switch ICs 1 in the first and second columns. First, the wiring between each output communication path of the unit switch IC1 of # 11 in the first column and the input communication path of the unit switch IC1 of # 21 to # 28 in the second column shown in FIG. 7A. Are assigned to the first layer, and each output communication path of the unit switch IC1 of # 12 in the first column and # 21 in the second column shown in FIG.
Wiring to the input communication path of each unit switch IC1 of # 28 to # 28 is assigned to the second layer. Further, each output communication path of the # 13 unit switch IC1 in the first column and each of the unit switch ICs # 21 to # 28 in the second column shown in FIG.
The wiring to the input communication path of 1 is assigned to the third layer,
Thereafter, in the same manner, wiring as shown in FIG. 8D and FIGS. 8A to 8D is performed, and finally the eighth layer is allotted.

By the way, in such an ATM exchange,
For high-speed, large-volume data communication, each unit switch I
It is necessary to connect C by a high-frequency transmission line, and when a printed board is used, it is generally a strip line.

Therefore, as described above, each unit switch I
When eight signal wiring layers are used for the connection of C, 17 layers of printed circuit boards with a plane layer interposed between the strip layers are required to form the strip lines. FIG. 9 shows a layer structure of such a printed circuit board, and eight signal wiring layers S1 to S8 are laminated with plane layers P1 to P9 interposed.

[0008]

However, it is generally said that the difficulty in manufacturing a multi-layered printed board increases in proportion to the number of layers. In addition to the remarkable deterioration of quality, there is a drawback that the manufacturing cost rises.

The present invention has been made in consideration of the above circumstances, and provides a mounting substrate device and a mounting method which can reduce the number of layers of a substrate, prevent the deterioration of the quality of the substrate, and significantly reduce the manufacturing cost. It is intended to be provided.

[0010]

SUMMARY OF THE INVENTION A mounting board device of the present invention is a mounting board in which ICs having a plurality of inputs and a plurality of outputs are arranged on the board in a plurality of n rows each and wirings between the rows are provided. In the device, a first wiring group in which wirings that connect the output side of the ICs in one row and the input side of the ICs in the other row are assigned to a single wiring layer of the substrate, and the ICs in one row A second wiring group in which the wiring connecting the output side and the input side of the IC in the other column is assigned to a plurality of wiring layers by bypassing the intersection of the wiring to another wiring layer of the substrate, The total number of the wiring layers is set to be smaller than that of the n layers. In the mounting method of the present invention, ICs each having a plurality of inputs and a plurality of outputs are arranged on the substrate in a number of n rows and m rows, and wiring is performed between the columns. Almost all the ICs in the other row are connected from the IC located in the first row in one row as the starting point, and almost all in the above one row from the IC located in the nth row in the other row as the starting point. A plurality of wirings for connecting the above ICs to an arbitrary first wiring layer,
Almost all the ICs except the n-th IC in the other row are connected with the IC located in the second row as a starting point, and the one row in the one row with the n-1th IC in the other row as a starting point A plurality of wirings for connecting almost all the ICs except for the IC located at the first position are assigned to an arbitrary second wiring layer, and the remaining total number of wirings is the same as the number of wirings of the first wiring layer. Until each wiring is at least approximately 1/2 to 2 times, an arbitrary third layer or later of the substrate is assigned to each wiring, and thereafter at least a part of the remaining wiring is assigned to two different layers of the substrate. , Wiring is performed up to the connection between the IC in one row and the IC in the other row, starting from the n-th IC in the one row and the first IC in the other row, respectively. I am trying. Further, it is characterized in that at least a part of the wiring allocated to an arbitrary wiring layer is modified and wired so as to be allocated to another wiring layer.

[0011]

As a result of the above-mentioned configuration, conventionally, an IC is usually used.
In the case of arranging a plurality of n rows in each row on the substrate, the number of layers of the substrate required n layers, but since it can be configured to be smaller than the n layers, this makes it possible to maintain the quality of the substrate. It is possible to suppress the steep rise in manufacturing costs.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In the following main embodiments, the case where the mounting board device and the mounting method according to the present invention are applied to an ATM exchange will be described. However, as will be described later, the mounting board device and the mounting method according to the present invention are It is not limited to the case of being applied to an ATM exchange.

1 and 2 are # 11- # 8 having 8 input communication paths and 8 output communication paths as shown in FIG.
Set the unit switch IC1 of # 18 to the first row, similarly to # 21.
The unit switches IC1 of # 28 to the second column, # 31 to #
A total of 24 unit switch IC1s in the third row
In the ATM switch having 64 input communication paths and 64 output communication paths, each of the unit switch ICs is used.
Unit switch IC1 of # 18 and # 21 to # 2 of the second column
The case where the wiring between the eight unit switch ICs 1 is realized on the printed circuit board is shown.

In this case, first, as shown in FIG. 1A, the unit switch IC1 of # 11 in the first column and the # of the unit switch IC in the second column.
Starting from the unit switch IC1 of 28,
Each of the output communication paths of the unit switch IC1 of 11 and the input communication path of the unit switch IC1 of # 21 to # 28 in the second column are connected to each input communication path of the unit switch IC1 of # 28 in the second column. And the unit switches I of # 11 to # 18 in the first column
Each output communication path of C1 is connected. In this case, the number of wires is 15.

Next, as shown in FIG. 3B, starting from the # 12 unit switch IC1 in the first row and the # 27 unit switch IC1 in the second row, the # 12 unit switch IC1 in the first row starts. Each output communication path of the unit switch IC1 and # 21 to # in the second column
The input communication paths of the unit switches IC1 of No. 27 are connected, and the input communication paths of the unit switch IC1 of # 27 of the second row and the output communication paths of the unit switch IC1 of # 12 to # 18 of the first row are connected. Are connected. In this case, the number of wirings is 13.

Next, as shown in FIG. 3C, starting from the # 13 unit switch IC1 of the first column and the # 26 unit switch IC1 of the second column, the # 13 unit switch IC of the first column is set. Each output communication path of the unit switch IC1 and # 21 to # in the second column
26, the input communication paths of the unit switches IC1 of No. 26 are connected, and the input communication paths of the unit switch IC1 of # 26 of the second row and the output communication paths of the unit switch IC1 of # 13 to # 18 of the first row are connected. Are connected. In this case, the number of wires is 11.

Next, as shown in FIG. 3D, starting from the # 14 unit switch IC1 in the first column and the # 25 unit switch IC1 in the second column, the # 14 unit switch IC1 in the first column starts. Each output communication path of the unit switch IC1 and # 21 to # in the second column
25, the input communication paths of the unit switches IC1 of 25 are connected to each other, and the input communication paths of the unit switch IC1 of the second row # 25 and the output communication paths of the unit switches IC1 of the first row # 14 to # 18 are connected. Are connected. In this case, the number of wires is 9.

Next, as shown in FIG. 2A, starting from the # 15 unit switch IC1 of the first column and the # 24 unit switch IC1 of the second column, the # 15 unit switch IC1 of the first column is set. Each output communication path of the unit switch IC1 and # 21 to # in the second column
24, the input communication paths of the unit switches IC1 of 24 are connected to each other, and the input communication paths of the unit switch IC1 of the second row # 24 and the output communication paths of the unit switches IC1 of the first row # 15 to # 18 are connected. Are connected. In this case, the number of wires is 7.

Next, as shown in FIG. 2B, focusing attention on the # 16 unit switch IC1 of the first row and the # 23 unit switch IC1 of the second row, the # 16 unit switch IC1 of the first row is selected. Each output communication path of the unit switch IC1 and # 21 to # 23 in the second column
Connected to the input communication paths of the unit switches IC1 of the unit switch IC1
The output communication paths of the unit switches IC1 of # 16 to # 18 in the column are connected. The number of wires in this case is five.

Next, as shown in FIG. 2C, starting from the # 17 unit switch IC1 in the first column and the # 22 unit switch IC1 in the second column, the # 17 unit switch IC1 in the first column is set. Each output communication path of the unit switch IC1 and # 21, # in the second column
22 are connected to the input communication paths of the unit switches IC1 of the second row, and the input communication paths of the unit switch IC1 of the second row # 22 and the output communication paths of the unit switches IC1 of the first row # 17 and # 18. Are connected. In this case, the number of wires is three.

Finally, as shown in FIG. 2D, the first
The output communication path of the unit switch IC1 in the column # 18 and the second
The input communication path of the unit switch IC1 of # 21 in the column is connected. In this case, the number of wires is one.

For the respective wirings shown in FIGS. 1A to 1D, independent signal wiring layers from the first layer to the fourth layer are assigned. Then, the remaining number of wirings is almost the same as the number of wirings of the first layer, here 15 wirings, as shown in FIG.
About 16 wirings in total shown in (d) to (d) are wired using two signal wiring layers of the fifth layer and the sixth layer.

In the wirings shown in FIGS. 2A to 2D, for wirings that cross each other, one wiring bypasses the other wiring by utilizing the fifth layer and the sixth layer. The wiring is done to avoid cross points.

The signal wiring layers from the first layer to the sixth layer, if these are strip layers, are composed of 13 layers of printed boards with a plane layer interposed between the strip layers. FIG. 3 shows a layered structure of such a printed circuit board. Six signal wiring layers S11 to S16 are laminated with plane layers P11 to P17 interposed.

In the above embodiment, after the number of remaining wirings becomes substantially the same as that of the wirings in the first layer, the remaining wirings are assigned to two different layers. However, the present invention is not limited to this embodiment. It is not limited. That is, for the wirings shown in FIGS. 1A to 1C, 15 wirings, 13 wirings, and 11 wirings, respectively, independent signal wiring layers from the first layer to the third layer are allocated. 1 (d) and FIG. 2 in which the number of remaining wires is approximately twice or less than the number of wires (15 wires) in the first layer.
(A) to (d) 25 in total (9, 7, 5, 3
For the (one, one) wiring, the signal wiring layers of the fourth and fifth layers may be used.

Also in this case, as for the wirings which cross each other in the remaining wirings, the remaining fourth and fifth layers are used to bypass the wirings to avoid cross points, as in the previous embodiment. Wire.

As in this embodiment, when the number of remaining wirings is about twice or less of that of the first layer having the most wirings, if the remaining wirings are assigned to different two layers, the board itself is the most wiring. In consideration of designing for the first layer, which has a large number, the most efficient wiring can be performed. In this embodiment, the layer structure of the printed circuit board can be achieved by five signal wiring layers, and the number of signal wiring layers can be further reduced as compared with the conventional eight layers shown in FIGS.

As yet another embodiment, FIG. 1 (a)
15 to 13, 11 shown in FIG.
For each of the 9th, 7th, and 7th wirings, independent signal wiring layers from the first layer to the fifth layer are allocated, and the number of remaining wirings is approximately ½ or more times the number of wirings of the first layer. Figure 2
A total of nine wires (b) to (d) may be wired using the sixth and seventh signal wiring layers. In this case, the number of signal wiring layers can be reduced by one as compared with the conventional example.

Therefore, when such a wiring method is adopted, the wiring between the unit switches IC1 of # 11 to # 18 in the first column and the unit switches IC1 of # 21 to # 28 in the second column is first. Wiring with the unit switches IC1 in the second or first row is performed while moving the respective starting points from the # 11 side in the second row and from the # 28 side in the second row, and the respective wirings are connected to the printed board. , And the total number of remaining wirings is at least approximately ½ times, and at most approximately twice, the number of wirings in the first layer, the remaining wirings are assigned to two different layers of the printed board. As a result, compared with the conventional wiring method, the number of layers of the printed circuit board can be reduced, which can prevent the deterioration of the quality of the printed circuit board and significantly reduce the manufacturing cost. Become.

In the above embodiment, after the total number of the remaining wirings is at least about 1/2 times, and at most about twice the number of the wirings of the first layer, the remaining wirings are different from those of different boards.
Although it is configured to be allocated to layers, the number of ICs having a plurality of inputs and a plurality of outputs is not limited to 1/2 to 2 times, and when n rows are arranged on the substrate in a plurality of rows. If the total number of wiring layers can be made smaller than n layers, if it is smaller than 1/2 times, for example, 1/3 times or 1 /
It may be 4 times or the like, and when it is more than 2 times, for example, 3 times or 4 times. Further, after the total number of the remaining wirings reaches the predetermined value as described above, the remaining wirings are configured to be allocated to two different layers of the substrate, but the present invention is not limited to this. It may be assigned to different three layers or four or more layers. Especially, the total number of remaining wiring is 4 for the first layer.
In the case of a large amount such as twice or more, if the layers are allocated to different two layers, the number of wirings is unevenly distributed to these two layers, so that
There may be cases where it is better to allocate more layers.

Further, in the above-described embodiment, for example, all the ICs in the second row are connected from the IC located in the first row in the first row as the starting point, and the I located in the nth row in the second row is connected.
Connect all ICs on the 1st column starting from C
However, it is not necessary to mechanically perform all wiring in this way, and one or several of these wirings, about half of them in an extreme example, is the first wiring layer. You don't have to connect with.

That is, the present invention can be implemented by being modified so that at least a part of the wirings to be assigned to any wiring layer in the above embodiment is assigned to another wiring layer.

The reason why this modification can be carried out is that when at least a part of the input or output terminals is originally unnecessary due to the circuit design of various devices, or because of the wiring design, other wiring is required. Reasons such as when it is more convenient to assign to layers are given. When the input terminal or the output terminal is originally unnecessary as described above, the terminal is not formed in the IC itself or the terminal is formed in the IC, but these input / output terminals are not electrically connected. Including cases. Further, the above description of the modified example is not limited to the connection example starting from the first in the first column and the n-th in the second column, and is applied to the connection of the ICs in any column in any order. After all, even if the connections are not neatly arranged as in the example shown in FIG. 1 or FIG. 2 due to design reasons or the like, they may be almost connected according to the concept of the present invention. Next, an example of the case where it is more convenient to assign the wiring layer to another wiring layer in the wiring design described in the above modification will be described with reference to FIG.

In the embodiment shown in FIG. 4, some of the wirings assigned to the first wiring layer as shown in FIG. 1A in the embodiment shown in FIGS. 1 and 2, for example, The wirings shown by broken lines a1 and a2 in FIG. 4 may be assigned to the second wiring layer as shown by solid lines a1 ′ and a2 ′, or may be assigned to the second wiring layer as shown in FIG. Some of the existing wirings, for example, the wirings shown by broken lines b1 and b2 in FIG. 4 are assigned to the third wiring layer as shown by solid lines b1 ′ and b2 ′, or although not shown, the wirings shown in FIGS. It is also possible to modify some of the wirings of the arbitrary layer shown in 2 so as to be allocated to other wiring layers, and to average the number of allocated wirings.

Further, in the above-described embodiment, the unit switches IC1 of # 11 to # 18 in the first column and # 2 in the second column.
The case where the wiring between the unit switch ICs 1 to # 28 is realized on the printed circuit board has been described.
The same applies to the case where the wiring between the unit switch IC1 of No. 8 and the unit switch IC1 of # 31 to # 38 in the third column is realized on the printed board. Further, in the above description, the unit switch ICs having 8 input communication paths and 8 output communication paths are applied to an ATM switch having a 64 input communication path and a 64 output communication path by using a total of 24 unit switch ICs, 3 in 8 rows. Although an example has been described, it is also possible to apply to an ATM switch having a configuration in which n columns and m columns are provided. Next, an embodiment other than the printed board to which the mounting board device of the present invention can be applied will be briefly described.

FIG. 5 shows a multi-chip module (MC
It is a schematic sectional drawing of M). The MCM is a device in which an unpackaged IC chip 11 (bare chip) is mounted on a ceramic substrate or a multilayer wiring substrate 10 in which polyimide resin and wiring layers such as copper are alternately laminated and housed in a case 12. .. Even in the MCM, in order to configure the strip line wiring, a plane layer is required between one signal wiring layer and another signal wiring layer, and its formation becomes difficult as the number of layers increases. Therefore, the mounting method of the present invention described in the embodiments of FIGS. 1 to 4 is effective, and it is easy to reduce the manufacturing cost and maintain the quality of the MCM.

The MCM can be applied not only to a switch module of a communication device such as an ATM switch, but also to an electronic device such as a personal computer, a workstation, a super computer, or other high-density mounting device, that is, The mounting substrate device and the mounting method of the present invention can be widely applied in addition to the ATM switch.

[0039]

As described in detail above, according to the present invention, it is possible to reduce the number of layers of the substrate, thereby preventing the deterioration of the quality of the substrate and realizing a great reduction in the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a wiring method of a printed circuit board for an ATM exchange according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of wiring a printed circuit board for an ATM exchange according to an embodiment of the present invention.

FIG. 3 is a schematic view showing a layer structure of a printed board obtained by the wiring method of the embodiment shown in FIGS. 1 and 2.

FIG. 4 is a diagram for explaining a wiring method according to a modified example of the mounting method of the present invention.

FIG. 5 is a schematic sectional view of an MCM (multi-chip module) according to a modification of the present invention.

FIG. 6 is a diagram showing a circuit example of an ATM exchange.

FIG. 7 is a diagram for explaining an example of a conventional wiring method for a printed circuit board for an ATM exchange.

FIG. 8 is a diagram for explaining an example of a conventional wiring method for a printed circuit board for an ATM exchange.

FIG. 9 is a diagram showing a layer structure of a printed board obtained by the wiring method shown in FIGS. 7 and 8;

[Explanation of symbols]

 1 unit switch IC (IC) S11 to S16 signal wiring layer P11 to P17 plane layer 10 multilayer wiring board 12 IC chip 13 case

Claims (3)

[Claims] 1. An I having multiple inputs and multiple outputs.
In a mounting board device in which a plurality of C's are arranged in n rows on the board and wiring is provided between the rows, wiring for connecting the output side of the IC in one row and the input side of the IC in the other row is provided. First assigned to a single wiring layer of the substrate
And a wiring connecting the output side of the IC of one row and the input side of the IC of the other row are assigned to a plurality of wiring layers by bypassing the intersection of the wiring to another wiring layer of the substrate. And a second wiring group, wherein the total number of the wiring layers is set to be less than n layers. 2. An I having multiple inputs and multiple outputs.
In a mounting method for arranging C rows on the substrate in n rows and m rows and performing wiring between the rows, starting from the IC located at the first position of one row of each corresponding pair of rows. A plurality of wirings for connecting almost all the ICs of the other row and connecting almost all the ICs of the one row starting from the nth IC of the other row are arbitrary first wirings. Allocating to a layer, connecting almost all ICs except the nth IC in the other row from the second IC in the one row as a starting point, and n-1th in the other row A plurality of wirings for connecting almost all ICs except the first IC in the one row from the located IC as a starting point are assigned to an arbitrary second wiring layer, and the remaining total number of wirings is similarly determined. The number of wires in the first wiring layer is small. In each case, each wiring is assigned an arbitrary third layer or later of the substrate until approximately 1/2 to 2 times, and thereafter, at least a part of the remaining wiring is assigned to two different layers of the substrate. Wiring is performed up to the connection between the IC in one row and the IC in the other row, starting from the nth IC in the row of one step and the first IC in the other row, respectively. How to implement. 3. The mounting method according to claim 2, wherein at least a part of the wiring allocated to the arbitrary wiring layer is allocated to another wiring layer.