JPH07211999A - Package for semiconductor chip - Google Patents

Abstract

PURPOSE:To provide a package for semiconductor chip composed of a laminated ceramic wiring board, laminated ceramic wiring board on which a thin film wiring layer is formed, or laminated ceramic wiring board on which a resin wiring board is formed. CONSTITUTION:In a package for semiconductor chip composed of a laminated ceramic wiring board 1 on which a resin wiring layer 2 is formed, independent feeder lines are provided at every semiconductor chip 3 and the feeder lines are led out from the rear surface of the board 1 in the shortest distance through paired via holes 7 and 8 provided vertically below the feeder lines. Therefore, the resistance values of the feeding routes can be reduced and the high-speed multi-terminal semiconductor chips can be fed with electricity without generating any power supply noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package comprising a laminated ceramic wiring board, a laminated ceramic wiring board having a thin film wiring layer formed thereon, or a laminated ceramic wiring board having a resin wiring layer formed thereon.

[0002]

2. Description of the Related Art Conventionally, in order to realize a compact and highly functional high-speed electronic circuit module, for example, a polymer resin is used as an interlayer insulating film, and a plurality of wiring layers and a multilayer ceramic wiring board are formed therein. A single-chip package or a multi-chip package in which one or a plurality of semiconductor elements are mounted on a resin wiring layer has been developed.

The input / output power supply terminal structure of these package modules will be described by taking as an example the configuration in which the resin wiring layer shown in FIG. 9 is mounted.

As shown in FIG. 9, the power supply terminals 64 (a, b, c, d) arranged on the surface of the semiconductor chip 63 are connected to the resin wiring by the conductive balls 65 (a, b, c, d) for connection. After being connected to the power supply terminals 6 (a, b, c, d) on the surface of the layer 62, the via holes 67 (a,
b, c, d), the via hole 6 is formed on the land 68 (a, b, c, d) on the surface of the ceramic wiring board 61.
7 (a, b, c, d), via the development wiring on the surface of the ceramic wiring board 61, and via holes V6 (a, b, c, d) in the ceramic wiring board 61.
Connected to the power supply layer P61 (a, b,
c, d) and the power supply layer P61 up to the position of the via hole V6 (a, b, c, d) in the ceramic wiring board 61.
It is expanded via (a, b, c, d) and connected to the power supply terminal T61 (a, b, c, d) of the package through the via hole V6 (a, b, c, d). ing.

Conventionally, in the connection between the power supply terminal of the semiconductor chip and the power supply terminal of the package, the electrical characteristics are not taken into consideration, and the power supply terminal of the semiconductor chip is vertically arranged on the surface on which the power supply terminal of the package is arranged. The power supply terminal of the package and the power supply terminal of the semiconductor chip at a position apart from the position projected on the board were connected.

Further, in order to simplify the structure, the same kind of power supplies are collectively supplied to a plurality of chips through a common power supply layer. For example, the chip power supply terminal 64d of the semiconductor chip 63 is connected to the power supply terminal 66d on the surface of the resin wiring layer 62 by the conductive balls 65d for connection, and then connected to the via hole 67d in the resin wiring layer 62, It is connected to a land 68d on the surface of the ceramic wiring board via a via hole 67d, and is connected to a via hole V60d in the ceramic wiring board 61 via a development wiring on the surface of the ceramic wiring board 61.

Further, the via hole V60d is a power source layer P.
The via hole V60d is deployed via 61d.
It is connected to the power supply terminal T61d of the package via (right end in the drawing). In addition, the power supply layer P61d includes vias V61d for feeding the other semiconductor packages 631 and 632.
And V62d are also connected, via hole V60
d is shared and connected to the power supply terminal T61d. In this case, a plurality of via holes V60d and power supply terminals T61d may be provided.

[0008]

The above-mentioned conventional structure shown in FIG. 9 has the following drawbacks.

Since the path from the power supply terminal of the semiconductor chip to the power supply terminal of the package is long, the voltage drop due to the resistance of the path is large, and the length of the path is different for each power supply terminal of the semiconductor chip. Potential variations occur at the and cause malfunctions. Furthermore, the self-inductance of the path is large, and simultaneous switching noise occurs, making high-speed operation difficult.

Further, the forward power supply via hole and the return power supply via hole forming the current path, the forward power supply layer and the return power supply layer, and the forward power supply terminal and the return power supply terminal of the package respectively have a structure in which electrical characteristics are particularly taken into consideration. However, noise in the power supply system has become a problem as the speed of signals increases and the scale of modules increases.

In view of the above problems, it is an object of the present invention to provide a semiconductor chip package having high speed transmission characteristics.

[0012]

The structure of a first semiconductor chip package according to the present invention which achieves the above-mentioned object is a semiconductor chip package made of a laminated ceramic wiring board, wherein each semiconductor chip has an independent power supply line. Is provided
It is characterized in that the power supply line is pulled out from the back surface of the substrate at the shortest distance via a via provided vertically below.

In the semiconductor chip package having the above structure, a thin wiring layer or a resin wiring layer is formed on the laminated ceramic wiring board.

That is, the first invention is a package comprising a laminated ceramic wiring board and having one or a plurality of semiconductor chips mounted therein, and the connection between the power supply terminal of the semiconductor chip and at least one power supply terminal of the package. The shortest distance that can produce the wiring path used in (1), preferably the vertical distance, preferably the distance of the developed portion is small, and the structure is such that power is supplied from the power supply terminal provided on the back surface of the substrate, and the resistance value of the power supply path can be reduced. As a result, it is different from the conventional one in that it is possible to supply power to a high-speed, multi-terminal semiconductor chip without generating power supply noise.

A second structure of the semiconductor chip package according to the present invention is, in a semiconductor chip package composed of a laminated ceramic wiring board, a forward power supply layer and a return path which form a current loop provided inside each laminated ceramic wiring board. At least one pair is adjacent to the power supply layer and is provided at a narrow interval.

In the above semiconductor chip package,
A thin wiring layer or a resin wiring layer is formed on a laminated ceramic wiring board.

In the semiconductor chip package, the narrow distance between the forward power supply layer and the return power supply layer forming the current loop is 400 μm or less.

That is, the second aspect of the present invention is a package comprising a laminated ceramic wiring board and mounting one or a plurality of semiconductor chips, the forward power supply layer and the return path forming a current loop provided in the laminated ceramic wiring board. With the configuration in which at least one pair of power supply layers are adjacent to each other and they are provided at a narrow interval, the mutual inductance between adjacent power supply layers increases and the effective inductance can be reduced. Further, the power supply layers provided at a narrow interval form a parallel plate capacitor, and the inductance of the developing wiring portion can be canceled by the capacitance and reduced. Due to the above two effects, it is possible to supply power to a high-speed, multi-terminal semiconductor chip without generating power supply noise, which is different from the conventional case.

Further, a third structure of the semiconductor chip package according to the present invention is a semiconductor chip package comprising a laminated ceramic wiring board, in which current is applied in each laminated ceramic wiring board and a wiring layer formed on the wiring board. At least one pair of forward path power supply vias and return path power supply vias forming the loop, and the package forward path power supply elements and return path power supply elements are adjacent to each other and are provided at a narrow interval.

In the above semiconductor chip package,
A thin wiring layer or a resin wiring layer is formed on a laminated ceramic wiring board.

In the above semiconductor chip package,
The forward power supply via and the return power supply via forming the current loop formed on the multilayer ceramic wiring board have a narrow interval of 400 μ, and at least a pair of the forward power supply element and the return power supply element of the package are adjacent to each other. It is characterized in that the narrow interval is 1 mm or less.

In the above semiconductor chip package,
The narrow interval between the forward power supply via and the return power supply via forming the current loop formed on the multilayer ceramic wiring board is 400 μ, and the thin wiring layer or the resin wiring layer formed on the multilayer ceramic wiring board is formed. It is characterized in that both a narrow space in which at least a pair of outward vias and a return via are adjacent to each other and a narrow interval in which at least one forward power supply element and a return power supply element of the package are adjacent to each other are both 1 mm or less. To do.

That is, the third invention comprises one or more of a laminated ceramic wiring board, a laminated ceramic wiring board having a thin film wiring layer formed thereon, or a laminated ceramic wiring board having a resin wiring layer formed thereon. In a package having the semiconductor chip mounted therein, at least one pair of forward power supply vias and return power supply vias forming a current loop, and the forward power supply terminal and the return power supply terminal of the package are adjacent to each other, and they are narrowed. It is characterized in that they are provided at intervals, and due to this effect, the inductance of the via portion can be canceled by the capacitance and reduced. Also,
Due to the configuration provided at a narrow interval, the mutual inductance between adjacent vias increases, and the effective inductance can be reduced. As a result, it is different from the conventional one in that it is possible to supply power to a high-speed, multi-terminal semiconductor chip without generating power supply noise.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings.

[Conceptual diagram of multi-chip package] FIG.
FIG. 3 is a conceptual diagram of a multi-chip package having a novel structure for supplying power to each chip according to the present invention.

FIG. 1A is a plan view of the multichip module, and FIG. 1B is a side sectional view thereof. In the figure, 1 is a laminated ceramic wiring board constituting a power supply layer, 2 is a resin wiring layer forming a signal wiring layer formed on 1, 3 is a semiconductor chip, 4 is a chip power supply terminal and a resin wiring layer surface pad. And conductive balls for connecting electrically and mechanically, and 5 and 6 are pairs of power supply layers provided in the laminated ceramic wiring board 1, 7 and 8.
Is a pair of power supply terminals provided on the bottom surface of the laminated ceramic wiring board 1, and 9 is a sealing case. The sealing case 9 may or may not be provided as needed.

There are three features of this structure, and power is preferably supplied by the shortest path via vias provided vertically downward for each chip. Thereby, the voltage drop can be reduced.
Forming power supply layers in pairs and gradually reducing the inductance of the power supply path. By forming the via and the power supply terminal of the package in a pair, the inductance of the power feeding path can be reduced.
By using ,, the influence of power supply noise can be reduced, and a high-speed and large-scale multi-chip package can be realized.

Various embodiments will be described below.

[Embodiment 1] FIG. 2 shows an enlarged detailed sectional view of Embodiment 1 in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board with a resin wiring layer according to the present invention. In FIG. 2, reference numeral 21 is a laminated ceramic wiring board forming a power supply layer, 22 is a resin wiring layer forming a signal wiring layer formed on the laminated ceramic wiring board 21, and 2 is a resin wiring layer.
3 is a semiconductor chip, 24 (a, b, c, d) is a chip power supply terminal, and 25 (a, b, c, d) is a chip power supply terminal 24.
And conductive pads for electrically and mechanically connecting the surface pad with the resin wiring layer 22, 26 (a, b, c, d) are power supply terminals on the surface of the resin wiring layer 22, and V21 and V22 are laminated ceramics. A power supply layer p21 (a,
b), p22 (c, d), and a pair of power supply terminals T21 (a, b), T22 (c, d) of the multi-chip package are shown respectively. Reference numeral 29 is a chip signal terminal.

The power supply terminals 24 (a, b, c, d) arranged on the surface of the semiconductor chip 23 have conductive balls 25 for connection.
After being connected to the power supply terminal 26 (a, b, c, d) on the surface of the resin wiring layer 22 by (a, b, c, d), it is connected to at least one power supply terminal T21 (a) of the package.

For example, the power supply path of the chip power supply terminal 24a is provided in a via hole 27a in the resin wiring layer 22, which is preferably provided vertically below the power supply terminal 26a on the surface of the resin wiring layer 22 so as to be the shortest path. After being connected, it is connected to the land 28a on the ceramic surface through the via hole 27a, and is provided on the surface of the ceramic wiring board 21 preferably vertically below the land 28a on the surface of the ceramic wiring board so as to have the shortest path. Connected to the via hole v21a in the wiring board, the via hole v21a
Is connected to the power supply layer p21a of the ceramic inner layer via
The power supply terminal T21 of the package, which is preferably provided vertically below the via hole v21a in the laminated ceramic wiring board.
It is connected to a. Hereinafter, the chip power supply terminal 24 (b,
Similar connection paths are taken for c and d).

Further, a forward power supply layer forming a current loop,
For example, P21a and return power supply layer P21b,
Adjacent to each other and at a narrow interval. Preferably, the distance between the forward power supply layer and the return power supply layer may be a narrow distance of 400 μm or less.

Further, the forward power supply terminal T21a and the return power supply terminal T of the laminated ceramic wiring board 21 which is a package.
21b and not only the forward via hole v21a and the return via hole v21b in the ceramic wiring board 21 are adjacent to each other, but also the forward via hole 27a and the return via hole 27b in the resin multilayer wiring layer 22 are adjacent to each other, and They are provided at narrow intervals. Preferably, the distance between the outward via and the return via is set to 1 mm or less.

With this structure, the mutual inductance of the power supply paths cancels out the self-inductance to reduce the effective inductance, and a bypass capacitor is formed, so that simultaneous switching noise is reduced and power supply system noise is eliminated.

When different types of power supply are required, for example, the forward power supply layer P2 in the ceramic substrate 21 is used.
2c and the return power supply layer P22d, the forward power supply terminal T21c and the return power supply terminal T21d of the package, and
Not only the forward via hole v21c and the return via hole v21d in the ceramic wiring board 21 are adjacent to each other,
The forward via hole 27c and the return via hole 27d in the resin multilayer wiring layer 22 and the forward via holes v21c and v21d in the ceramic wiring board 21 are also adjacent to each other in the same manner, so that the mutual inductance of the power supply path cancels the self-inductance. As a result, the effective inductance becomes small and a bypass capacitor is formed, so that simultaneous switching noise can be reduced and power system noise can be eliminated.

Further, a greater effect can be obtained by increasing the number of power supply layers and alternately stacking the forward power supply layers and the return power supply layers. Further, the noise from other power supply layers can be reduced by making the power supply layers forming the power supply loop as narrow as possible and widening the space between the power supply layers.

There are the following three characteristic structures in this embodiment. Power is supplied from the back surface of the ceramic wiring board 21 through the power supply vias and the power supply layer so that the power supply path is as short as possible. In this case, the power supply layer may or may not be connected between the semiconductor chips as appropriate. The power supply layer provided in the laminated ceramic wiring board 21 has p21 (a, b) and p22 (c, d) for the forward path and the return path.
It is made up of a pair at narrow intervals. The vias provided in the laminated ceramic wiring board 21 are constituted by v21 (a, b) and v22 (c, d) in pairs at narrow intervals on the outward path and the return path. In addition, the power supply terminals of the multi-chip package are also T21 on the forward and return paths.
(A, b) and T22 (a, b) are paired at a narrow interval.

The electrical characteristics will be described below.

First, by adopting the above structure, the power feeding path from the power source terminal 26a on the surface of the resin wiring layer to the power source terminal T21a has a shortest path via hole in which the sum of resistance values is almost the minimum. realizable.

With the above structure, the self-inductance between the power supply layers can be reduced due to the effect of increasing the mutual inductance between the power supply layers.

Further, with the above configuration, the self-inductance between the power supply vias can be reduced due to the effect of increasing the mutual inductance between the power supply vias and the power supply terminals.

From the results of ~, the power feeding path can be shortened to about the thickness of the substrate, regardless of the part of the wiring board.
Not only does each power supply layer connected to a large number of power supply terminals on the surface of the semiconductor chip, via holes in the power supply path, resistance including power supply terminals, and self-inductance become almost minimum,
The voltage is substantially uniform, the potentials supplied to the power supply terminals of the semiconductor are substantially uniform, the voltage drop is small, and noise such as simultaneous switching noise due to inductance such as power supply noise can be suppressed, and the influence of the power supply can be significantly reduced.

In this embodiment, one type of power is supplied from the power supply terminals of a plurality of packages through the power supply layers p21a and p21b in the ceramic wiring board 21.
When a sufficient current can be supplied by one power supply terminal or when the power supply system nozzle can be suppressed, power may be supplied from the power supply terminal of one package, and the power supply layer p21 (a, b)
Does not have to be used. Further, although the terminals are expanded on the surface of the resin wiring layer, the surface of the ceramic wiring board, and the power supply layer, the terminals may not be expanded if unnecessary.

In this embodiment, the power supply terminals of the LSI chip and the terminals on the surface of the resin wiring layer are connected by balls.
You may connect with a wire, TAB (Tape Automated Bonding), etc.

[Second Embodiment] Next, a second embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 3 is an enlarged detailed sectional view of a second embodiment in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board with a resin wiring layer.

The basic configuration of FIG. 3 is omitted because it is completely the same as that of FIG. 2, but is characterized by a structure in which wiring is developed in a resin wiring layer. In this figure, the wiring development in this resin wiring layer will be described.

Development wiring A on the surface of the resin wiring layer 222
Is a wiring that connects the power supply terminal pitch of the semiconductor chip 223 and the via hole pitch in the resin wiring layer when the pitch is different. Normally, the semiconductor chip terminal pitch is several hundred μ
m, and the via pitch of the resin wiring layer is several hundred μm.
Therefore, if the pitches of the two are the same, it is possible to arrange the via holes in the resin wiring layer 222 directly below the power supply terminals 24 of the semiconductor chip without using the development wiring A, and to connect them. Preferred (this was described in Example 1 in FIG. 2). However, the via hole pitch of the laminated ceramic wiring board 21 is less than about 1 mm in the current manufacturing technology, which is the limit of high density.
Since the via pitch of 2 is several hundred μm, which is larger than the via pitch, both via hole pitches are matched by the development wiring A provided on the surface of the resin wiring layer or the development wiring B provided on the inner layer.

Next, the electrical characteristics will be described. From the power supply terminal on the surface of the resin wiring layer described above to the power supply terminal T
The power supply path to 221a has a via-hole power supply structure in which the total sum of resistance values is substantially the minimum path. Further, similarly to FIG. 2, the power supply layers p221 (a, b), and
The power supply vias are arranged in pairs at narrow intervals. For this reason,
The power supply path can be shortened to almost the thickness of the substrate without regard to the part of the wiring board, and the resistance and self-inductance including the via holes of each power supply path connected to many power supply terminals on the surface of the semiconductor chip are almost minimum. not only,
The voltage is substantially uniform, the potentials supplied to the power supply terminals of the semiconductor are substantially uniform, the voltage drop is small, and power system noise such as simultaneous switching noise due to the inductance can be suppressed, and the influence of the power supply can be significantly reduced.

[Third Embodiment] Next, a third embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 4 is an enlarged detailed cross-sectional view of a third embodiment in which power is supplied to each chip in a semiconductor multichip package using a laminated ceramic wiring board with a resin wiring layer. The basic configuration of FIG.
Although the description is omitted because it is exactly the same as that in FIG. 3, the structure is characterized in that the wiring is developed on the surface of the ceramic wiring board.
In this figure, the development of wiring on the surface of this ceramic wiring board will be described.

The development wiring C on the surface of the ceramic wiring board 231 has the same purpose as that of the second embodiment shown in FIG. 3 when the pitch of the power supply terminals of the semiconductor chip 223 and the pitch of the via holes in the resin wiring layer are different. It is a wiring that connects both. The rightmost chip shows an example in which it is used together with the development in the resin wiring layer described in the second embodiment. The structure and electrical characteristics are the same as those of the second embodiment shown in FIG.

[Fourth Embodiment] Next, a fourth embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 5 is an enlarged detailed cross-sectional view of a fourth embodiment in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board with a resin wiring layer. The basic configuration in FIG. 5 is omitted because it is completely the same as that in FIG. 2 described above, but is characterized by a structure in which wiring is developed in a resin wiring layer and a ceramic wiring board inner layer. In this figure, the development of wiring on the surface of this ceramic wiring board will be described.

The power supply terminal T241 (a,
The pitch of b) and T242 (c, d) is usually several mm, which is larger than the via hole pitch of the laminated ceramic wiring board 241, so that the power supply layers p241 (a, b) in the laminated ceramic wiring board 241 are large. ), P242 (c,
In the d), the development wiring D and the development wiring E are developed. The structure and electrical characteristics are the same as those of the second embodiment shown in FIG.

[Fifth Embodiment] Next, a fifth embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 6 is an enlarged detailed cross-sectional view of a fifth embodiment in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board with a resin wiring layer. The basic structure of FIG. 6 is omitted because it is completely the same as that of FIG. 2 described above, but is characterized by a structure in which various developing methods are applied in combination. Regarding each structure, Example 2 (straight), Example 3
(Development on resin wiring layer, ceramic substrate surface), Example 4
(Expanded in resin wiring layer, ceramic substrate), the same as described above is used.

The semiconductor chip package made of the laminated ceramic wiring board having the resin wiring layer formed thereon has been described above. However, the semiconductor chip package made of the laminated ceramic wiring board or the laminated ceramic wiring board formed with the thin film wiring layer has been described. Can be similarly applied. These will be described below.

[Sixth Embodiment] Next, a sixth embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 7 is an enlarged detailed cross-sectional view of a sixth embodiment in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board. The basic configuration of FIG. 7 is similar to that of FIG.
Since it is exactly the same as the above, the description thereof is omitted, but an application example to a laminated ceramic wiring board is shown. An example in which various development methods are applied in combination is shown. For each structure,
Since it is similar to the fifth embodiment, the description thereof is omitted.

[Seventh Embodiment] Next, a seventh embodiment of the semiconductor chip package according to the present invention will be described with reference to FIG.
FIG. 8 shows an enlarged detailed cross-sectional view of a seventh embodiment in which power is supplied to each chip in a semiconductor multi-chip package using a laminated ceramic wiring board. The basic configuration of FIG. 8 is the same as that of FIG. 2 and is omitted here, but an example of application to a laminated ceramic wiring board having a thin film wiring layer is shown. In addition,
An example is shown in which various development methods are applied in combination.
Since each structure is similar to that of the first embodiment, the description thereof will be omitted.

[0057]

In a semiconductor chip package using a laminated ceramic wiring board or the like, at least one power feeding path for feeding power to each power supply terminal of the semiconductor chip is a vertical projection surface of the power supply terminal of the mounted semiconductor chip, or ,
From the power supply terminal provided on the back surface of the ceramic wiring board in the immediate vicinity, to the power supply via provided on the inner layer of the ceramic wiring board,
And, if necessary, via the power layer provided in the wiring board,
By adopting a structure in which power is supplied to each semiconductor chip at almost the shortest distance, the power supply path can be shortened to about the thickness of the substrate regardless of the part of the wiring board.

Further, by arranging the power supply layer and the outward and branch paths of the power supply via adjacent to each other in a pair and arranged at intervals, it is possible not only to significantly reduce the execution inductance generated between the power supply layers but also to reduce the capacitance of both. High frequency noise can be reduced by sexual coupling. Therefore, the influence of power supply noise can be significantly reduced.

As a result, since signal distortion can be reduced at high speed and high frequency, it is possible to use a large substrate and increase the number of terminals, and it is possible to realize a large-scale, high-speed semiconductor chip package.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a multi-chip module having a novel structure for supplying power to each chip of the present invention.

FIG. 2 is an enlarged detailed side sectional view of a structure for supplying power to each chip of the present invention in a straight via power supply with a resin wiring layer.

FIG. 3 is an enlarged detailed side cross-sectional view of a structure in which power is supplied to each chip of the present invention: a structure for developing and supplying power with a resin wiring layer with a resin wiring layer.

FIG. 4 is an enlarged side cross-sectional view of a third embodiment of supplying power to each chip of the present invention: a structure for developing and supplying power on the surface of a ceramic wiring board with a resin wiring layer.

FIG. 5 is an enlarged detailed side cross-sectional view of a structure in which power is supplied to each chip of the present invention: a structure is developed in which a resin wiring layer with a resin wiring layer and a ceramic wiring board inner layer are used to supply power.

FIG. 6 is an enlarged detailed side sectional view of a structure for supplying power by combining various development methods with a resin wiring layer according to a fifth embodiment of supplying power to each chip of the present invention.

FIG. 7 is an enlarged detailed side sectional view of a structure for supplying power to a ceramic wiring board according to a sixth embodiment of the present invention.

FIG. 8 is an enlarged detailed side sectional view of a structure for supplying power to each chip of the present invention: a structure for supplying power to a ceramic wiring board with a thin film wiring layer.

FIG. 9 is an enlarged detailed side sectional view of a structure with a resin wiring layer, which is a conventional technique and collectively supplies power of the same type to a plurality of chips.

[Explanation of symbols]

 1,21 Multilayer ceramic wiring board 2,22 Resin wiring layer 3,3 Semiconductor chip 4 Chip conductive balls connected to chip power supply terminals 5,6 Power supply layer pair 7,8 Via pair 9 Encapsulation case

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisashi Tomomi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (9)

[Claims] 1. In a semiconductor chip package comprising a laminated ceramic wiring board, an independent power supply line is provided for each semiconductor chip, and the power supply line is provided at the shortest distance from the back surface of the substrate via a via provided vertically downward. A semiconductor chip package characterized by being pulled out. 2. The semiconductor chip package according to claim 1, wherein a thin wiring layer or a resin wiring layer is formed on the laminated ceramic wiring board. 3. A semiconductor chip package made of a laminated ceramic wiring board, wherein at least a pair of a forward power supply layer and a return power supply layer forming a current loop provided inside each laminated ceramic wiring board are adjacent to each other and at a narrow interval. A semiconductor chip package characterized by being provided. 4. The semiconductor chip package according to claim 3, wherein a thin wiring layer or a resin wiring layer is formed on the laminated ceramic wiring board. 5. The semiconductor chip package according to claim 3, wherein a narrow gap between the forward power supply layer and the return power supply layer forming the current loop is 400 μm or less. 6. A semiconductor chip package comprising a laminated ceramic wiring board, wherein a forward power supply via and a return power supply via forming a current loop in each laminated ceramic wiring board and a wiring layer formed on the wiring board, and A package for a semiconductor chip, characterized in that at least a pair of a forward power supply element and a return power supply element of the package are adjacently provided at a narrow interval. 7. The semiconductor chip package according to claim 6, wherein a thin wiring layer or a resin wiring layer is formed on the laminated ceramic wiring board. 8. The semiconductor chip package according to claim 6, wherein the distance between the forward power supply via and the return power supply via forming the current loop formed on the multilayer ceramic wiring board is 400 μm, and A package for a semiconductor chip, characterized in that at least a pair of a forward power supply element and a return power supply element of the package are adjacent to each other and a narrow interval is 1 mm or less. 9. The semiconductor chip package according to claim 7, wherein a narrow gap between the forward power supply via and the return power supply via forming a current loop formed on the multilayer ceramic wiring board is 400 μm, and A narrow space formed by adjoining at least a pair of forward vias and return vias of a thin wiring layer or a resin wiring layer formed on the multilayer ceramic wiring board, and adjoining at least a pair of forward power supply elements and return power supply elements of the package. The semiconductor chip package is characterized in that the narrow intervals thus formed are both 1 mm or less.