JPH05315347A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To form electrodes of an emitter and a base by forming once a polysilicon film, and to reduce leakage and a hot carrier effect by etching the polysilicon film with an Mo film which is peripherally etched as a mask. CONSTITUTION:An Mo film 113 is formed on a polysilicon film 110, a resist is patterned thereon, peripherally etched, the film 113 of a resist pattern edge is removed, and the film 110 is etched with the film 113 as a mask to form a groove 115. Then, an N-type impurity layer is formed in a bottom of the groove 115, the film 113 on an emitter is removed, the groove 115 is then buried with a CVD insulating film 116, and a boron layer 112 on the emitter electrode polysilicon 110 is removed. Thereafter, an N-type impurity is implanted in the polysilicon 110, and an emitter diffused layer 122 and a base output P<+> type layer 121 are formed by diffusing from the polysilicon film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly to a method of manufacturing a bipolar transistor having a double polysilicon structure.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, (1) JP-A-2-34935, (2)
"Poly Emitter Bipolar hot
carrier effects in an ad
advanced BICMOS technology
y ", IEDM 1987, P182-185, (3).
“BiCMOS process with high reliability”, so
lid / state / technology (solid state technology) / Japanese version / Novemb
er, 1989, P50-56.

6 to 8 are cross-sectional views of manufacturing steps of a conventional double polysilicon type bipolar transistor, which will be described below step by step. (1) As shown in FIG. 6A, here, a state is shown in which field oxidation is completed in order to determine the bipolar transistor formation region. Since the forming method up to this point is generally well known, only the outline will be described in order.

First, a P-type (1
00) After forming the N-type buried layer 602 and the P-type buried layer 601 on the Si substrate 501, the specific resistance is 5 to 10 Ωcm.
An N-type epitaxial layer 603 having a thickness of 1 μm is formed.
After forming the P well 604 on the P type buried layer 601 and the N well 605 on the N type buried layer 602, the collector active region 401 and the base active region 402 are determined by the known Locos technique, and the outside of the region is defined. Then, a field oxide film 608 is formed.

(2) Next, as shown in FIG.
The polysilicon film 502 is made 2000 by the known CVD technique.
Å Generate. (3) Next, as shown in FIG.
Of polysilicon on the polysilicon film 502 and then the base region 610.
Then, the resist 609 is opened. Then, 40 Ke
Ion implantation of boron is performed on the entire surface of the wafer under the conditions of V and 1 × 10 ¹⁵ ions / cm ² (not shown).

(4) Next, as shown in FIG. 6 (D), after removing the resist 609, a new resist 611 is applied on the polysilicon film 502, and a window is opened in the resist 611 in the collector region 612. .. Next, 40 KeV, 2x
Phosphorus is ion-implanted under the condition of 10 ¹⁵ ions / cm ² (not shown). (5) Next, as shown in FIG. 7A, the polysilicon film 502 (not shown) is etched by a known photolithography / etching technique to form a polysilicon film 614 in the base formation region and a collector formation. Polysilicon film 6 in the area
13 is formed.

(6) Next, as shown in FIG. 7B, a resist 615 is applied to the entire surface of the wafer, a window is opened in the resist in the emitter section, and a polysilicon film is formed by a known anisotropic etching technique. 614 is etched to form an emitter formation region 616. (7) Next, as shown in FIG.
After removing 15, the oxide film 617 is formed on the polysilicon film 614 and the emitter forming region 616 by 100 Å by oxidizing in a dry O ₂ atmosphere at 850 ° C. for 10 minutes.

Further, phosphorus and boron are diffused from the polysilicon by this oxidation, and the N ⁺ layer 619 and the P ⁺ layer 6 are formed.
20 are formed simultaneously. (8) Next, as shown in FIG.
Is applied to the entire surface of the wafer, and photolithography is performed so that the emitter formation region 616 is completely opened.
Open the window.

Subsequently, in order to form the main base layer 621, boron is added at 10 KeV, 3 × 10 ¹³ ions / cm.
^After ion-implanting under the condition ² and removing the resist 650, the main base layer 621 is electrically activated.
Annealing is performed at 0 ° C. for 20 minutes under N ₂ . (9) Next, as shown in FIG.
₂ Generates 640 Å membranes.

(10) Next, as shown in FIG.
Using the known anisotropic etching technique, the CVD / Si
The O ₂ film 640 (not shown) is etched to form sidewalls 503 in the emitter formation region 616. At the same time, the oxide film 617 on the main base layer 621 is also removed. (11) Next, as shown in FIG. 8C, after forming a polysilicon film 504 over the entire surface of the 2000Å wafer, 40 Ke
Arsenic is ion-implanted under the conditions of V, 1 × 10 ¹⁶ ions / cm ² (not shown), and a polysilicon film 504 is formed in the emitter formation region 616 (not shown) by using a known photolithography / etching technique. Continuing, 900 ℃ 10
Annealing is performed under the condition of N _{2 for} the polysilicon film 50.
Arsenic is diffused from 4 to form an emitter layer 643.

After that, although the drawing is omitted because it is a known wiring forming technique, after the NSG film 1000Å and the BPSG film 7000Å are formed by the CVD technique, contact photolithography /
Etching is performed to form a contact hole at a predetermined position. Subsequently, after aluminum is vapor-deposited on the entire surface of the wafer, aluminum wiring is formed by the well-known photolithography / etching technique to complete an integrated circuit.

[0012]

However, in the above-mentioned conventional method, the first polysilicon film for forming the base take-out electrode is formed by photolithography / etching, and the second polysilicon film serving as the emitter electrode is formed. Since the film is formed again by photolithography / etching, many polysilicon forming steps are complicated.

FIG. 9 is an enlarged cross-sectional view of the base and emitter portions of a conventional bipolar transistor. The emitter 509 and the polysilicon film 504 shown by A in this figure are shown.
The interface will be damaged by anisotropic etching when the emitter is opened, and damage and defects will remain at this interface. When a reverse potential is applied between the emitter and the base layer when a bipolar transistor is actually formed, according to our experiments, as shown in FIG. 10, the emitter formation portion is opened, so that anisotropic etching of the base electrode polysilicon is performed. The formed bipolar transistor has a larger amount of leak in the reverse direction between the emitter and the base, as compared with the case of performing wet etching (etching solution mainly containing buffer HF).

"Suppression of Hot Carrier Effect by LGE Structure", CAS 91-30, SMD 91-35, IC
According to the documents of D91-39, P17-21, B of FIG.
At the location indicated by, the depletion layer extending from the emitter to the base side is bent near the surface and electric field concentration occurs. As a result, impact ionization occurs and electrons or the like jump into the sidewall 503 in FIG. 9 as hot carriers to create a potential, and the polysilicon film 614, the sidewall 503 and the side base layer 620 in FIG. There is a problem that the reliability of the bipolar transistor is deteriorated because the interface level 510 is generated at the interface.

In the present invention, the number of steps for forming the polysilicon film to be the base, emitter, and collector electrodes described above increases. Since anisotropic etching is used when opening a part of the emitter, damage and defects enter the emitter portion, and after the bipolar transistor is formed, reverse leakage between the emitter and the base increases.

The electric field concentration due to the depletion layer extending from the emitter to the base side causes a hot carrier effect, which causes traps of hot carriers in the sidewalls and generation of an interface state, which causes holes to be formed at the interface during forward operation. The recombination causes an increase in the base current. Accordingly, "increase in the base current" = "h _FE of deterioration (h _FE = I _C
/ I _B) leads to "reverse pulse during circuit operation emitter - when applied between the base, h _FE is changed in use (deterioration), lowering the reliability of the bipolar transistor.

In order to eliminate the above problems, the emitter and base electrodes can be formed by forming the polysilicon film to be the base, emitter, and collector electrodes only once, and at the same time, the emitter and base electrodes can be formed. To eliminate the damage and defects due to anisotropic etching on the emitter portion, and to form the N ⁻ layer around the emitter diffusion layer to alleviate the electric field of the depletion layer extending to the base side, thereby providing the hot carrier effect. It is an object of the present invention to provide a method for manufacturing a bipolar transistor that can reduce the power consumption.

[0018]

In order to achieve the above object, the present invention provides a method of manufacturing a bipolar transistor, wherein a polysilicon film is formed after a base layer is formed, and a P-type impurity is added to the surface of the polysilicon film. Forming a molybdenum (Mo) film on the polysilicon film, patterning a resist on the polysilicon film, opening a resist window in the emitter region, and performing peripheral etching to form a resist pattern edge. Mo
Removing the film by etching, etching the polysilicon film to the surface of the base layer using the Mo film as a mask, and forming a groove to separate the emitter electrode and the base electrode; and the Mo film and the polysilicon film. Forming an N-type impurity layer at the bottom of the groove by ion implantation using the mask as a mask, removing the Mo film on the emitter by etching and removing the resist, and forming a CVD insulating film over the entire surface of the wafer, and then forming an upper surface of the emitter electrode. Etching back until the appearance of the trench, the step of filling the inside of the trench with the CVD insulating film, the step of etching away the boron layer on the emitter electrode polysilicon film, and the step of removing N-type impurities at least in the emitter electrode polysilicon film. forming an emitter diffusion layer and the base contact P ⁺ layer on the diffusion from the polysilicon And forming Te is obtained as applied sequentially.

Further, as an insulating film filling the space between the base electrode polysilicon and the emitter electrode polysilicon, CVD is used.
-It uses SiO ₂ or PSG.

[0020]

According to the present invention, since it is configured as described above,
The base electrode polysilicon film and the emitter electrode polysilicon film can be formed by one-time polysilicon formation and etching (peripheral etching), and the number of steps can be significantly reduced compared to the conventional case.

Further, since anisotropic etching at the time of partial opening of the emitter for forming the emitter electrode polysilicon is eliminated, etching damage and defects are eliminated, and a bipolar transistor with less leakage can be formed (FIG. 4). reference). Further, the depletion layer extending from the emitter to the base is relaxed by the guard ring N ⁻ layer formed around the emitter diffusion layer to reduce the hot carrier effect, so that a highly reliable bipolar transistor can be obtained.

[0022]

EXAMPLES Now, an outline of peripheral etching will be described before starting the description of the examples. FIG. 11 is a schematic diagram of peripheral etching. As shown in this figure, Si
After forming the Mo film 3 as an etching material on the substrate 1, the polysilicon film, the Si ₃ N ₄ film 2, etc., the resist 5 is formed.
Patterning and reactive ion etching with a mixed gas of CCl ₄ and O ₂ results in an O ₂ concentration of 60%
At 70%, Mo film (M
The same applies to oSi ₂ ) 3 is selectively etched. The reason is that the O ₂ concentration is different between the resist pattern edge and other portions, and the O ₂ concentration is 50% or less at the resist pattern edge, so the Mo film (the same applies to the MoSi ₂ film) 3 is etched, and 60 of the part
This is because when the O ₂ concentration is 70%, the oxide 4 is formed on the Mo film 3 and etching is completely stopped.

The details of this peripheral etching are described in "Special Issue RIE Si RIE and Peripheral Etching", Semiconductor World, 1983.10.
P. 49-54. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 5 are sectional views of a bipolar transistor manufacturing process showing a first embodiment of the present invention, which will be described in order below.

(1) First, FIG. 1A shows a state in which a base / emitter formation region 001 and a collector formation region 002 are completed for forming a bipolar transistor (Bip Tr.). The forming method up to this point is that the base layer 200 is formed in the base-emitter forming region 001 and the collector sink 109 is formed in the collector forming region 002 in addition to the conventional forming method of FIG. ..

Reference numeral 101 is a P-type (100) Si substrate (specific resistance 10 to 20 Ωcm), 102 is an N-type buried layer, 103 is a P-type buried layer, and 104 is an epitaxial layer (N-type, specific resistance 5 to 10 Ωcm). , 105 is a P-type isolation layer, 106 is an N well layer, 107 is a field oxide film,
108 is an oxide film, 109 is a collector sink, 200 is a main base layer, the junction depth (Xjb) is 0.20 μm, and the sheet resistance is 2.0 kΩ / □. The main base layer 200 contains boron at 10 keV and 2 × 10 ¹³ ions / c.
After forming by ion implantation under the condition of m ² , it is formed by heat treatment at 1000 ° C. for 15 seconds using RTA (rapid thermal annealing) technique.

(2) Next, as shown in FIG. 1 (B), the oxide film 108 (see FIG. 1 (A)) formed on the semiconductor substrate (hereinafter referred to as a wafer) is changed to 1% HF. After removing by etching, a polysilicon film 110 is formed on the 3000 Å wafer. Subsequently, ion implantation 111 is performed with boron under the conditions of 30 keV and 5 × 10 ¹⁵ ions / cm ² .

(3) Next, as shown in FIG. 1 (C), a Mo film 113 is formed on the polysilicon film 110 on which the boron layer 112 has been formed to 1500 Å. After that, a resist film 114 is formed on the entire surface of the wafer, and the emitter and collector parts are opened. The resist opening size of the emitter is a photolithographic limit size, and in this case, the opening size is 1 μm.

(4) Next, as shown in FIG.
Using the peripheral etching method, CCl ₄ + O ₂ (7
0%) mixed gas is used for etching, and the resist film 1
The Mo films 113 around the 14 pattern edges are removed by etching by 0.2 μm from the resist pattern edges (not shown). Next, the resist film 114 and the Mo film 11
The polysilicon film 110 is etched by an anisotropic etching method using CF ₄ gas with 3 as an etching mask to form a groove 115.

(5) Next, as shown in FIG. 2 (B), CCl ₄ + O ₂ (50% or less) is formed by a reactive etching apparatus.
Gas other than the base extraction electrode 003 is used.
The film 113 is removed by etching (not shown), and then the resist film 114 [see FIG. 2 (B)] is removed. (6) Next, as shown in FIG. 2 (C), 10 keV,
Phosphorus is ion-implanted under the condition of 1 × 10 ¹² ions / cm ² to form the guard ring N layer 201.

(7) Next, as shown in FIG.
After forming the CVD / SiO ₂ film on the wafer by about 6000Å, etch back (entire surface etching) is performed by the anisotropic etching technique, and the CVD / SiO ₂ film 1 is formed in the groove 115.
16 to 2000 Å. (8) Next, as shown in FIG. 3B, the polysilicon film 110 without the Mo film 113 is removed by 1000 Å etching with CF ₄ gas using an anisotropic etching technique. At this time, the boron layer 112 near the surface of the polysilicon film 110 formed earlier is simultaneously removed, and the polysilicon film 110 without the Mo film 113 becomes a non-doped polysilicon film. In addition, the surface of the Mo film 113 reacts with the etching material by the action of excess O ₂ in the gas (CCl ₄ + O ₂ ) of the peripheral etching previously performed, and Mo
Poly-etching (CF
Not etched in ₄ ).

(9) Next, as shown in FIG. 3C, As (arsenic) is applied to the entire surface of the wafer at 20 keV and 2 × 10 ¹⁶ io.
Ion implantation is performed under the condition of ns / cm ² . A at this time
The energy at the time of ion implantation of s is performed under the low energy condition as described above so as not to penetrate the Mo film 113. (10) Next, as shown in FIG.
After applying 05 to the entire surface of the wafer, the emitter polysilicon layer 1
Photolithography is performed so as to form a resist on 10 and on the collector polysilicon layer 206. Next, the polysilicon film is removed by etching with CF ₄ gas. At this time, since an oxide is formed on the surface of the base polysilicon layer 207, it is not removed by the polysilicon etching using CF ₄ .

(11) Next, as shown in FIG. 4B, reactive ion etching is performed under the conditions of CCl ₄ + O ₂ (50% or less) to remove the Mo film 113 by etching. (12) Next, as shown in FIG. 5 (A), the NSG film 1
19 for 1000Å and BPSG film 120 for 8000ÅC
Grow by VD method. Subsequently, for the purpose of flattening the surface of the BPSG film 120, a flow is performed at 950 ° C. for 5 minutes under N ₂ condition. By the heat treatment at this time, the emitter layer 12
2. The collector layer 124 and the base extraction layer 121 are formed by diffusion of polysilicon.

(13) Next, as shown in FIG.
After opening the contact hole by using the known photolithography / etching method, the aluminum wiring 12 is formed by using the known wiring forming technique.
3 is formed. Next, a second embodiment of the present invention will be described in detail with reference to the drawings. 12 to 14 are sectional views of the bipolar transistor manufacturing process showing the second embodiment of the present invention, which will be described in order below. The same parts as those in FIGS. 1 to 4 are designated by the same reference numerals and the description thereof will be omitted.

(1) First, FIG. 1 (A) to FIG. 2 described above.
The step (B) is performed. Then, as shown in FIG. 12 (A), a PSG film is formed on the wafer at about 6000Å and then etched back (entire surface etching) by an anisotropic etching technique.
Then, a PSG film 301 of 2000 Å is formed in the groove 115. (2) Next, as shown in FIG.
As in the case of (B), using an anisotropic etching technique, CF ₄
The polysilicon film 110 without the Mo film 113 is removed by 1000 Å etching with the above gas. At this time, the boron layer 112 near the surface of the polysilicon film 110 formed earlier is simultaneously removed, and the polysilicon film 110 without the Mo film 113 is removed.
Is a non-doped polysilicon film. Also, the Mo film 1
The surface of 13 reacts with the etching material by the action of excess O ₂ in the gas (CCl ₄ + O ₂ ) of the peripheral etching previously performed, and forms an oxide on the surface of the Mo film, so that poly etching (CF ₄ ) Is not etched.

(3) Next, as shown in FIG.
As in the case of FIG. 3C described above, ion implantation of As (arsenic) is performed on the entire surface of the wafer under the conditions of ²⁰ keV and 2 × 10 ¹⁶ ions / cm ² . At this time, the energy at the ion implantation of As is performed under the low energy condition as described above so as not to penetrate the Mo film 113. (4) Next, as shown in FIG.
Similar to (A), after applying the resist film 205 on the entire surface of the wafer, photolithography is performed so as to form a resist on the emitter polysilicon layer 110 and the collector polysilicon layer 206. Next, the polysilicon film is removed by etching with CF ₄ gas. At this time, since an oxide is formed on the surface of the base polysilicon layer 207, it is not removed by the polysilicon etching using CF ₄ .

(5) Next, as shown in FIG. 13 (B), as in the case of FIG. 4 (B) described above, CCl ₄ + O ₂ (5
Reactive etching is performed under the condition of 0% or less) Mo film 1
13 is removed by etching. (6) Next, as shown in FIG. 14 (A), the NSG film 119 is set to 1000 Å and B as in FIG. 5 (A) described above.
The PSG film 120 is grown by 8000Å by the CVD method. Then, reflow is performed at 950 ° C. for 5 minutes under N ₂ conditions for the purpose of flattening the surface of the BPSG film 120. By this reflow, the emitter layer 122, the collector layer 124,
The base extraction layer 121 is formed by diffusion from polysilicon. In addition, P by the same heat treatment (reflow)
The N ⁻ guard ring layer 201 is formed by solid layer diffusion from the SG film 301.

(7) Next, as shown in FIG.
As in the case of FIG. 5B described above, after the contact hole is opened by using the known photolithography / etching method, the aluminum wiring 123 is formed by using the known wiring forming technique to complete the formation of the integrated circuit. The present invention is not limited to the above embodiment,
Various modifications are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0038]

As described above in detail, according to the present invention, (1) the base electrode polysilicon film and the emitter electrode polysilicon film are formed once by polysilicon formation and etching (peripheral etching). Since it is formed by, it is possible to significantly reduce the number of steps as compared with the conventional method.

(2) Since anisotropic etching at the time of partial opening of the emitter for forming the polysilicon film for the emitter electrode is eliminated, etching damage and defects are eliminated, and a bipolar transistor with less leakage can be formed ( (See FIG. 4). (3) Since the depletion layer extending from the emitter to the base is relaxed by the guard ring N ⁻ layer formed around the emitter diffusion layer to reduce the hot carrier effect, a highly reliable bipolar transistor can be obtained.

[Brief description of drawings]

FIG. 1 is a manufacturing process sectional view (1) of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process sectional view (2) of the bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process sectional view (3) of the bipolar transistor according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process sectional view (4) of the bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process sectional view (5) of the bipolar transistor according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process sectional view (1) of a conventional double polysilicon bipolar transistor.

FIG. 7 is a manufacturing process sectional view (2) of a conventional double polysilicon bipolar transistor.

FIG. 8 is a manufacturing process sectional view (3) of a conventional double polysilicon bipolar transistor.

FIG. 9 is an enlarged cross-sectional view of a base and an emitter of a conventional polysilicon bipolar transistor.

FIG. 10 is an emitter-base leakage characteristic diagram of a conventional polysilicon bipolar transistor.

FIG. 11 is a schematic cross-sectional view of peripheral etching.

FIG. 12 is a manufacturing process sectional view (1) of a bipolar transistor according to a second embodiment of the present invention.

FIG. 13 is a manufacturing process sectional view (No. 2) of the bipolar transistor according to the second embodiment of the present invention.

FIG. 14 is a manufacturing process sectional view (3) of the bipolar transistor according to the second embodiment of the present invention.

[Explanation of symbols]

001 Base / emitter formation region 002 Collector formation region 003 Base extraction electrode 101 P-type (100) Si substrate 102 N-type buried layer 103 P-type buried layer 104 Epitaxial layer 105 P-type isolation layer 106 N-well layer 107 Field oxide film 108 Oxidation Film 109 Collector sink 110 Polysilicon film (emitter polysilicon layer) 111 Ion implantation (Br) 112 Boron layer 113 Molybdenum (Mo) film 114,205 Resist film 115 Groove 116 CVD / SiO ₂ film 117 Ion implantation (As) 119 NSG Film 120 BPSG film 121 Base extraction layer 122 Emitter layer 123 Aluminum wiring 124 Collector layer 200 Base layer 201 Guard ring N layer 206 Collector polysilicon layer 207 Base polysilicon Layer 301 PSG film

Claims (3)

[Claims] 1. A step of: (a) forming a polysilicon film after forming a base layer, and forming a P-type impurity near the surface of the polysilicon film; and (b) forming a Mo film on the polysilicon film. And patterning a resist thereon to open a resist window in the emitter region, and (c) performing peripheral etching to remove the Mo film at the edge of the resist pattern by etching, and using the Mo film as a mask to form the polysilicon film. Etching the film to the surface of the base layer to form a groove, thereby separating the emitter electrode and the base electrode; (d) using the Mo film and the polysilicon film as a mask to form an N-type impurity layer into the groove A step of forming at the bottom, (e) a step of removing the Mo film on the emitter by etching and then removing the resist, and (f) a CVD step. After the film is formed on the entire surface of the wafer, etching back is performed until the upper surface of the emitter electrode appears, and the inside of the groove is filled with the CVD insulating film, and (g) a step of etching away the boron layer on the polysilicon film of the emitter electrode. And (h) a step of forming an N-type impurity in at least the emitter electrode polysilicon film, and (i) a step of forming an emitter diffusion layer and a base extraction P ⁺ layer by diffusion from the polysilicon film. A method of manufacturing a bipolar transistor, which is characterized by the above. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein the CVD insulating film is a CVD silicon oxide film. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein the CVD insulating film is a CVD / PSG film.