JPH05312917A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform the functional test of each functional block in a short time in a semiconductor integrated circuit containing one or more functional blocks. CONSTITUTION:An individual functional block is constituted of a ROM 12, which stores test input patterns for testing the validity of the own functions, a ROM 13, which stores test expected-value patterns, a ROM-address generating circuit 15, which imparts address signals 112 to two ROMs, and a comparator circuit 14, wherein the test-expected-value pattern 104 is collated with a test- output pattern 105 outputted from a function circuit 11 when a test-input pattern 108 is inputted into the function circuit 11. Therefore, the tests of all functional blocks can be performed at the same time. When an error is detected in any functional block, the test is immediately finished. Therefore, the number of the test patterns can be decreased to a large extent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit structure for efficiently performing a functional test of a semiconductor integrated circuit including at least one functional block.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuit technology has been remarkable, and the scale-up and integration of semiconductor integrated circuits have been accelerated. Along with this, efficient functional test of semiconductor integrated circuits and detection of defects at a high rate are one of the factors that determine the cost and reliability of products. Further, as the scale of semiconductor integrated circuits increases and the progress of compounding progresses, the difficulty level of failure analysis is increasing.

A circuit division method is often used as a method for efficiently performing this functional test, detecting defects at a high rate, and easily performing defect analysis. This circuit division method divides a RAM (random access memory) or a ROM (read only memory) mounted on a large-scale circuit or a set of circuits having a certain function into functional blocks, In addition to the test of the entire function, the function test of each function block is performed.

In order to perform a functional test for each functional block using the circuit division method, a normal signal (an input / output signal when operating normally) and a test signal (for a functional block test when testing a functional block) are used. I / O signals) can be input and output directly from external terminals. However, considering the chip size, the number of pins in the package, the size, etc., one external terminal is shared by the test signals of multiple functional blocks. It has a structure as shown in FIG.

Next, a specific example of the circuit division method will be described with reference to FIG. In the block diagram of the semiconductor integrated circuit shown in FIG. 2, the functional block test input terminal (not shown) and the functional block test output terminal (not shown) are shared by the functional blocks. In the circuit configuration of the conventional example shown in FIG. 2, the functional circuit 122B and the selector circuit 1
22A functional block 122 and functional circuit 123B
And a functional block 123 including a selector circuit 123A
And a functional block 124 including the functional circuit 124B and the selector circuit 124A, and a functional block 125 including the functional circuit 125B and the selector circuit 125A.

In normal operation, the function block 122, the function block 123, and the function block 122 correspond to the input signal 101.
Input signals 128 and 1 are input to the function block 124 and the function block 125 by the internal bus 301, respectively.
29, 130, and 131 are input, and the output of each functional block is sent through the internal bus 301 to the output signal 13
It is output as 6. Further, at the time of testing each functional block, the input signal 126 for functional block test is input by the input selection circuit 120 and the input signal 127 for functional block test is sent to each functional block 122, 123, 124, 1
Distribute to 25. Here, the input selection circuit 120 outputs the functional block test input signal 127 only to the functional block to be tested.

On the other hand, the output signals 132, 133, 134 and 135 of the respective functional blocks at the time of the functional block test are input to the output selection circuit 121. The output selection circuit 121 selects the output of the functional block to be tested and outputs it as a functional block test output signal 137 to the outside. further,
There is also a method of sharing an input terminal and an output terminal for normal use with a test input terminal and an output terminal used for a test, but the description thereof is omitted here.

Next, a method for testing the semiconductor integrated circuit having the configuration of the conventional example shown in FIG. 2 will be described. First, a test of the entire semiconductor integrated circuit is performed using normal input signal and output signal terminals. In that case, the test is generally a test that can test the function of the entire semiconductor integrated circuit, and is not a test that can test the detailed function of each functional block. Tests such as connection between individual functional blocks and external interface are mainly performed. Next, after a functional test of the entire semiconductor integrated circuit, a detailed test of each functional block is performed. A detailed test of each functional block is performed by directly inputting a signal to each functional block from the outside and determining the input signal of each functional block by the outside.

[0009]

As described above, the conventional semiconductor integrated circuit is constructed on the basis of the idea that the normally used state and the state at the time of test are separated, and detailed test of each functional block is performed. The configuration is such that one external terminal is commonly used by a normal signal and a test signal of a plurality of functional blocks. Therefore, since a plurality of functional blocks cannot be tested simultaneously and must be performed individually, a circuit including a plurality of functional blocks has a large number of test patterns, resulting in a long test time and thus a decrease in test efficiency. It has a drawback.

[0010]

A feature of the present invention is that it includes at least one functional block, each functional block stores a test input pattern for testing its own function, and a test expected value pattern. R to remember
An OM, a ROM address generation circuit for giving an address to the two ROMs, and a comparator circuit for collating the test output pattern output from the functional circuit with the test expected value pattern when the test input pattern is input to the functional circuit. Especially.

An object of the present invention is to provide a semiconductor integrated circuit including one or more functional blocks capable of efficiently performing a functional test of each functional block in a short time by eliminating the above-mentioned drawbacks. To provide.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a circuit of an embodiment of the present invention.

The functional block 1 as shown in FIG.
A functional circuit 11, a ROM 12 that stores a test input pattern for testing the functional circuit 11, a ROM 13 that stores a test expected value pattern, and a ROM 12
And a ROM address generation circuit 15 for giving an address signal 108 to the ROM 13, a test output pattern 105 output from the functional circuit 11 when the test input pattern 103 is input to the functional circuit 11, and a test expected value pattern 104 output from the ROM 13. It is constituted by a comparator 14 for collating. Here, when the semiconductor integrated circuit includes N functional circuits, the functional block 2,
, ..., N have the same configuration as the functional block 1.

An input signal TEST107 is used to switch between the normal use of the semiconductor integrated circuit and the test of each functional block. In order to simplify the description here, the input signal TEST107 is used as a TEST signal, the semiconductor integrated circuit is normally used when the TEST signal 107 = "1", and the functional circuit is tested when the TEST signal 107 = "0". I shall.

When the semiconductor integrated circuit is normally used, the TEST signal 107 is "1" and the input signal 101
Is input to the functional circuit 11 of the functional block 1 via the internal bus 120 as the input signal 102, and the output signal 105 of the functional block is output to the internal bus 120 as the output signal 106. In the test of the functional block, the TEST signal 107 = "0" causes the ROM address generation circuit 15 to send an address signal to the ROM 12 and the ROM 13 from the designated address. The test expected value pattern 104 is output to. Comparator 14
Compares the test output pattern 105 of the functional circuit 11 with the test expected value pattern 104, and determines an error determination signal 109 (hereinafter referred to as an ERR signal) and a test pattern end signal 110 (hereinafter referred to as an END signal). Is output. To simplify the explanation here, if an error occurs in the functional test, the ERR signal 109 is set to "1", and when the functional circuit test pattern ends, the END signal 1 is output.
Each of the functional blocks 1, 2, ..., N outputs 10 = “1”.

The logic circuit 16 comprises all functional blocks 1, 2,
..., N is the logical sum of the ERR signals 109 output from N
As the ROR signal 111, the logical product of the END signal 110 output from all the functional blocks and the logical sum of the ERROR signal 111 are output as the TC signal 112. The test of all functional blocks ends with the TC signal 112 = “1”. If an error occurs in any of the functional circuits, the ERROR signal 111 = "1" is output and the process ends.

Here, in the test of the functional circuits, the test of all the functional circuits is simultaneously started by inputting the TEST signal 107 = "0" to all the functional blocks 1, 2, ... The test is performed until the test of the most functional circuit ends (the test of all the functional circuits ends) or an error occurs in any of the functional circuits.

[0018]

As described above, in the semiconductor integrated circuit of the present invention, the test of each functional circuit is switched between the case where the semiconductor integrated circuit is normally used for the external terminal and the case where each functional circuit is tested. TEST signal 1 for
07 and the addition of the ERROR signal 111 for notifying the error judgment of all the functional blocks 1, 2, ..., N and the TC signal 112 for notifying the test of all the functional circuits, the number of terminals of the semiconductor integrated circuit can be greatly increased. Can be reduced to If there are a plurality of functional circuits, the TEST signal 10
By inputting 7 to the test circuits of all functional circuits in common and starting the test of all functional circuits at the same time, if there is no error in all functional circuits, the test time determined by the number of patterns of the functional circuit with the largest number of patterns. If all functional circuits can be tested with and an error is detected in any of the functional circuits,
Since the error signal is output and the test ends immediately,
This has the effect of significantly reducing the time for passing the test pattern and increasing the efficiency of the test.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1,2, N Functional block 11 Functional circuit 12,13 ROM 14 Comparator 15 ROM address generation circuit 101 Input signal 101,102 Input signal 103 Test input pattern 104 Test expected value pattern 105 Test output pattern 106 Output signal 107 TEST signal 108 ROM Address signal 109 ERR signal 110 END signal

Claims (1)

[Claims] 1. A ROM including at least one functional block, each functional block storing a test input pattern for testing its own function, a ROM storing a test expected value pattern, and the two ROMs. A semiconductor integrated circuit characterized by including a ROM address generating circuit for giving an address to the test circuit and a comparator circuit for collating the test output pattern output from the functional circuit with the test expected value pattern when the test input pattern is input to the functional circuit. circuit.