JPH05307516A - Data transfer controller and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of resources for the transfer control of a register, etc., for designating a transfer origin and a transfer destination. CONSTITUTION:To resources (transfer destination/transfer origin designation address registers MARA, MARB, transfer counter constitution registers ETCRA, ETCRB, and control registers DTCRA, DTCRB) by one channel in the case of executing a data transfer between memories minimum resources (I/O address registers IOARA, IOARB) are added and as for a data transfer channel actuated by an interruption requested by an input/output circuit, as well it can be used as a 2-channel portion. Whether the resources are utilized by one channel or two channels is determined by the value of bits TRSA1, TRSA2. The respective MARA, MARB have the number of bits corresponding to an address space and the IOARA and the IOARB have the number of bits being smaller than the number of bits corresponding to the address space.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and, for example, to a technique effective when used in a single-chip microcomputer incorporating the data transfer control device.

[0002]

2. Description of the Related Art Single-chip microcomputers, as described in "LSI Handbook" P540 and P541 issued by Ohmsha, Ltd. on November 30, 1984, have a central processing unit (CPU) as a center for holding programs. Functional blocks such as a ROM (read only memory), a data holding RAM (random access memory), and an input / output circuit for inputting / outputting data are formed on one semiconductor substrate. The present inventors have considered incorporating a direct memory access controller (DMAC) that transfers data independently of the CPU in such a single-chip microcomputer.
As an example of a document describing such a DMAC, "Hitachi 16-bit Microprocessor HD641016" P169 to P, published by Hitachi, Ltd. in September 1987
There is 206.

Such a DMAC transfers data between memories by activation by CPU software or activation by an external terminal, and also by a timer or serial communication interface (SCI).
It can also be activated by an interrupt requested by an input / output circuit such as. Further, the DMAC incorporates two address registers (designating a transfer source address and a transfer destination address) for performing data transfer between memories, for example, for four channels. The address register has a bit number corresponding to the address space of the microcomputer, for example, 2 if the address space is 16 Mbytes.
It has 4 bits.

[0004]

However, the studies by the present inventors have revealed that the DMAC has the following problems. That is, first, when the data transfer between the memories is performed by the activation by the software of the CPU or the activation by the external terminal, the address register is set so that the source and destination addresses can be arbitrarily selected. The number of bits corresponding to the address space, for example, 24 bits are required when the address space is 16 Mbytes.
When C is activated, one of the data transfers is mostly one of the input / output circuits, and the address area of such an input / output circuit is often smaller than the address space. , A continuous area such as 256 bytes. Therefore, in the case of data transfer between the memory and the input / output circuit, the upper bit of one address that specifies the data transfer source or the data transfer destination is always the same, and the upper bit of the address register is It is in vain.

Secondly, a large number of factors are required to activate the DMAC by an interrupt in accordance with the interrupt factors of the input / output circuit. For example, when the DMAC is activated by the SCI transmission completion interrupt and continuous transmission is performed without CPU software intervention, the transfer destination address is the SCI output data register and the transfer source is the CPU.
Is prepared in advance by the software of, for example, the address of RAM. If two channels of SCI are built-in, if continuous transmission / reception is performed for each channel, all four channels of the DMAC are required, and data transfer by a timer interrupt or CPU It becomes impossible to transfer data by software / external pin.

Thirdly, only one channel can be transferred due to one interrupt factor. Therefore, for example, it is impossible to change the output value of data and the set time of the next timer interrupt at the same time by the interrupt of the timer, and any change must be made by the CPU.

Fourth, the transfer source / transfer destination address is incremented / decremented or fixed, and in the case of being fixed, a read or write is performed with respect to an address of 1 byte or 1 word which is a DMAC data transfer unit. It will be. Therefore, repeated data transfer cannot be performed for any data block.

An object of the present invention is to provide a data transfer control device capable of improving the utilization efficiency of resources for transfer control such as a register designating a transfer source and a transfer destination. Another object of the present invention is to provide a data transfer control device capable of controlling data transfer by a large number of interrupt factors. Another object of the present invention is to provide a data transfer control device capable of repeatedly carrying out data transfer to an arbitrary data block of a data unit or more.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the minimum resources are added to the resources for one channel when data is transferred between memories, and there are two data transfer channels that are activated by an interrupt requested by the input / output circuit. Enable as minutes. At this time, in each of the two data transfer channels for two channels which are also activated by the interrupt of the input / output circuit, the register for specifying the input / output circuit as the transfer source / transfer destination has less bits than the number of bits corresponding to the address space. Made to have a number.

The transfer counter of one data transfer channel of the two data transfer channels, which is also activated by the interrupt requested by the input / output circuit, is used as the transfer counter of the data block, and the transfer counter of the other data transfer channel is used of the data block. It is used as a transfer counter to realize data block transfer between memories.

In a data transfer mode using a data transfer channel that is activated by an interrupt requested by the input / output circuit, a transfer counter, a counter for counting the number of transfers, and means for designating the number of transfers age,
As a unit operation, the data transfer operation of performing the specified number of times of data transfer by using the counting operation of the transfer counter and the memory address register is performed as a unit operation. A repeat transfer mode is realized in which the value is returned to the set value and the unit operation is repeated a plurality of times.

Holding means for holding an activation factor given by an external single signal for instructing activation of a data transfer channel that is activated by an interrupt requested by the input / output circuit is provided, and the single signal is provided. By holding the activation factor given by the holding means,
A multi-transfer mode is realized in which a plurality of data transfers are performed via the plurality of data transfer channels according to a single activation factor.

[0015]

According to the above means, the minimum resource is added to the resources for one channel when data is transferred between memories, and the data transfer channel is activated by the interrupt requested by the input / output circuit. The data transfer control device that can be used for two channels as the above improves the utilization efficiency of the resources for transfer control such as the register that specifies the transfer source and the transfer destination, and facilitates the handling of many interrupt factors. To do. The data block transfer between the memories and the repeat transfer mode or the multi-transfer mode between the memory and the input / output circuit broadens the application range of the data transfer control device.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a single chip microcomputer incorporating a data transfer control device according to the present invention.

The single chip microcomputer 100 shown in the figure is not particularly limited, but is a DMA which is an embodiment of the data transfer control device according to the present invention.
C1, CPU (Central Processing Unit) 2, which controls overall control, bus controller 3, ROM 4, RAM 5, timer 6, S
It is composed of functional blocks such as CI 7, pulse output device (PSO) 8 and input / output ports (IOP) 91 to 97, and is formed on one semiconductor substrate by a known semiconductor manufacturing technique. The functional blocks of such a single-chip microcomputer are mutually connected by an internal bus 69 including address, data, read signal, write signal, system clock and the like. CPU2
The DMAC 1 is an internal bus 69 via the bus controller 3.
It is connected to the. Either the CPU 2 or the DMAC 1 performs the read and write operations in the bus cycle. The bus controller 3 has an arbitration function for this purpose. The timer 6 is composed of a timer A, a timer B, a timer C, and a timer D, although not particularly limited, and the SCI 7 is composed of SCIA and SCIB, although not particularly limited. The single chip microcomputer 100 is a clock pulse generator C
The operation is performed in synchronization with a crystal oscillator connected to the terminals XTAL and EXTAL of PG or a reference clock generated based on an external clock input from the outside. The minimum unit of this reference clock is called a state. In the figure, Vss and Vcc are power supply terminals.

Although not particularly limited, the address space of the CPU 2 is 16 Mbytes and the address bus is 24
Is a bit. ROM3, RAM4, and DMAC
1, the timer 5, the SCI 6, the pulse output device 8, the input / output ports 91 to 97, etc. are registers of the CPU.
It is arranged in two address spaces. An operation mode of the single-chip microcomputer is selected by a mode signal (not shown), and a part of the input / output port can be used as an address bus, a data bus and a control signal to expand the external bus. The other input / output ports are also used as the input / output terminals of the timer 6, SCI7 and DMAC1, and the terminal functions are switched by software. ..

The DMAC 1 controls data transfer between the memory and the memory or between the memory and the input / output circuit, although not particularly limited, based on the activation factor, the transfer address, the number of transfer data, etc. designated by the CPU 2. .. The memories at this time are the ROM4 and the RAM.
5, a memory external to the single chip computer (not shown) is also included. Although the input / output circuit is not particularly limited, it is a built-in register such as the timer 5, the SCI 6, the pulse output device 8, and the input / output ports 91 to 97.

FIG. 2 shows a block diagram of an embodiment of the DMAC 1.

The DMAC 1 is used as a total of 2 channels of channels A and B when data is transferred from the memory-input / output circuit, and is used as 1 channel when data is transferred from memory to memory. Channel A is a 24-bit memory address register MARA
(MARA-L, MARA-H, MARA-E), 8-bit I / O address register IOARA, 8-bit execution transfer count register ETCRA, 8-bit transfer count register TCRA, 8-bit control register D
Includes TCRA. Channel B is a 24-bit memory address register MARB (MARB-L, MARB-
H, MARB-E), 8-bit I / O address register IOARB, 8-bit execution transfer count register E
TCRB, 8-bit transfer count register TCRB,
It includes an 8-bit control register DTCRB. A 24-bit arithmetic logic unit ALU common to these two channels
(ALU-L, ALU-H, ALU-E), address buffer AB (AB-L, AB-H, AB-E), data buffer DB (DB-L, DB-H), memory interface MIF (MIF- L, MIF-H, MIF-E,
MIF-C), and a control unit CONT. The control unit CONT operates based on the contents of the control registers DTCRA and DTCRB and the activation factor given from the outside of the DMAC1 to control each unit of the DMAC1. The memory address registers MARA and MARB are generically referred to, or one of them is also referred to as a memory address register MAR. Similarly, I / O address register I
OARA and IOARB are simply I / O address registers I
OAR and execution transfer count registers ETCRA, ET
CRB simply executes transfer count register ETCR, transfer count registers TCRA, TCRB simply transfer count register TCR, and control register DTCR
A and DTCRB are also simply referred to as a control register DTCR.

Each of the above registers, arithmetic logic unit ALU,
The memory interface MIF is connected via the A bus, the B bus, etc. as the DMAC internal bus. Further, bits 23 to 0 of the A bus are connected to the address buffer AB. Address buffers AB-L, AB-H, A
B-E are connected to a 24-bit address bus included in the internal bus 69. Data buffer DB-L, DB-H
Is connected to a 16-bit data bus included in internal bus 69.

Each register outputs data to the A bus, and the data is stored in the address buffer AB and the arithmetic logic unit A.
Converted to LU or memory interface MIF. Arithmetic and logic unit ALU, memory interface MIF is B
Data is output to the bus, and the data can be transferred to each register. The data written by the CPU 2 is made writable in each register via the internal data bus included in the bus 69, the memory interface MIF, and the B bus. The data to be read by the CPU 2 is read by the CPU 2 via the A bus, the memory interface MIF, and the internal data bus included in the bus 69 of the single-chip microcomputer 100. Further, the transfer count register TCR can output data to the C bus, and the transfer count register ETCR
And the lower 8 bits of the arithmetic and logic unit ALU (ALU-L)
Can be transferred to. The arithmetic logic unit ALU is A
It is possible to operate the input of the bus and the C bus or a constant value. In FIG. 2, SFT is a shifter and SEL
Is a selector.

In FIG. 3, the register configuration of the DMAC 1 is shown separately for channel A and channel B.

As described above, the 24-bit memory address register MAR and the 8-bit I / O address register I
It has two OARs, two execution transfer count registers ETCRs, two transfer count registers TCRs, and two control registers DTCRs. Control registers DTCRA, DTC
Control bits having different functions are assigned to the RBs.

The DMAC 1 can be selected to be used as one channel for data transfer between memories or two channels for each data transfer between memory and input / output circuits. This selection is made by bits 1 and 2 of the control register DTCRA (TRSA1, TR
(SA2 bit), and if all the bits are set to 1, it becomes one channel for data transfer between memory and memory, and otherwise, it becomes two channels for data transfer between memory and input / output circuit. ..

When the memory-to-memory data transfer is selected, the memory address register MARA is used as an address register for designating a transfer source address, and the memory address register MARB is used as an address register for designating an address of a transfer destination.

When the data transfer of the memory-input / output circuit is selected, the memory address register MAR and the I / O address register IOAR are used as address registers for designating the transfer source and the transfer source in each channel. At this time, the I / O address register IOAR is always an address register that specifies the address of the input / output circuit. That is, when the transfer source is an input / output circuit, the I / O address register IOAR specifies the transfer source and the memory address register MAR specifies the transfer destination address. When the transfer destination is the input / output circuit, the memory address register MAR is the transfer source, and the I / O address register IOAR.
Is used as an address register that specifies the transfer destination address. Since the I / O address register IOAR has 8 bits, the address of the upper 16 bits is a fixed value, and the upper 16 bits are all 1 although not particularly limited. In this case, I / O address register IOA
Addresses that can be specified by R are H'FFFF00 to H'FF
It is 256 bytes of FFFF (H 'means a hexadecimal number). Therefore, the address of the input / output circuit is assigned to such an address.

FIG. 4 shows an address map of the single chip microcomputer 100.

Built-in ROM, although not particularly limited
4 is 32 kbytes, internal RAM 5 is 1 kbyte,
Addresses H'000000 to H'007FF respectively
It is arranged in F, H'FFFB00-H'FFFEFF,
Input / output circuits such as timer 6 and SCI 7 and DMAC1
The address of each register is H'FFFF00 to H'FF
It is located in FFFF. At this time, it is understood that the memory address register MAR can specify the entire address space, but the 8-bit I / O address register IOAR can specify only the internal input / output circuit. The addresses H'FFFF00 to H'FFFFF
Part of the external space may be provided in F.

FIGS. 5 to 7 show the function of the control register DTCR when data is transferred between the memory and the input / output circuit.

The control register DTCR selects a DTE bit for permitting transfer, a DIE bit for selecting whether to request an interrupt at the end of transfer, an RPE bit for selecting whether to repeat or end the transfer, and a transfer size. SZ
Bits, an ID bit for selecting whether to increment or decrement MAR after transfer, and TRS0 to 2 bits for selecting an activation factor.

When the DTE bit is cleared to 0, D
The corresponding channel of MAC1 is stopped. When the DTE bit is set to 1, TRS0-2 shown in FIG.
Data transfer is performed when the activation factor specified by the bit occurs. Here, 1 for TRSA2 and 1 for TRSA1, respectively
Since the transfer between the memory and the memory is performed when is set, as shown in FIG. 7, in the transfer between the memory and the input / output circuit, TRS2 and TRS in each channel are set.
A state in which both 1s are set to 1s is excluded.
When the RPE bit is cleared to 0, a predetermined number of transfers are completed and ETCR: TCR (meaning that the execution transfer count register ETCR and the transfer count register TCR are linked and used as a 16-bit register). The DTE bit is cleared to 0 when the content of is 0.

When the DTE bit is cleared to 0 and the DIE bit is set to 1, CPU1
Request a transfer end interrupt. DIE bit is 0
If cleared to, regardless of the state of the DTE bit,
No interrupt is requested to the CPU1. If the SZ bit is cleared to 0, byte data is transferred, and if the SZ bit is set to 1, word data is transferred. The RPE bit and the DIE bit specify the operation mode as shown in FIG.

First, the transfer counter is made to be an 8-bit register only by the execution transfer count register ETCR, or the execution transfer count register ETCR and the transfer count register TCR are connected to each other to make a 16-bit register ETCR: TCR.
Specify whether or not. When the RPE bit is cleared to 0 or the DTIE bit is set to 1, the transfer counter is a 16-bit register ETCR: TCR, and RP
When the E bit is set to 1 and the DTIE bit is cleared to 0, the transfer counter is set to the 8-bit register ET.
CR and TCR are used to hold the number of transfers.

ETCR or ET after completion of one transfer
CR: Decrement of TCR and RPE
The holding address of the memory address register MAR is incremented or decremented according to the setting state of the bit and the DIE bit. The increment or decrement of the memory address register MAR at this time is designated by the ID bit. The increment or decrement value is specified by the SZ bit, and 1 is incremented or decremented when the size is byte and 2 when the size is word.

If the decrement result of ETCR or ETCR: TCR used as a transfer counter is not 0, the corresponding channel will be in a standby state until the next activation factor occurs. When the decrement result becomes 0,
If the RPE bit is cleared to 0 or the DIE bit is set to 1, the DTE bit is automatically cleared to 0 and the corresponding channel is stopped. RPE bit is 1
Set to 0 and the DIE bit is cleared to 0,
The contents of the transfer count register TCR are transferred to the execution transfer count register ETCR, and the memory address register M
The contents of the transfer count register TCR are added to or subtracted from the contents of AR, the corresponding channel enters the standby state, and the transfer is repeated.

Although the activation factor designated by bits 0 to 2 of TRS is not particularly limited, as shown in FIG. 7, compare match of timer A, timer B, timer C and timer D and transmission end / reception of SCI are performed. That is the end. When the compare match of the timers A to D and the SCI transmission end are designated as the activation factors, the transfer from the address indicated by the memory address register MAR to the address indicated by the I / O address register IOAR is performed. S
When the end of CI reception is specified as the activation factor, I / O
Transfer from the address indicated by the address register IOAR to the address indicated by the memory address register MAR is performed. For these activation factors, refer to Showa 6 above.
Since it is publicly known as "Hitachi 16-bit microprocessor HD641016" issued by Hitachi, Ltd. in September 2000, further detailed description will be omitted. In addition, in FIG. 5, the symbol − means an arbitrary value.

FIG. 8 shows the function of each register in each operation mode in the data transfer between the memory and the input / output circuit.

Which of the memory address register MAR and the I / O address register IOAR designates the transfer source address or the transfer destination address differs depending on whether the activation factor is the completion of receiving the SCI7 or not. In the normal mode 2, the content of the memory address register MAR is set to a fixed value. In the repeat mode, the transfer counter has an 8-bit execution transfer count register ETCR.
In the normal mode, the transfer counter is 16-bit long ETCR: TCR.

FIG. 9 shows an example flow chart of the normal mode 1 in the data transfer between the memory and the input / output circuit of the DMAC 1, and FIG. 10 shows an example timing chart of the data transfer in the normal mode 1.

In the normal mode 1, continuous data on the memory can be transferred between a fixed 1-byte or 1-word register of the input / output circuit. The activation factor can be selected from timer compare match or SCI reception completion / transmission completion. Channel B can also select to be activated by an external terminal. When these activation factors occur, the transfer is performed once (1 byte or 1 word), and when the transfer is completed, the system waits until the activation factor occurs again. This is the transfer counter (E
(TCR: TCR) repeats the number of times specified.

For example, it can be applied to the case of transmitting a plurality of bytes of data by SCI7. In this case, the data to be transmitted is prepared on the RAM and the control register DTC
The RPE bit of R is cleared to 0, the SZ bit is cleared to 0, the ID bit is cleared to 0, the DIE bit is set to 1, and the byte number (n) of the transmission data is set in ETCR: TCR.
To the memory address register MAR, the start address (e) of the RAM, and the I / O address register IOAR.
The address (m) of the transmission data register of CI7 is written. After this, the DTE bit is set to 1 and SCI7
Enable the transmission completion interrupt of. If the SCI7 is in the standby state, immediately
A transmission completion interrupt occurs and the DMAC 1 is requested to start.

When the DMAC is requested to be activated, the DMAC1 holds the activation factor inside the DMAC1 and requests the bus right to the BSC3 in a first step S1.
If the bus right can be acquired, in a second step S2, the contents of the memory address register MAR are output to the A bus and transferred to the address buffer AB and the arithmetic logic unit ALU. The arithmetic and logic unit ALU performs an operation (+1 in the above example) designated by the SZ bit and the ID bit, and stores the result in the memory address register MAR.

In the third step S3, the address buffer A
The memory read operation is started according to the address of B. The contents of the transfer counter ETCR: TCR are output to the A bus, transferred to the arithmetic and logic unit ALU, and decremented. In the fourth step S4, the contents of the I / O address register IOAR are output to the A bus and transferred to the address buffer AB. Further, the read memory data is stored in the data buffer DB from the data bus.

If the decrement result is 0, the fifth
In step S5, the DTE bit is cleared. Also, the write operation to the SCI internal register is started according to the address transferred to the address buffer AB in the fourth step S4, and the contents of the data buffer DB are output to the data bus. In the sixth step S6, the write is completed and the DMAC1 is stopped. If the DIE bit is set to 1, a DMAC1 transfer completion interrupt is generated for the CPU2.

If the decrement result is not 0, in the seventh step, the write operation to the SCI built-in register is started according to the address transferred to the address buffer AB in the fourth step S4, and the contents of the data buffer DB are written into the data. Output to the bus. 8th following this
In the step, the write is completed and the DMAC 1 enters the standby state, and stops until the activation factor occurs again.

At the end of the transfer, the memory address register MAR is set to the address next to the last data, and the transfer counter ETCR: TCR is set to 0. The maximum value of the transfer counter ETCR: TCR is 65536. In addition,
Although not particularly limited, the read / write of the memory / input / output circuit is performed in two states.

FIG. 11 shows the SCI in the normal mode 1 as the data transfer between the memory and the input / output circuit of the DMAC1.
A reception flow chart is shown.

In this flowchart, in the second step S2, the contents of the I / O address register IOAR are set to A
The data is transferred to the address buffer AB via the bus, the reading of the SCI built-in register is started according to the address in the third step S3, and the content of the memory address register MAR is written in the address buffer AB via the A bus in the fourth step S4. To the arithmetic logic unit ALU
Then, the memory address is updated and stored again in the memory address register MAR, and the fifth step S5
Then, in the seventh step S7, the data read from the SCI built-in register is written according to the memory address of the address buffer AB, and other than that is the same as the processing of FIG.

FIG. 12 is a flowchart showing an example of the operation in the normal mode 2 for data transfer between the memory and the input / output circuit of the DMAC1.

In normal mode 2, data can be transferred between fixed 1-byte or 1-word data on the memory and the register of the input / output circuit. The activation factor can be selected from timer compare match or SCI reception completion / transmission completion. When these activation factors occur 1
The transfer is performed once (1 byte or 1 word), and when the transfer is completed, it is put in a standby state until the activation factor occurs again. This is repeated the number of times specified by the transfer counter (ETCR: TCR). Memory address register MAR
Is the same as the normal mode 1 except that the value of is fixed. Since the DIE bit is set to 1, when the transfer for the number of times specified by the transfer counter (ETCR: TCR) is completed, the CPU 2 is requested to make an interrupt.

When the DMAC1 is requested to be activated, in the first step S1, the DMAC1 holds the activation factor inside the DMAC1 and makes a bus right request to the BSC3. If the bus right can be acquired, the content of the memory address register MAR is output to the A bus and transferred to the address buffer AB in the second step S2.

In the third step S3, the address buffer A
The read operation is started at the address held by B. Also,
Transfer counter ETCR: The contents of TCR are output to the A bus, transferred to the arithmetic and logic unit ALU, and decremented. In the fourth step S4, the I / O address register I
Outputs the contents of OAR to the A bus and outputs the address buffer AB
Transfer to. The data read through the third step is stored in the data buffer DB from the data bus.

If the decrement result is 0, the fifth
In step S5, the DTE bit is cleared. Further, the write operation is started according to the address of the address buffer AB, and the content of the data buffer DB is output to the data bus. In the subsequent sixth step S6, the write is completed and the DMAC1 is stopped. If the DIE bit is set to 1, a DMAC1 transfer completion interrupt is generated for the CPU2.

If the decrement result is not 0, in the seventh step S7, the write operation is started according to the address of the address buffer AB, and the data buffer D
The contents of B are output to the data bus. In the eighth step S8 subsequent to this, the write operation is completed and the DMAC1 enters the standby state and is stopped until the activation factor occurs.

At the end of transfer, transfer counter ETCR: TC
R is 0. The transfer counter ETCR: T
The maximum value of CR is 65536 as described above, and read / write between the memory and the input / output circuit is also performed in two states.

FIG. 13 is a flow chart showing an example of the repeat mode in data transfer between the memory and the input / output circuit of the DMAC 1, and FIG. 14 is a timing chart showing an example of the data transfer operation in the repeat mode.

The repeat mode is an operation mode in which data can be repeatedly transferred between continuous data on the memory and a fixed register of 1 byte or 1 word of the input / output circuit. The activation factor can be selected from compare match of timer 6 or reception completion / transmission completion of SCI7. When these activation factors occur, transfer is performed once (1 byte or 1 word), and when the transfer ends,
It is in a standby state until the activation factor occurs again. When this is repeated the number of times specified by the transfer counter (ETCR), the contents of the memory address register MAR and the execution transfer count register ETCR are restored, and the transfer is further repeated.

For example, it can be applied when the excitation data of the stepping motor controlled by the single chip microcomputer 100 is output through the pulse output device 8. In this case, for example, compare match of timer A is selected as the activation factor. RAM to output data
Prepare on top of 5. This data is, for example, excitation data for one rotation of the stepping motor.

Set the RPE bit of the control register DTCR to 1
Set to 0, clear SZ bit to 0, and set ID bit to 0
, The DIE bit is cleared to 0, and the execution transfer count register ETCR and transfer count register TC
The number of bytes of transmission data (n) is stored in R, and the start address (e) of the RAM 5 is stored in the memory address register MAR
The address (m) of the output data register built in the pulse output device 8 is written in the / O address register IOAR.
After this, the DTE bit is set to 1 to enable the timer A compare match interrupt. When the compare match of the timer A occurs, the pulse output device 8 outputs a pulse and the DMAC 1 is requested to start.

When the DMAC1 is requested to be activated, in the first step S1, the DMAC1 holds the activation factor inside the DMAC1 and makes a bus right request to the BSC3. If the bus right can be acquired, in a second step S2, the contents of the memory address register MAR are output to the A bus and transferred to the address buffer AB and the arithmetic logic unit ALU. The arithmetic logic unit ALU performs an operation (+1 in this example) designated by the SZ bit and the ID bit, and writes the result back to the memory address register MAR.

In the third step S3, the read operation is started according to the address held in the address buffer AB. Further, the contents of the transfer counter ETCR are output to the A bus, transferred to the arithmetic logic unit ALU, and decremented. In the fourth step S4, the contents of the I / O address register IOAR are output to the A bus and the address buffer A
Transfer to B. Further, the data which has started the reading is stored in the data buffer DB from the data bus.

If the result of the decrement is 0, the process proceeds to the fifth step S5, the contents of the transfer count register TCR are output to the C bus, and the execution transfer count register E is output.
The data is transferred to the TCR and also input to the arithmetic logic unit ALU. On the other hand, the contents of the memory address register MAR are output to the A bus and given to the arithmetic and logic unit ALU, and SZ
An operation is performed based on the bit and the ID bit to return the content of the memory address register MAR to the initial value (e). Further, the write operation is started according to the address held in the AB, and the content of the data buffer DB is output to the data bus.

If the decrement result is not 0, the process proceeds to the sixth step S6, the write operation is started according to the address held in the address buffer AB, and the contents of the data buffer DB are output to the data bus.

In the seventh step S7, the writing is completed and D
MAC1 is in a standby state, and the transfer operation is stopped until an activation factor occurs. Execution transfer count register ETC
The maximum value of R and the transfer count register TCR is 256. As in the above, the read / write between the memory and the input / output circuit is performed in two states. For timer compare match and pulse output device, see 6
February, "Hitachi 8 / 16-bit microcomputer peripheral LSI" published by Hitachi, Ltd. P538 to P59
Since it is publicly known, the detailed description thereof will be omitted.

FIGS. 15 to 18 show control registers DTCRA and DTC for memory-to-memory data transfer.
The function of TCRB is shown.

Data transfer between memories is TRSA.
Both 1 and TRAS2 are selected by setting them to 1. Data transfer is performed between the address indicated by memory address register MARA and the address indicated by memory address register MARB. At this time, the I / O address registers IOARA and IOARB are not used.

The control register for data transfer between the memories is a DTEA bit which permits the transfer,
Select whether to request an interrupt at the end of transfer D
IEA bit, SZA bit for selecting transfer size, and RP for selecting whether to increment, decrement, or fix MARA and MARB after transfer
Each bit of EA, RPEB and IDA, IDB, TRSA0 bit for selecting transfer mode, DT indicating transfer interruption
In the memory-memory transfer mode 2 (block transfer mode), the EB bit is composed of a DIEB bit for selecting which of a transfer source and a transfer destination is a block area, and TRSB0 to TRSB2 bits for selecting an activation factor. ..

When the DTEA bit is cleared to 0, the DMAC1 is stopped. When the DTEA bit is set to 1, data transfer is performed when the activation factor designated by the bits TRSB0 to 2 occurs. When the content of the transfer counter ETCRA: TCRA becomes 0 after the transfer of a predetermined number of times is completed, the DTEA bit is cleared to 0.

If the DIEA bit is set to 1 when the DTEA bit is cleared to 0, the CPU
Request a transfer end interrupt to 1. If the DIEA bit is cleared to 0, no interrupt is requested to the CPU 1 regardless of the state of the DTEA bit.

If the SZA bit is cleared to 0, byte data is transferred, and if the SZA bit is set to 1, word data is transferred.

RPEA, RPEB bits and IDA, ID
B bit is a memory address register MARA, MAR
Specify the operation of B. When the RPEA and PREB bits are cleared to 0, the memory address register MAR
The values of A and MARB are fixed values. RPEA, RPE
IDA, ID when B bit is set to 1
If the B bit is cleared to 0, the memory address registers MARA and MARB are incremented, and if the IDA and IDB bits are set to 1 at that time, the memory address registers MARA and MARB are decremented. The increment or decrement value is designated by the SZA bit, and 1 is incremented or decremented when the size is byte and 2 when the size is word. Memory address register MAR
The operations of A and MARB can be designated independently.

The TRSA0 bit is set to the memory-memory transfer mode 1 as shown in FIG.
The memory transfer mode 2 (block transfer mode) is selected. The activation factor designated by bits 0 to 2 of TRSB is not particularly limited, but as shown in FIG. 18, it is an auto request, an external terminal, and a compare match of the timer A, timer B, timer C, and timer D. .. However, the start factors that can be selected are different between the memory-memory transfer mode 1 and the memory-memory transfer mode 2 (block transfer mode).

FIG. 19 shows the function of each register for each operation mode in data transfer between memories.

Both the mode 1 in the memory-memory transfer and the mode 2 (block transfer mode) in the memory-memory transfer are the memory address register MAR.
A and MARB are respectively address registers for designating a transfer destination and a transfer source, and ETCRA: TCRA serves as a transfer counter. The memory-memory transfer mode 2 (block transfer mode) further uses the register TCRB to specify the block size and the register ETCRB to count the data in the block. The I / O address registers IOARA and IOARB are not used. Although not particularly limited, the maximum value of the block is 256 (byte or word).

FIG. 20 shows an example operation flowchart of the memory-memory transfer mode 1, and FIG.
An example operation timing chart of the memory transfer mode 1 is shown.

The memory-memory transfer mode 1 auto request is an operation mode in which when the CPU 1 sets the DTEA bit to 1, a transfer request is automatically generated and transfer is performed. In the burst mode, once the DMAC1 acquires the bus right, the transfer is performed until the transfer specified by the transfer counter ETCRA: TCRA is completed. In the cycle steal mode, the bus right is released to the CPU2 at each transfer. Transfer. In the burst mode, when the highest priority interrupt request (NMI) from the external terminal occurs, the DTEA bit remains set to 1 and the DT
The EB bit is cleared to 0, the transfer is interrupted, and the CPU2
Open the bus right to. After that, when the CPU 2 sets the DTEA bit or the DTEB bit to 1, the transfer is restarted based on this.

In the transfer request from the external terminal, after the DTEA bit is set to 1 and the signal specified by TRSB0 to 2 is generated in the external terminal (DREQ), the transfer is performed once, and when the one transfer ends, the transfer is designated. It goes into a standby state until the generated signal is generated at the external terminal (DREQ). This is repeated the number of times designated by the transfer counter ETCRA: TCRA.

Regarding such operation of the DMAC1,
Since it is known from "Hitachi 16-bit Microprocessor HD641016" P169 to P206, etc., issued by Hitachi, Ltd. in September 1987, detailed description thereof will be omitted.

FIG. 22 shows an example operation flowchart of the memory-memory transfer mode 2.

In the memory-memory transfer mode 2 (block transfer mode), the data block size is set in the register TC.
It is stored in RB and ETCRB, and the number of times of data transfer is designated in the transfer counter ETCRA: TCRA.

In the memory-memory transfer mode 2 (block transfer mode), when a transfer factor occurs, data transfer is performed from the address indicated by the memory address register MARA to the address indicated by the memory address register MARB. MARA, M
ARB holding value is RPEA, IDA, SZA, RPE
It is incremented, decremented, or fixed according to the designation of B, IDB, and SZB bits. Further, the value of the register ETCRB is decremented. This is repeated until the value of the register ETCRB becomes 0. When the value of the register ETCRB becomes 0, the contents of the register TCRB are transferred to the register ETCRB as in the repeat mode,
The contents of the memory address register MARB are returned to the initial state, and the contents of the transfer counter ETCRA: TCRA are decremented. If the decrement result is not 0, the process waits until an activation factor occurs. The above operation is performed every time an activation factor occurs. Transfer counter ETCRA: TCR
Repeat until A becomes 0.

FIG. 23 shows a specific example circuit diagram of the arithmetic and logic unit ALU, the shifter SFT, and the selector SEL.

The arithmetic and logic unit ALU is composed of a decrementer DECRMT, an adder circuit ADD, and a zero detection circuit ZERO, although not particularly limited thereto. The arithmetic and logic unit ALU is composed of 24 bits, and the lower 8 bits (ALU-L) are selected from the data from the A bus (A0 to A7), the constant value or the input from the C bus (C0 to C7). , And whether or not to shift them by 1 bit to the upper side or invert them is selected, and the selection result is input. Upper 16 bits (ALU-H, A
LU-E) contains data from the A bus (A8 to A23),
Enter a constant value. Whether or not to invert the constant value is selected. For bit 8, either the shift output from bit 7 or a constant value is selected.

The constant value is stored in the memory address register MAR.
, The transfer counter ETCR: TC
1 is input to the bit 8 during the operation of R, 1 is input into the bit 16 when the operation of the transfer counter TCR is performed, and 0 is input to the bit 16 in other cases or other bits.
Memory input from the C bus is selected when the ETCR becomes 0 in the repeat mode or when the ETCRB becomes 0 in the block transfer mode and the contents of the TCR or TCRB are input, and the memory input from the A bus. It is calculated with the contents of the address register MARA or MARB. When the word size data is being transferred, the shift is selected during the increment / decrement of the memory address register MAR and the above calculation. Inversion is selected when decrementing or subtracting. The zero detection circuit ZERO outputs 1 when the upper 8 bits are 0 and the transfer counter has an 8-bit length, or when the upper 16 bits are 0, to detect the end of the transfer.

FIG. 24 shows a concrete example circuit diagram of the register.

The I / O address register IOAR is an 8-bit register and can be output to the A bus while the system clock φ is 1 level and can be input from the B bus while the system clock φ is 0 level. .. When the I / O address register IOAR is output to the A bus, one level is output to the upper 16 bits of the A bus. This allows the I / O address register IOA
The designated address of R is H'FFFF00 to H'FFFFF
It becomes F. Although not particularly limited, the A bus may be precharged by the P channel type MOS during the period when the system clock φ is 0 level. In this way, the clock gate can be deleted.

The transfer count register TCR is an 8-bit register and can be output to the A bus while the system clock φ is at 1 level, and can be input from the B bus while the system clock φ is at 0 level. Therefore, the system clock φ can be output to the C bus during the period of 1 level.

The execution transfer count register ETCR is an 8-bit register and can output to the A bus while the system clock φ is at 1 level.
Can be input from the B bus during the 0 level period, and can be input from the C bus during the 1 level level of the system clock φ.

Although not shown, the memory address register MAR has the same structure as the I / O address register IOAR for 24 bits. No clock gate equivalent is required.

FIG. 25 shows a specific example circuit diagram of the data buffer and the memory interface.

In the present embodiment, although not particularly limited, when the CPU 2 reads / writes the register of the DMAC 1, the 8-bit bus, that is, the upper 8 bits D15-8 of the internal data bus is used. Therefore,
The lower side (DB-L) of the data buffer DB is DMAC1.
Not connected to the internal bus. The data written from the CPU 2 is output to the B bus via the data buffer DB-H by 8 bits, and is written to the selected register by determining the lower address. When the CPU 2 reads, the lower address is determined, data is output from the selected register to the A bus, and the contents of the A bus are selected by the memory interface MIF. Such data is output to the internal data bus via the data buffer DB-H and read by the CPU 2.

The data read by the DMAC 1 at the time of data transfer is temporarily stored in the data buffer DB from the internal data bus and then output as write data to the internal data bus. The bus controller 3 indicates whether the valid data is output to the upper or lower portion of the internal data bus at the time of reading, and to the upper or lower portion of the internal data bus at the time of writing. For example, when a 16-bit memory or an input / output circuit is read / written in byte size, data is output to the upper part of the internal data bus if the address is even, and to the lower part if the address is odd. In addition, when reading / writing 8-bit memory or input / output circuit,
Data shall be output to the upper part of the internal data bus. When such an 8-bit memory or an input / output circuit is read in word size, the reading is continuously performed twice in the order of even addresses and odd addresses. The same applies to lights. Although not particularly limited, word data is limited to data starting from an even address. The DMAC
1 stores byte size data in the upper part of the data buffer and word size data in the upper and lower parts.

FIG. 26 shows a specific example circuit diagram of the factor holding means included in the control unit CONT of the DMAC 1.

The factor holding means includes factor selection circuits (selectors) 201 and 202, factor holding circuits (flip-flops) 211 and 212, and priority determination circuits (encoders).
221, a timing control circuit 231, and a clear control circuit 241. Factor selection circuits 201, 201
02, the factor holding circuits 211 and 212, and the priority determination circuit 221 control the activation of the DMAC1. The timing control circuit 231 generates the operation timing. In the figure, the symbol * means that it is an inversion signal of the signal without it.

The selectable activation factors are input to the factor selection circuits 201 and 202 from outside the DMAC 1. The T
These activation factors are selected based on the RS0 to TRS0 bits and input to the factor holding circuits 211 and 212. When the DTE bit is cleared to 0, the factor holding circuits 211 and 212 are always reset.
In the memory-memory transfer mode, the channel B factor holding circuit 212 is reset.

If any of the factor holding circuits 211 and 212 is set to 1, the priority determination circuit 221 makes a bus request to the bus controller 3 and gives an operation instruction to the timing control circuit 231. Furthermore, if the factor holding circuits 211 and 212 of both channels A and B are set to 1, channel A is prioritized.

The timing control circuit 231 receives the register DTCRA, when the bus right acknowledge signal becomes 1 level.
The operation of the above operation flowchart is controlled based on the value of DTCRB. The clear control circuit 241 is activated by each activation request source (timer / SCI) based on the activation factor clear signal instructed by the timing control circuit 231, the channel instructed by the priority determination circuit 221, and the TRS2 to TRS0 bits. Give a clear signal of the factor.
In addition, the factor holding circuits 211 and 212 that are being executed are reset.

When the same activation factor is selected for the channels A and B, the two factor holding circuits 211 and 212 are set, the channel A with the higher priority is executed first, and the activation factor and the channel are executed during execution. Although the factor holding circuit 211 of A is cleared, the factor holding circuit 212 of channel B remains set and the data transfer of channel B can be executed after the execution of channel A is completed.

FIG. 27 shows another embodiment of the DMAC1.

The DMAC 1 shown in the figure has two sets of register groups each consisting of channels A and B, and has a data buffer DB (DB-L, DB-H) and an arithmetic logic unit ALU (ALU) common to them. -L, ALU-H, ALU-
E), shifter SFT, selector SEL, memory interface MIF (MIF-L, MIF-H, MIF-E,
MIF-C) and address buffers AB (AB-L,
AB-H, AB-E). DMAC1 of FIG.
As compared with the case where two sets are provided, the logical and physical scale of the DMAC 1 can be reduced by the amount that the circuits such as the ALU can be shared.

In the DMAC1 of FIG. 27, the priority of each channel is set higher in the order of channels 1A>1B>2A> 2B. At this time, the factor holding means of the control unit CONT is
This can be easily realized by providing four factor selection circuits and factor holding circuits as described with reference to FIG. 26 and changing the logic of the priority determination circuit accordingly.

FIG. 28 shows a state transition diagram of the DMAC1.

In the explanation of the operation timing chart,
Although both the memory and the input / output circuit are read / written in two states, the wait may be requested from the externally connected memory or input / output circuit. The bus controller 3 determines whether or not the wait is requested, and instructs the DMAC 1. Control unit CON of DMAC1
When T is instructed to wait, TRW is inserted between TR1 and TR2 in the read cycle, and TWW is inserted between TW1 and TW2 in the write cycle. TR
For W and TWW, DMA other than data buffer DB
Each part of C1 is in a non-operation state. When an 8-bit memory or input / output circuit is read / written in word size, it is read / written in order of even addresses and odd addresses.
When writing is performed twice consecutively, the first cycle of the first read / write is set to TR1 · TW1 and 2
TR2 TW for the last cycle of the second read / write
2, and all other cycles are recognized as TRW / TWW, and the DMAC 1 recognizes them.

FIG. 29 shows an example block diagram of the bus controller 3.

The bus controller 3 includes an address decoder ADRDEC, an AND circuit ANDLOG, a control register CONTREG, a wait control circuit WSCONT,
And an access control circuit ACSCONT. Address decoder ADRDEC is CPU2 or DM
The address signal output from AC1 is input, a selection signal for the built-in functional block is generated, and the address signal is output. The control register CONTREG includes the bus width designation register BSWCR and the access state designation register A.
An STCR, a wait state control permission designation register WSCER, and an address multiplex designation register MPXCR are provided, and their contents can be arbitrarily set under the control of the CPU 2. AND circuit ANDL
The OG is an address signal supplied through the address decoder ADRDEC and the registers BSWCR, ASTCR, WSCER, M included in the control register CONTREG.
Based on the value of PXCR, control signals relating to wait permission, bus width, access state, and address multiplex are generated and given to the access control circuit ACSCONT. The wait control circuit WSCONT receives a wait signal issued from a built-in functional block or the like and issues a wait request corresponding to the required number of states to the access control circuit ACS.
Give to CONT. Access control circuit ACSCONT
Receives various signals provided from the AND circuit ANDLOG, the wait control circuit WSCONT, etc., and various strobe signals AS, HRD, LR for access control.
It generates D, HWR, LWR, and buffer control signals for the CPU 2 and the DMAC 1.

When a data transfer activation factor occurs in DMAC1, the DMAC bus request signal is set to 1 level. In response to this bus request, the bus controller 3 permits the DMAC 1 to use the bus at a predetermined timing, and sets the DMAC bus permission signal to 1 level. CPU otherwise
2 can use the bus. The bus activation signal and address input are multiplexed between the output of the CPU 2 and the output of the DMAC 1. That is, if the DMAC bus permission signal is at the 1 level, the bus activation signal or address input from the DMAC 1 is accepted, and otherwise the bus activation signal or address input from the CPU 2 is accepted. The internal operation of the bus controller 3 includes access by the CPU 2 and D
It is the same in both cases of access by MAC1.
The buffer control signal to be given to the CPU2 / DMAC1 during read / write is also multiplexed.

30 to 34, the control signal HH,
The output specifications of LH, HL, and LL are shown.

The size is the size of transfer data designated by SZ bits, and the bus width is the data width of the memory or input / output circuit to be transferred. T1 is the first state, T2 is the second state, T3 is the third state, T
w is a wait state. In the figure, the symbol − means that there is no corresponding state. The states are not particularly limited, but there are two states and two types of reading or writing with three or more states. In addition, 4 states or more are realized by requesting a wait for 3 states. A0 is bit 0 of the address bus. Although not particularly limited, word size data always starts with an even address. At the time of reading and writing of the DMAC1, the control signals HH, LH, HL, L
Based on L, the data buffers DB-L, DB of FIG.
-H control is performed. The data buffer of the CPU 2 can be similarly configured.

FIG. 35 is a block diagram of another embodiment of a single chip microcomputer to which the data transfer control device according to the present invention is applied.

The single chip microcomputer 101 shown in FIG. 35 is different from the single chip microcomputer of FIG.
The difference is that they are provided individually. For convenience, both DMAC1 are D
It is described separately for MAC1-1 and DMAC1-2. At this time, the bus controller 33 uses the bus controller 3
On the other hand, if two sets of the DMAC bus request signal and the DMAC bus permission signal are provided and the number of inputs of the multiplexer is increased, this can be easily realized. The priority order in bus arbitration is, for example, DMAC1-1> DMAC1-2. Such priority control is included in the arbitration function of the bus controller 33.

FIG. 36 shows a printer control system as an example of a control system to which the single chip microcomputer 101 of FIG. 35 is applied.

The printer control system includes a single-chip microcomputer 101, a Centronics interface circuit 301, a buffer RAM 302, a character generate ROM (CGROM) 303, an output buffer RAM 304 serving as a print data output buffer, and a print head 305 of the printer. They are connected via an external bus 306 of the single-chip microcomputer 101, and further include a line feed motor 307 and a carriage return motor 308 for mechanically moving the print head. These motors 3
07 and 308 are driven and controlled by the output of the timer 6 and the output of the pulse output device 8, respectively. Line feed motor 307 and carriage return motor 30
Reference numeral 8 is a stepping motor, although not particularly limited.

Data sent from a host processor (not shown) is the Centronics interface circuit 301.
Is transferred to the buffer RAM 302 via. The channel 1 of the DMAC 1-1 (a configuration in which the channels 1A and 1B are combined) can be used for such a transfer by starting the external terminal of the memory-memory transfer mode 1. The address of the Centronics interface circuit 301 is set in the memory address register MARA, and the buffer RAM
The address of 302 is set in the memory address register MARB, and the transfer count is set to the transfer counter ETCRB: TCRB.
Set to. For example, the memory address register MARA
Is fixed, the memory address register MARB is set to the increment mode, and the Centronics interface circuit 3
The 01 strobe signal may be input to the DREQ1 terminal.

The CPU 2 generates a character R based on the data stored in the buffer RAM 302.
The OM 303 is referred to and the data is converted into font data. For example, the data is converted for one line and stored in the print data buffer RAM 304.

After that, the timer A61 and the channels 2A and 2B of the DMAC1-1 are activated and pulse output is performed.
The carriage return motor 308 is driven. The print head 3 is rotated by the rotation of the carriage return motor 308.
05 moves. As the print head 305 moves,
Print data buffer 304 to print data head 305
Data transfer to. As the print data, the data of each column of one font is transferred as one block. For example, if one font has 24 × 24 dots, one block has 2
There are 4 bits or 3 bytes. DMAC1 for such transfer
The channel-1 of -2 can be used in the memory-memory transfer mode 2 (block transfer mode) by the compare match of the timer B62, although not particularly limited thereto.

FIG. 37 shows an example of a stepping motor control method.

In this embodiment, both channels 2A and 2B of the DMAC 1-1 are activated by the compare match signal of the timer A. The channel A transfers from the built-in RAM 5 to the comparison register TCMR of the timer A. The channel 2B transfers from the built-in RAM 5 to the output buffer register NDR of the pulse output device 8. The pulse output device 8 outputs the content of NDR as a pulse when the compare match signal of the timer A is generated. Therefore, the timer A is transferred by the transfer of the channel 2A for each compare match of the timer A.
The comparison register TCMR is rewritten to change the compare match period, that is, the pulse output interval. As a result, the stepping motor can be accelerated or decelerated. When accelerating the motor, the content of the first comparison register may be gradually reduced to shorten the pulse output interval. On the contrary, when the motor is decelerated, the content of the first comparison register may be gradually increased to shorten the pulse output interval. The counter of timer A is set so that it is cleared to 0 when the contents of the comparison register match.

The channel 2B transfers the excitation data of the stepping motor motor stored in the internal RAM 5 to the NDR in the repeat mode through the phases 1 to 3. In channel 2A, phase 1 and phase 3 are normal mode 1
Then, the phase 2 operates in the normal mode 2 and transfers the compare match cycle stored in the internal RAM 5 to the comparison register TCMR.

FIG. 38 shows an example of a memory map when controlling the stepping motor.

In the compare match cycle, m2 + 1 words are stored in the internal RAM 5 starting from the address RAMA1. Although not particularly limited, the comparison register has 16 bits and is stored in descending order of the compare match period. The excitation data is stored in n bytes starting from the address RAMA0.

Channel 2B registers ETCR and TC
R is set to n, and the start address RAMA0 of excitation data is set to the memory address register MAR. Clear SZ bit to 0, ID bit to 0, RPE bit to 1, DIE bit to 0, TRS2
~ Clear all 0 bits to 0.

If the total number of revolutions is m1 and the number of revolutions during acceleration / deceleration is m2, the ETC of channel 2A in phase 1 is assumed.
R: TCR is set to m2-1 and the memory address register MARA is set to the start address RAM of the compare match cycle.
Set 1 + 2. The SZ bit is set to 1, the ID bit is cleared to 0, the RPE bit is cleared to 0, the DIE bit is set to 1, and the TRS2-0 bits are all cleared to 0. After that, set the DTE bit to 1 and set CP
It suffices that U2 write the contents of the address RAMA0 in the comparison register, operate the timer A, and generate a compare match signal. The contents of the RAM 5 are transferred to the comparison register one word for each compare match, and when the compare match occurs m2 times, ETCR: TCR becomes 0, the DTE bit is cleared to 0, and an interrupt request is sent to the CPU 2. , Channel 2A is stopped.

In phase 2, the CP request causes CP
U2 executes the interrupt processing routine, and ETCR: TC
After setting m1-m2 × 2 to R, setting the RPE bit to 1, and then setting the DTE bit to 1. When a compare match occurs, the contents of RAM1 + (m2-1) × 2 are transferred to the comparison register. Compare match is m1
When -m2 × 2 times occur, ETCR: TCR becomes 0, the DTE bit is cleared to 0, an interrupt is requested to the CPU 2, and the channel 2A is stopped.

In phase 3, the interrupt request causes C
PU2 executes the interrupt processing routine to execute ETCR: T
Set m2 in CR, clear RPE bit to 0, ID
After setting the bit to 1, set the DTE bit to 1. When a compare match occurs, RAM1 + (m2
-1) The contents of the RAM 5 are transferred to the comparison register while sequentially subtracting the address from the contents of the address 2. When a compare match occurs m2 times, ETCR: TCR becomes 0, the DTE bit is cleared to 0, an interrupt is requested to the CPU 2, and the channel 2A is stopped.

In response to this interrupt request, the CPU 2 executes the interrupt processing routine to generate the compare match m1 times, rotate the stepping motor a predetermined number of times, and stop the timer A assuming that the print head 305 has moved a predetermined amount. Then, the DTE bit of channel B is cleared to 0 and the operation is stopped. The pulse output device also stops while holding the last output value. Further, the output of the pulse output device 8 may be cleared to zero.

After that, when the stepping motor is rotated in the reverse direction, the channel 2B has the memory address register M
The last address RAM0 + n-1 of the excitation data is set in AR, and the ID bit is set to 1. The channel A may repeat the above operation. Since the contents of the comparison register of timer A are the contents of address RAMA0, the CPU
2 need not perform the transfer.

Alternatively, when the motor rotates in the reverse direction from the stopped position, the last data of MARB and ETCRB is determined, and MAR is RAMA0 to RAMA0 + n-.
1, ETCR may be reset within the range of 1 to n.

FIG. 39 shows an example timing chart at the time of controlling the stepping motor.

Channel 2 is generated by the occurrence of compare match.
Although activation of both A and 2B is required, channel 2A has a high priority and is executed first. The channel 2A transfers 1 word as described above and rewrites the comparison register, and then the channel 2B transfers 1 byte and rewrites the excitation data. This excitation data is output from the pulse output device 8 at the next compare match. The next compare match is done with the new compare register value.

FIG. 40 shows a specific example circuit diagram of the pulse output device 8.

The pulse output device 8 has a buffer register N.
It comprises a DR, an output data register DR, a buffer permission register NDER, and a data direction register DDR.
When performing pulse output, the data direction register DD
Set R to 1 and set buffer enable register NDER to 1
Set to. Writing from the internal bus of the output data register DR is prohibited, and the content of the buffer register NDR is transferred to the output data register DR when a compare match occurs. This content is held in the output data register DR and is output from the terminal P. Buffer register N
DR can always be written from the internal bus. Such a write does not depend on whether the CPU2 or the DMAC1.

FIG. 41 is a block diagram showing an example of the stepping motor drive circuit.

Although not particularly limited, the pulse output signal of the pulse output device 8 is applied to the 8-pole 4-phase stepping motor via the power drive element. For example, by outputting 1 and 0 levels to the pulse outputs 0 and 4, respectively, a current is caused to flow between the poles of the stepping motor through the power drive element to drive the motor. For example, the excitation data is H'1E, H'2D,
By outputting H'4B and H'87, the stepping motor rotates leftward. As the power drive element, for example, a complementary power MOSFET can be used.

FIG. 42 shows an example of a memory map when print data is output.

Although not particularly limited, one row of data m × n bytes is stored in the print data buffer starting at the address BFR0. If the font data of 24 × 24 dots is 40 per line, m = 3,
n = 24 × 40, which is 2880 (3 × 24 × 40) bytes. This is transferred to the print data head 3 bytes at a time.

FIG. 43 shows an example timing chart when printing data is output.

The timing of print data is designated by the timer B. Although not particularly limited, the timer B has first and second comparison registers, starts the DMAC by the first compare match, and outputs 0 to the timer output terminal that is also used as the input / output port (not shown). Output level. Also, one level is output to the timer output terminal by the second compare match. The print data is at the time of the second compare match, that is, 0 at the timer output terminal.
When the level changes to 1 level, 24 dots are printed collectively, and after the first compare match occurs, the next print data is transferred by the DMAC.

In this embodiment, the line feed motor is driven by the timer A and the print timing is generated by the timer B. Therefore, it is desirable that the printing is performed during the constant speed rotation of the phase 2. If the same timer is used to drive the line feed motor and generate the print timing, the above restriction does not occur.

FIG. 44 shows an example of print data.

Although the character data is not particularly limited,
It is sent from the host processor in 2 bytes per character. Font data 96 in character generation ROM
Expands to (3 x 24) bytes. The 3-byte data for one column is assigned to the 3-byte print head.

In the above embodiment, the print head has a continuous 3-byte address different from each other, but it may have a 1-byte address as a first-in first-out buffer. In this case, the RPEB bit may be cleared to 0 and MARB may be fixed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the detailed structure of the DMAC is as follows.
Any number of channels other than 2 channels (1 set) or 4 channels (2 sets) may be used. The configuration of the internal bus of the DMAC can be changed in various ways. Further, the internal configuration of the single-chip microcomputer is not limited at all. It is possible to change the number of timer channels, timer functions, types of activation factors, etc. For example, the activation factor that can be selected can be changed for each channel.

In the above explanation, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer and the printer control system which are the fields of application in the background has been explained, but the invention is not limited thereto. The present invention can be applied to other semiconductor integrated circuit devices or control systems, and the present invention can be applied to a semiconductor integrated circuit device having at least a function of performing data transfer and a control system using such a semiconductor integrated circuit device. it can. For example, it is possible to control the driving of three motors for reading, recording, and unloading the FAX by using the data transfer control device for each two channels (one set).

[0147]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the minimum resources are added to the resources for one channel in the case of memory-to-memory data transfer, and the data is used as two channels for data transfer activated by an interrupt requested by the input / output circuit. By making it possible, it is possible to improve the utilization efficiency of resources for transfer control such as registers that specify the transfer source and the transfer destination, and it is possible to easily deal with many interrupt factors. effective. In addition, the hardware of the data transfer control device can support the data block transfer between the memory and the memory, and the repeat transfer mode or the multi transfer mode between the memory and the input / output circuit. The range can be easily expanded.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a single chip microcomputer to which a data transfer control device according to the present invention is applied.

FIG. 2 is a block diagram of a DMAC which is an embodiment of a data transfer control device according to the present invention.

FIG. 3 is a register configuration diagram of an example of a DMAC.

FIG. 4 is an example address map of a single-chip microcomputer.

FIG. 5 is a first functional explanatory diagram of the control register at the time of memory-input / output circuit transfer.

FIG. 6 is a second functional explanatory diagram of the control register at the time of memory-input / output circuit transfer.

FIG. 7 is a third functional explanatory diagram of the control register at the time of memory-input / output circuit transfer.

FIG. 8 is a fourth functional explanatory diagram of the control register at the time of memory-input / output circuit transfer.

FIG. 9: Memory-input / output circuit transfer (normal mode 1)
It is an example operation flowchart.

FIG. 10 is an example operation timing chart of FIG. 9;

FIG. 11 is another operation flowchart of memory-input / output circuit transfer (normal mode 1).

FIG. 12 is an operation flowchart of an example of memory-input / output circuit transfer (normal mode 2).

FIG. 13: Memory-input / output circuit transfer (repeat mode)
It is an example operation flowchart.

FIG. 14 is an example timing chart of FIG. 13;

FIG. 15 is a first functional explanatory diagram of a memory-memory control register.

16 is a second functional explanatory diagram of the control register at the time of memory-memory transfer. FIG.

FIG. 17 is a third functional explanatory diagram of the control register at the time of memory-memory transfer.

FIG. 18 is a fourth functional explanatory diagram of the control register at the time of memory-memory transfer.

FIG. 19 is a functional explanatory diagram of registers for each mode during memory-memory transfer.

FIG. 20 is an operation flowchart of an example of memory-memory transfer (normal mode).

FIG. 21 is an example timing chart of FIG. 20.

FIG. 22: Memory-memory transfer (block transfer mode)
It is an example operation flowchart.

FIG. 23 is a specific example circuit diagram of an arithmetic logic unit.

FIG. 24 is a specific example circuit diagram of a register.

FIG. 25 is a specific example circuit diagram of a data buffer and a memory interface.

FIG. 26 is a specific example circuit diagram of a factor holding unit included in the control unit.

FIG. 27 is a block diagram of another embodiment of the DMAC.

FIG. 28 is a state transition diagram of an example of the DMAC.

FIG. 29 is a block diagram of an example of a bus controller.

FIG. 30 is an explanatory diagram 1 of an operation specification of the bus controller.

FIG. 31 is a second explanatory diagram of the operation specifications of the bus controller.

FIG. 32 is a third explanatory diagram of the operation specifications of the bus controller.

FIG. 33 is an explanatory diagram 4 of an operation specification of the bus controller.

FIG. 34 is a fifth explanatory diagram of the operation specifications of the bus controller.

FIG. 35 is a block diagram of an embodiment of a single chip microcomputer.

FIG. 36 is a block diagram of an example of a printer control system to which a single chip microcomputer is applied.

FIG. 37 is an explanatory diagram of a stepping motor control method that can be adopted in the printer control system.

FIG. 38 is an explanatory diagram showing an example of a memory map during stepping motor control.

FIG. 39 is an example timing chart when controlling a stepping motor.

FIG. 40 is a specific example circuit diagram of a pulse output device.

FIG. 41 is a block diagram showing an example of a stepping motor drive circuit.

FIG. 42 is an example memory map when print data is output.

FIG. 43 is an example timing chart when printing data is output.

FIG. 44 is a diagram illustrating an example of print data.

[Explanation of symbols]

1 DMAC (Direct Memory Access Controller) 1-1 DMAC 1-2 DMAC 2 CPU (Central Processing Unit) 3 BSC (Bus Controller) 4 ROM 5 RAM 6 Timer 7 SCI (Serial Communication Interface) 8 PSO (Pulse Output Device) MAR Memory address register IOAR I / O address register ETCR Execution transfer count register TCR Transfer count register DTCR control register TRSA1, TRSA2 1 channel / 2 channel designation bit ALU Arithmetic and logic unit AB address buffer DB data buffer MIF memory interface CONT control unit 100 Single Chip Microcomputer 101 Single Chip Microcomputer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Teruichi Watanabe 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. 20-1 No. 1 In stock company Hitachi Ltd. Musashi factory

Claims (9)

[Claims] 1. A data transfer control device for controlling data transfer between storage devices arranged in an address space, comprising: register means for designating an address of a data transfer source or a data transfer destination; and a register means of the register means. A data transfer control device having means for selecting whether the number of bits is a number of bits corresponding to the address space or a number of bits smaller than the number of bits. 2. A data transfer control device capable of configuring a plurality of data transfer channels for performing a plurality of data transfers between storage devices arranged in an address space, the data transfer control device comprising: A data transfer control device, wherein resources of a plurality of data transfer channels can constitute a single data transfer channel for performing a single data transfer. 3. In the single data transfer channel for performing the single data transfer, the number of bits of register means for designating addresses of a transfer source and a transfer destination is a bit number corresponding to the address space. In the plurality of data transfer channels for performing the plurality of data transfers, the number of bits of register means for designating an address of a transfer source or a data transfer destination is smaller than the number of bits corresponding to the address space. The data transfer control device according to claim 2, wherein 4. Each data transfer channel for performing the plurality of data transfers includes a first register means having a bit number corresponding to the address space and a second register means having a bit number smaller than the bit number. 4. The data transfer control device according to claim 3, further comprising: 5. When performing the single data transfer,
The first register means of each of the plurality of data transfer channels for data transfer is used as a transfer source / transfer destination addressing means, and the transfer count means of one of the plurality of data transfer channels for the plurality of data transfers is used. Used as a transfer count means for counting the number of transfers, the other transfer count means of the plurality of data transfer channels for the plurality of data transfers is a data block size designating means and a unit number in units of data blocks. 5. The data transfer control device according to claim 4, further comprising a block transfer mode as the specifying means, wherein the data transfer of the specified data block size is repeated a number of times specified by the unit specifying means. 6. A data transfer mode using one data transfer channel for performing the plurality of data transfers, wherein the transfer counting means includes a transfer counter for counting the number of transfers and a transfer number designating means. The data transfer operation is performed by using the counting operation of the transfer counter and the first register means for the data transfer of the number of times designated by the transfer number designating means, and each time the unit operation is completed, 6. The data transfer control device according to claim 4, further comprising a repeat transfer mode in which the address of the first register means and the value of the transfer counter are returned to the set values and the unit operation is repeated a plurality of times. 7. A register means and an arithmetic unit respectively connected to three parallel buses are provided, and one of the register means is provided.
7. The data transfer control device according to claim 6, further comprising a local bus for transferring one content to another register means and further to an arithmetic unit. 8. Holding means for holding an activation factor given by an external single signal for instructing the activation of the data transfer channel for performing the plurality of data transfers, is provided by the single signal. 8. The data transfer control device according to claim 2, further comprising a multi-transfer mode in which a plurality of activation factors are held in the holding means and a plurality of data are transferred via the plurality of data transfer channels. 9. A data transfer control device according to claim 1, a pulse output terminal, a first data holding means connected to the pulse output terminal, and a first data holding means. A semiconductor integrated circuit device having a pulse output means including the second data holding means and a clocking means, wherein the data transfer control device transfers data according to a signal generated by the clocking means. A semiconductor integrated circuit device capable of performing data transfer to the second data holding means and data transfer from the second data holding means to the first data holding means.