JPH0530524A - Signal processor - Google Patents

Abstract

PURPOSE:To form a video signal corresponding to an optional television(TV) system. CONSTITUTION:When this signal processor correspond to NTSC and PAL systems, 4 fsc and 16 fsc/5 are used as the sampling frequency fs of a Y signal. A timing generator 10 generates the sampling frequency fs, sampling frequency fs/4 for color difference signals R-Y, B-Y, a shift clock fSHIFT, and balance modulating carrier frequency 4fsc and the shift clock fSIFT are set up to fsc/4 and fsc/5 corresponding to the NTSC and PAL systems. At the time of correspondence to the PAL system, the timing generator 10 locks the phases of respective output signals outputted from an oscillator and a voltage control oscillator by a PLL circuit and registers 33, 34 shift respective digital collor difference signals R-Y, B-Y based upon the shift clock fSHIFT outputted from the generator 10 and supply the shifted signals to a digital balance modulator 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for processing a signal.

[0002]

2. Description of the Related Art Television signal systems currently in use are the NTSC system used in Japan and North America, the PAL system used in China and Western Europe, and the SECAM system used in Eastern Europe. It is roughly divided into methods. By the way, in the NTSC system and the PAL system, a chroma signal formed by quadrature two-phase modulation of a color subcarrier signal by two types of color difference signals is superimposed on a luminance signal (Y signal). The color subcarrier frequency fsc is 3.579545 MHz in the case of the NTSC system.
And 4.43361875MH in case of PAL system
z.

FIG. 8 is a diagram showing a schematic configuration of a conventional signal processing device for forming a composite video signal from a luminance signal and two kinds of color difference signals. In FIG. 8, the Y signal is the A / D converter 1Y at a predetermined sampling frequency fs.
Digitized in a frame memory (Mem)
It is stored in 2Y. On the other hand, the color difference signals RY and BY are
Digitized by the A / D converters 1R and 1B at arbitrary frequencies synchronized with the color subcarrier frequency fsc,
It is stored in the frame memories 2R and 2B.

In the above signal processing device, the color difference signals RY and BY are frequencies synchronized with the color subcarrier frequency fsc in the A / D converters 1R and 1B, for example, 2fsc and 4f.
Digitized at frequencies such as sc, fsc, fsc / 2,
Further, the Y signal can be digitized at an arbitrary frequency, but the Y signal is also the same in order to easily configure a controller (not shown) for controlling writing and reading of the frame memories 2Y, 2R, 2B. In addition, the A / D converter 1Y digitizes a frequency synchronized with the color subcarrier frequency fsc, such as a frequency of 4fsc or 3fsc.

Then, the digital Y signal stored in the frame memory 2Y is read out, converted into an analog signal by the D / A converter 4Y operating at the sampling frequency fs, and passed through a low pass filter (LPF) 5Y. After that, it is supplied to the adder 6 and the buffer (Buf
f) is output via 7Y and also the frame memory 2
Digital color difference signals RY stored in R and 2B,
BY is read out and balanced-modulated by the digital balanced modulator 3 operating at the sampling frequency 4fsc to form a digital chroma signal, which is converted into an analog signal by the D / A converter 4a, and then the band-pass filter. After being passed through the (BPF) 5a, it is supplied to the adder 6 and also output through the buffer 7b. Then, a signal obtained by adding the luminance signal and the chroma signal is output from the adder 6 as a composite video signal via the buffer 7a.

[0006]

However, even if an attempt is made to configure the above-mentioned conventional signal processing apparatus so as to be compatible with both the NTSC system and the PAL system, the color subcarrier frequencies fsc of both systems are greatly different. There is a problem in that it is very difficult to configure such that the sampling clocks of the same frequency are operated.

That is, when the above-mentioned device is adapted to the NTSC system, if the sampling frequency fs of the Y signal is 4 fsc (= 14.3 MHz), the horizontal resolution becomes about 500 and the frame memory 2Y stores With a capacity of 8 bits per sample, 2.8 Mbits are required. On the other hand, when this device is adapted to the PAL system, the sampling frequency fs of the Y signal is 4 fsc (= 1.
7.7 MHz), the horizontal resolution becomes about 620, and the capacity of the frame memory 2Y requires 3.5 Mbits as 8 bits per sample, so a frame with a larger capacity than that when the NTSC system is supported. The memory 2Y is required.

Therefore, in order to solve the above problems, when the Y signal is adapted to the NTSC system, for example, the Y signal is sampled at a sampling frequency of 4 fsc (14.3 MH).
z) and digitize the Y signal at a sampling frequency of 3 fsc to support the PAL system, a method of reducing the capacity of the frame memory 2Y for the PAL system is conceivable.
In this case, when the digital balanced modulator 3 is operated at a sampling frequency of 3 fsc (= 13.3 MHz) and the color difference signals RY and BY are subjected to balanced modulation processing, the digital balanced modulator 3 has √3. A circuit for calculating / 2 is required, and the circuit becomes complicated. Also, NT
In order to support both the SC system and the PAL system, the sampling frequencies should be 4 fsc and 3 fsc.
A circuit for switching with and is also required.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a signal processing device capable of forming a video signal corresponding to each of a plurality of types of television systems with a simple structure.

[0010]

In order to achieve the above object, the present invention provides a first oscillator for generating a clock for digitizing a luminance signal and two kinds of color difference signals, respectively.
A second oscillator that generates a subcarrier when the two types of color difference signals are encoded into a chroma signal, and a subcarrier that is generated from the second oscillator with respect to a clock generated from the first oscillator. A phase synchronization control circuit for synchronizing the phases of the two, and two types of color difference signals digitized according to the clock generated from the first oscillator are shifted according to the subcarrier phase-synchronized with the clock by the phase synchronization control circuit. And a shift circuit that operates.

[0011]

According to the present invention, since the two kinds of color difference signals can be digitized at frequencies other than integer multiples of the subcarrier frequency, the present invention can form a video signal compatible with any television system. it can.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of a signal processing device according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of a timing generator in the signal processing device shown in FIG. 1, and FIG. 1 is a block diagram showing a detailed configuration of a shift register in the signal processing device shown in FIG.
FIG. 5 is a block diagram showing a detailed configuration of a balanced modulator in the signal processing device shown in FIG. 5, and FIG. 5 is a diagram for explaining an operation when the signal processing device shown in FIG. 1 forms a video signal compatible with the NTSC system. Timing chart, FIG. 6, FIG.
7 is a timing chart for explaining the operation of the signal processing apparatus shown in FIG. 1 when forming a video signal compatible with the PAL system. FIG. 7 shows an example of an electronic still video reproducing apparatus to which the signal processing apparatus shown in FIG. 1 is applied. It is a block diagram showing an example of composition.

By the way, the color subcarrier frequency fsc is NT
In the case of SC system, it is 3.579545MHz, and P
In the AL system, the frequency is 4.43361875 MHz. Therefore, in the signal processing apparatus of the present embodiment, the sampling frequency fs of the Y signal is 4 fsc (= 14.31818 MHz = 14.3 MHz) in the case of the NTSC system.
16 fsc / 5 (= 14.
18758 MHz = 14.2 MHz).

In FIG. 1, the timing generator 10 is
Sampling frequency signal fs of Y signal and color difference signal R-
Y, B-Y sampling frequency signal fs / 4, shift clock fSHIFT, and frequency signal 4fsc for balanced modulation
And generate. Here, the shift clock fSHIFT is N
In the case of the TSC system, the frequency fsc / 4 (= 0.895M
Hz) clock, and in the case of the PAL system, a clock of frequency fsc / 5 (= 0.887 MHz) is used.

Then, the Y signal is converted into a digital signal by the A / D converter 11 operating at the sampling frequency signal fs and stored in the frame memory 21. That is, when operating the signal processing device so as to correspond to the NTSC system, the Y signal is digitized with the sampling frequency signal 4fsc (= 14.3 MHz),
When operating so as to correspond to the L system, the Y signal is
Sampling frequency signal 16 fsc / 5 (= 14.2 MH
z) and digitized and stored in the frame memory 21. The digital Y signal stored in the frame memory 21 is read out and the sampling frequency signal f
It is converted into an analog signal by the D / A converter 41 that operates in sc, and passes through the low-pass filter 42, and then the adder 4
3 and is output via the buffer 51.

On the other hand, the color difference signals R-Y and B-Y are A / D which operate at the sampling frequency signal fs / 4.
The signals are converted into digital signals by the converters 12 and 13 and stored in the frame memories 22 and 23. That is, when the signal processing device is operated so as to support the NTSC system, the color difference signals R-Y and B-Y are digitized by the sampling frequency signal fsc (= 3.58 MHz),
When operating so as to correspond to the PAL system, the color difference signals RY and BY are the sampling frequency signals 4fsc /
5 (= 3.62 MHz) and digitized and stored in the frame memories 22 and 23.

After the digital color difference signals RY and BY stored in the frame memories 22 and 23 are read out and shifted by the registers 31 and 32 which operate at the sampling frequency signal fs / 4, respectively. , Register 3 operating with shift clock fSHIFT
Shifted by 3, 34. That is, the color difference signals RY and BY corresponding to the NTSC system are registered in the registers 33 and 3.
4, the shift clock fsc / 4 (= 0.895 MH
z), the color difference signal R- compatible with the PAL system
Y and BY are shift clocks fsc / 5 (= 0.887).
MHz) will be shifted. Next, the digital color difference signal R- output by the registers 33 and 34
Y and B-Y are balanced-modulated by the digital balanced modulator 40 that operates with the sampling frequency signal 4fs to form a digital chroma signal, which is converted into an analog signal by the D / A converter 44, and the bandpass filter 45. Then, it is supplied to the adder 43 and output via the buffer 53. Then, the signal obtained by adding the Y signal and the chroma signal is added from the adder 43 to the buffer 52.
Is output as a composite video signal.

Next, the detailed structure of the timing generator 10 in the signal processing apparatus shown in FIG. 1 will be described with reference to FIG. In FIG. 2, an oscillator (OSC) 100
Is the sampling frequency signal fs of the Y signal, that is, the sampling frequency signal 4fsc (= when the signal processing device shown in FIG. 1 is operated so as to correspond to the NTSC system.
14.31818 MHz) and a sampling frequency signal 16 fsc when operated to correspond to the PAL system.
/ 5 (= 14.18758 MHz) is selectively output.

As described above, the signal fs output from the OSC 100 is directly supplied to the A / D converter 11 and the frame memory 21 shown in FIG. 1 and, when operating so as to correspond to the NTSC system, the signal fs shown in FIG. Sampling frequency signal 4fsc for operating the digital balanced modulator 40 of
Is output via the input terminal N of the switch 101. The signal fs output from the OSC 100 is 4
The frequency is divided into 1/4 by the frequency divider 107, and the sampling frequency signal fsc / 4 is obtained as the A / D converters 12 and 13 in FIG.
1 is supplied to the frame memories 22 and 23 and the registers 31 and 32, and when operating in accordance with the NTSC system, the registers 33 and 3 of FIG. 1 are input as the shift clock fSHIFT via the input terminal N of the switch 108.
4 is supplied.

The signal of frequency fs output from the OSC 100 is further divided by the frequency divider 102 into 1/7 or 1 /.
After being divided by 6, it is divided into 1/65 by the 65 divider 103 and supplied to the H (horizontal) decoder 104. Also, the signal divided by the 65 divider 103 is doubled by the double multiplier 105, and the H decoder 104 and the V decoder 104
It is supplied to the (vertical) counter 106. H decoder 10
4 is the V counter 1 based on the signal frequency-divided by the frequency divider 103 and the frequency-multiplied signal by the frequency doubler 105.
06 is reset and a horizontal synchronizing signal (Hsync) is output. On the other hand, the V counter 106 has a vertical synchronizing signal (Vsy
nc) is output. It should be noted that 1/7 or 1 depending on the frequency divider 102.
The signal divided by / 6 (130 fH in the figure) is supplied to an ID modulation / demodulation circuit (not shown).
After the frequency is divided into ⅕ in the modulation / demodulation circuit, it is further divided into ½ to become an ID carrier (13 fH).

The phase comparator 109 divides the signal divided by 4 by the frequency divider 107 into 1/4 and the signal divided by 5 by 1/5.
Output a signal according to the phase difference from the signal divided by 5,
This phase error signal is converted into a phase error voltage by the LPF 110. The voltage controlled oscillator (VCO) 11
1 outputs a frequency signal (4 fsc = 17.734475 MHz) controlled according to the phase error voltage to the input terminal P of the switch 101 and the frequency divider 112. 5 divider 112
Divides the signal supplied from the VCO 111 into ⅕, supplies it to the phase comparator 109, and, via the input terminal P of the switch 108, as a shift clock fSHIFT in the case of operating so as to correspond to the PAL system. Are supplied to the registers 33 and 34 of FIG. Therefore, the phase comparator 109, the LPF 110 and the VCO 111
The 5 frequency divider 112 constitutes a PLL circuit that locks the phases of the signal output from the 4 frequency divider 107 and the signal output from the 5 frequency divider 112.

The frequency divider 107 and the frequency divider 11 shown in FIG.
2 is configured as shown in FIG. 3, and divides the frequencies of the signals output from the oscillator 100 and the VCO 111 into 1/4 and 1/5, respectively, and registers 31 (and 32),
To 33 (and 34). Registers 31 and 33 are
As shown in FIG. 3, a 6-bit digital RY signal stored in the frame memory 22 of FIG. 1 per sample is input in 6-bit parallel, and a signal fs / 4 and a shift clock fSHIFT are input, respectively. To output to the balanced modulator 40 of FIG. Although not shown, the registers 32 and 34 similarly input a 6-bit digital BY signal stored in the frame memory 23 of FIG. 1 per sample in 6-bit parallel,
The signals are shifted by the signal fs / 4 and the shift clock fSHIFT and output to the digital balanced modulator 40 of FIG.

The digital balanced modulator 40 of FIG.
1 and is configured as shown in FIG.
4 digital RY signal and digital B
A selection circuit 401 for selecting the -Y signal, and the selection circuit 40
1 has a burst addition circuit 402 for adding a burst to the signal selected by 1, and a sign inversion circuit 403 for inverting the sign of the signal output from the burst addition circuit 402. Each of the circuits 401 to 403 is a 6-bit parallel circuit. Is configured to be connected to. In FIG. 4, Hc
k is a clock Hck whose phase is inverted every 1H, BF is a burst flag that defines the burst period, and N / P is NTS.
An NTSC / PAL instruction signal for instructing C compatible or PAL compatible, PF is a pedestal flag defined by a pedestal period, and BD is burst data.

Next, the operation for forming a chroma signal compatible with the NTSC system will be described with reference to FIG. First, as described with reference to FIG. 1, the color difference signals R-Y and B-Y compatible with the NTSC system have sampling frequencies f.
The signals are digitized by the A / D converters 12 and 13 at s / 4 (= fsc = 3.58 MHz) and stored in the frame memories 22 and 23, respectively. Next, the digital color difference signals RY and BY read from the frame memories 22 and 23 have the same sampling frequency fs / 4.
Are shifted by the registers 31 and 32 which operate at the same time, and are shifted by the registers 33 and 34 which operate at the shift clock fSHIFT (= fsc / 4).

In the above case, the period of each signal is as shown in FIG.
It becomes 279.4 nsec as shown in, and registers 33, 3
The time shifted by 4 is 69.8 nsec (= 1/4
fsc). The signals shifted by the registers 33 and 34 are balanced-modulated by a digital balanced modulator 40 as shown in FIG. 5C, and are (BY) and (R-
The signs are alternately inverted such as Y),-(BY), and-(RY).

Next, the operation of forming a chroma signal compatible with the PAL system will be described with reference to FIG. First,
As described with reference to FIG. 1, the color difference signals RY and BY corresponding to the PAL system have sampling frequencies fs / 4.
(= 4 fsc / 5 = 3.62 MHz) and digitized by the A / D converters 12 and 13, respectively, and stored in the frame memories 22 and 23, respectively. Next, the digital color difference signals RY and BY read from the frame memories 22 and 23 have the same sampling frequency fs / 4.
Are shifted by the registers 31 and 32 which operate at 1, respectively, and are shifted by the registers 33 and 34 which operate at the shift clock fSHIFT (= fsc / 5).

In the above case, the period of each signal is as shown in FIG.
225.5 nsec as shown in, register 33, 3
The time shifted by 4 is 56.4 nsec (= 1/4 fsc) as shown in FIG. Here, the shift clock fs / 4 of the registers 31 and 32 in the preceding stage is as shown in FIG.
Is generated by the oscillator (OSC) 100, and the shift clock fSHIFT of the registers 33 and 34 in the subsequent stage is generated by the voltage controlled oscillator (VCO) 111.
Even if the phase is locked by the L circuit, some fluctuations occur between them. Therefore, register 3 in the latter stage
3 and 34 are configured to perform sampling at the timing when the data of the registers 31 and 32 of the previous stage are fixed.

Therefore, in the above embodiment, the oscillator 10
0 generates a clock for sampling the color difference signal, the VCO 111 generates a subcarrier for encoding the chroma signal, and the oscillator 1 is generated by the PLL circuit.
00, the phase of the subcarrier output from the VCO 111 is locked, and the color difference signals sampled by the clocks output from the oscillators of the registers 33 and 34 are sublocked by the PLL circuit. By shifting by the carrier, the chrominance signal is sampled at a frequency other than an integral multiple of the subcarrier frequency and digitized, so this digital chrominance signal is encoded as a chroma signal without converting it to an analog signal. be able to. Further, since these circuits can be integrated on the same IC chip together with other digital circuits, they can be realized as highly reliable circuits that are resistant to temperature fluctuations and the like.

FIG. 7 is a block diagram showing an example of the configuration of an electronic still video reproducing device to which the signal processing device shown in FIG. 1 is applied. In FIG. 7, the frame memories 21, 22, 23 shown in FIG. 1 are omitted, and the same components as those in FIG. 1 are designated by the same reference numerals. In FIG. 7, the video floppy disk 60 loaded in the apparatus is rotated at a predetermined rotational speed by the spindle motor 61, and the video signal recorded on the video floppy disk 60 is reproduced by the head 62. After the reproduced video signal is amplified by the amplifier 63, the luminance signal component YFM and the color signal component CFM are respectively HPF 64 and B.
It is extracted by PF65. The luminance signal component YFM and the chrominance signal component CFM are generated by demodulators 66 and 67, respectively
The signal is demodulated and further de-emphasized by the de-emphasis circuits 68 and 69 to restore the luminance signal Y and the color difference line sequential signal RY / BY.

The luminance signal Y is digitized by the A / D converter 70 at the sampling frequency fs as described with reference to FIG. 1, and then, via the 1/2 delay line 71,
Skew compensation is performed by switching the skew gate switch 72 to which the 1 / 2H delayed signal and the undelayed signal are supplied every one field period in accordance with the skew gate signal, and is analogized and output by the D / A converter 41. It On the other hand, color difference line sequential signal RY / B
-Y is digitized in the A / D converter 73. Then, the color difference line sequential signals R-Y / B-Y digitized by the A / D converter 73 are converted into the 1/2 delay line 75.
Skew compensation is performed by switching the skew gate switch 76, which is supplied with a signal delayed by 1 / 2H and a signal not delayed by 1/2, for each field period in accordance with the skew gate signal, and then by the 1H delay line 77. The signal delayed by 1H and the signal not delayed by 1H are synchronized by switching the gate switch 78 according to the discrimination signal output from the color ID discrimination circuit 74, and output as digital RY and BY signals. It Then, the digital RY and BY signals are supplied to the registers 31 and 32. Hereinafter, as described in FIG. 1, the Y signal, the chroma signal, and the composite video signal are formed and output. In the embodiment shown in FIG. 7, the 1/2 delay line 71 operates at the sampling frequency fs output from the timing generation circuit 10 shown in FIG. 1, and the 1/2 delay line 75 and the 1H delay line 77 are , Sampling frequency f output from the timing generation circuit 10
It is configured to operate at s / 4.

[0031]

As described above, according to the present invention, a first oscillator for generating a clock for digitizing a luminance signal and two kinds of color difference signals respectively, and the two kinds of color difference signals as chroma signals. A second oscillator for generating subcarriers for encoding; a phase synchronization control circuit for synchronizing the phase of the subcarriers generated by the second oscillator with a clock generated by the first oscillator; ,
Since it has a shift circuit that shifts two types of color difference signals digitized according to the clock generated from the first oscillator according to subcarriers that are phase-synchronized with the clock by the phase synchronization control circuit, two types of color difference signals are provided. The color difference signal can be digitized at a frequency other than an integer multiple of the subcarrier frequency, and thus a video signal compatible with an arbitrary television system can be formed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing device according to the present invention.

2 is a block diagram showing a detailed configuration of a timing generator in the signal processing device shown in FIG.

3 is a block diagram showing a detailed configuration of a shift register in the signal processing device shown in FIG.

4 is a block diagram showing a detailed configuration of a balanced modulator in the signal processing device shown in FIG.

5 is a timing chart for explaining an operation when the video signal corresponding to the NTSC system is formed by the signal processing device shown in FIG.

FIG. 6 is a timing chart for explaining an operation when the video signal corresponding to the PAL system is formed by the signal processing device shown in FIG.

7 is a block diagram showing a configuration example of an electronic still video reproducing device to which the signal processing device shown in FIG. 1 is applied.

FIG. 8 is a block diagram showing a schematic configuration of a conventional signal processing device that forms a composite video signal from a luminance signal and two types of color difference signals.

[Explanation of symbols]

 10 Timing Generator 11-13 A / D Converter 21-23 Frame Memory 31-34 Register 40 Digital Balance Modulator 100 Oscillator (OSC) 111 Voltage Controlled Oscillator (VCO) 109-111 PLL Circuit

Claims (1)

Claim: What is claimed is: 1. A first oscillator for generating a clock for digitizing a luminance signal and two kinds of color difference signals respectively, and a first oscillator for encoding the two kinds of color difference signals into a chroma signal. A second oscillator that generates subcarriers; a phase synchronization control circuit that synchronizes the phase of the subcarriers generated from the second oscillator with a clock generated from the first oscillator; And a shift circuit for shifting two kinds of color difference signals digitized according to a clock generated from the oscillator according to a subcarrier phase-synchronized with the clock by the phase-lock control circuit. ..