JPS63260387A - Reproducing device for pal system color video signal - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by using a frequency converting circuit applying high frequency conversion to a low frequency conversion chrominance carrier signal in a color video signal to PAL system and restoring it into the original chrominance carrier signal in common use with a frequency converting circuit obtaining the polarity of the V axis signal of the obtained chrominance carrier signal and the inverted polarity. CONSTITUTION:The low frequency conversion carrier chrominance signal in the color video signal of the PAL system reproduced by the 1st and 2nd frequency conversion circuits 45, 53 is subject to high frequency conversion and restored into the original chrominance carrier signal and the V axis signal component with the original polarity and the inverted polarity of the chrominance carrier signal obtained through high frequency conversion are obtained. Thus, it is possible to replace frequency conversion circuit in a conventional VTR into noninverting and inverting frequency converting circuits 71, 72 and the C signal processing is attained with very simple processing by using a signal being the result of 1/4 frequency division of the output of the clock signal generating circuit 64 with the use of 4fsc clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reproducing apparatus for PAL color video signals, and more particularly to a reproducing apparatus equipped with a frequency conversion circuit for axis stop and inversion.

[Summary of the invention]

The present invention provides a PAL color video signal including a low-pass converted carrier color signal obtained by low-pass converting a carrier color signal in which a subcarrier having a frequency of fsc is modulated with a color signal so that the carrier frequency becomes fc. In a playback device that plays back the frequency f3
．． fz are respectively fl', fsc+rc and f2-fsc-
Frequency conversion signals with frequencies fl and f2 are generated, respectively, and the low frequency conversion carrier color signal is converted to a high frequency signal, and the polarity of the axis signal component included in the carrier color signal is changed. Obtain first and second carrier color signals that are opposite to each other, and make these 1! By selecting the i-transmission false color signal based on a signal that determines odd or even lines,
A frequency conversion circuit for high-frequency converting the low-frequency converted carrier color signal in the reproduced PAL color video signal and returning it to the original carrier color signal, and a carrier color signal obtained by high-frequency conversion. (1) Using a frequency conversion circuit to obtain the polarity of the axis signal component with the same polarity and with the polarity reversed,
This is intended to simplify the circuit configuration.

[Prior art] Conventional PAL VTRs do not have a built-in TBC (time base collector), so they convert color video signals obtained from a rotating magnetic head into FM luminance signals and low frequency conversion carrier color signals. The FM luminance signal is FM demodulated into a luminance signal, the low-frequency converted carrier color signal is high-frequency converted and returned to the original carrier color signal, and the luminance signal and the high-frequency converted carrier color signal are synthesized to obtain a signal. The PAL color video signal is transferred to VTR.
The time axis M difference was corrected by supplying it to a separate rBC.

In this °rBC, PAL with time axis error correction
A synchronization signal synchronized with a reference color video signal and a color burst signal are added to the color video signal of the system.

By the way, the phase of the vIMl signal component of the carrier color signal of a PAL color video signal is reversed for each line, and correspondingly, the phase of the color burst signal is also +135° and -135° for each line. are changing alternately.

Therefore, when adding a synchronization signal and a color burst signal that are synchronized to a reference color video signal to a PAL color video signal that has been corrected for time axis errors, the phase of the color burst signal to be added is +135°. , -135°
It may be necessary to invert the polarity of the V-axis signal component of the carrier color signal depending on whether
A circuit is provided for obtaining a carrier color signal with the polarity of the V-axis signal component unchanged and with the polarity reversed, and a switch for switching between the two carrier color signals depending on whether the line is odd or even.

Below, with reference to FIG. 2, such a conventional PAL VTR and a TBC used in connection therewith will be explained. In FIG. 2, (2) indicates a VTR,
(3) indicates TBC.

First, VTR(2) will be explained. A PAL color video signal reproduced from the tape by a rotating magnetic head is supplied to the HPF and LPF, respectively, and F M
Luminance signal (1' [signal)] and reproduction low-pass conversion carrier color (No. 6 (
The signal is separated into C'-fold signals. FM from input terminal (4v)
-Y signal is subjected to FM fjt modulation in the FM demodulation circuit (5) to form a luminance signal (Y signal), which is supplied to the first addition circuit (12) through the first delay circuit (7). The C'-times signal from the input terminal (4C) is amplitude-adjusted by the first automatic chroma adjustment circuit (ACC) (6), and then supplied to the first frequency conversion circuit (8). C' in PAL system
The frequency is lower-converted to the double signal carrier frequency [C-924KIlz.

The output of the first voltage controlled oscillator (VCO), (9)
The signal is supplied to the frequency conversion circuit (8) and converted to a low frequency C′ multiplied signal with a frequency of 9241 Hz, and the original color subcarrier frequency is converted to a high frequency carrier color signal (C signal) of 4.43 MHz. Ru. For this purpose, the color subcarrier frequency fsc is set to 4 in the standard subcarrier generation circuit (11) consisting of a crystal oscillator, etc.
．． A subcarrier of 43111z is generated and supplied to the first phase comparison circuit (10). This first phase comparison circuit (1
The C signal from the first frequency conversion circuit (8) is supplied to V CO (9), the phase of the burst signal in the C signal is compared with the subcarrier, and a control signal according to the phase difference is sent to V CO (9). APC control is performed by controlling the oscillation frequency of the first VCO (9). ! The output of the frequency conversion circuit (8) of 81 is supplied to the first addition circuit (12) and is added to the Y signal to form a signal ((Y+C) signal), and this (Y+C) signal is T B C (3) L)'
It is supplied to F(13).

In 'l' B C (3), in order to facilitate time axis correction, the (Y + C) signal is reseparated into Y signal and C signal by LPF (13) and first BPF (14), respectively. The Y signal separated by the LPF (13) is sent to the first A/D.
The signal is supplied to a conversion circuit (15) and a clock generation circuit (16). The Y signal input to the clock generation circuit (16) includes a jinter component, and a clock signal CK of a predetermined frequency is generated based on the horizontal synchronization signal in the Y signal, and this clock signal GK is input to the Y signal memory. Circuit (23), first
A/D conversion circuit (15), 1/2 frequency divider circuit (21A)
and is supplied to the 1/8 frequency divider circuit (22). 1st A/
In the D conversion circuit (15), the Y signal is A/D converted by the clock signal, and the resulting digitized Y signal (0-v
The signal N is supplied to the next stage memory circuit (23), and writing is performed using the clock signal CK.

-10,000, the C signal separated by the first BPF (14) is
frequency conversion circuit (17) and a second phase comparison circuit (17).
8). The output signal from the second VCO (19) is supplied to the second phase comparison circuit (18), and a phase comparison is made between the burst signal in the C signal and the output signal of the second VCO (19). The phase difference signal is transmitted to the second VCO (19
), its oscillation frequency is controlled, and the oscillation signal is supplied to the third frequency conversion circuit (20). The third frequency conversion circuit (20) includes a 1/8 frequency divider circuit (22
), a clock signal CK1 having a frequency obtained by dividing the clock signal CK by 1/8 is supplied. The output of the first frequency signal generation circuit (20) is supplied to the second frequency conversion circuit (17). In the second frequency conversion circuit (17), 4.
The C signal converted into a field having a color subcarrier frequency of 43 Mflz is sent to the second A/D conversion circuit (24
/D conversion to an appropriate frequency f x KHz that is easy to perform. For this reason, the first frequency signal generation circuit (20) uses 4.
A conversion signal having a frequency of 43 MHz to f x KHz is frequency-converted and extracted.

The C signal converted to a frequency of f x KHz is supplied to the second A/D conversion circuit (24), and the frequency of the clock signal CK is divided by 1/2 by the 1/2 frequency divider circuit (21A). A/D conversion is performed using the clock signal CK2, and this conversion output (low C signal) is supplied to the memory circuit (26).
It is written using clock signal CK2. Memory circuit (23) for Y signal and C signal.

The successive outputs of (26) are supplied to first and second D/A conversion circuits (25) and (28). 1st D
/A conversion circuit (25) and Y signal memory circuit (23)
) is supplied with the clock signal GK3 from the uterine organ O8C, and the D- signal stored in the memory circuit (23) for the Y signal is supplied to
The Y signal is read out using the clock signal CK3.

On the other hand, the C signal memory circuit (2
6) and the second D/A conversion circuit (28), a clock signal CK4 obtained by dividing the clock signal CK3 from O20 into 1/2 by a 1/2 frequency divider circuit (21B>) is supplied. The D-C signal stored in the C signal memory circuit (26) is read out using the clock signal CK4.

The output of the first D/A conversion circuit (25) is made into the original analog Y signal, which is delayed by the second delay circuit (27),
It is supplied to the second adder circuit (29).

The output of the second D/Am conversion circuit (28) is converted into the original analog C signal with a frequency of f x KHz, and is converted to the original 4.0 KHz through a frequency conversion circuit for normal rotation and 9 inversion of the V-axis signal component, which will be described later. A C signal having a 43MH2O color subcarrier frequency is formed and supplied to the second adder circuit (29). In the second addition circuit (29), the Y signal and the C signal are added together again, and the output processing circuit (30) outputs the burst signal and synchronization signal of the reference external video signal, which will be described later, to be supplied to the input terminal 'rz. A synchronized reference burst signal and a reference synchronization signal are added to output a composite video signal to output terminals 1 and 3.

Hereinafter, a frequency conversion circuit for normal rotation and one inversion of the {circle around (2)} axis signal component, which is connected to the output of the second D/Am conversion circuit, will be described.

■The frequency conversion circuit for normal rotation of the axis signal component consists of a third frequency conversion circuit (31), a third VCO (33), and a third phase comparison circuit (34), and the frequency conversion circuit for normal rotation of the V-axis signal component The conversion circuit includes a fourth frequency conversion circuit (35) and a fourth frequency conversion circuit (35).
It is composed of a CO (36) and a fourth phase comparison circuit (37).

The C signal output from the third frequency conversion circuit (31), to which the output signal of the second D/A conversion circuit (28) is supplied, is supplied to the fixed contact of the switch circuit SW.
4), from the fourth frequency conversion circuit (35) which is also supplied to the line odd-even coincidence determination circuit (32), and which is also supplied with the output signal of the second D/A conversion circuit (28). C
The signal output is supplied to the fixed contact C of the switch circuit SW and the fourth phase comparison circuit (37). A reference external video signal is supplied from the input terminal T1 to the line odd/even coincidence judgment circuit (32), and the judgment output causes the switch circuit S
The contact piece a of W is switched to the fixed contact or C side, and the output of either the third or fourth frequency conversion circuit (31) or (35) is supplied to the second addition circuit (29). Third
And the fourth phase comparison circuit' (34) and (37) receive the reference color subcarrier frequency tsc= from the input terminal T3.
A 4.43 MHz subcarrier signal is supplied and each comparison output is sent to the third and fourth VCOs (33) and (36).
2 will be supplied. The third VCO (33) has a subcarrier signal of fj9C and a frequency f x KHz of the analog C signal.
oscillates a signal with a frequency of fsc+fx, which is the sum of
). The fourth VCO (36) oscillates a signal with a frequency of fsc-fx obtained by subtracting the subcarrier signal of Esc and the frequency f x KHz of the analog C signal, and converts the converted signal of this frequency into a fourth frequency conversion circuit. (35).

With this configuration, a C signal in which the {circle around (2)}-axis signal component is inverted in the normal direction is obtained on the fixed contact side of the switch circuit SW, and a C signal in which the ■-axis signal component is inverted is obtained in the fixed contact C side.

[Problem that the invention seeks to solve]

In the above-mentioned conventional configuration, the VTR and 'l' BC are separated into separate devices, and in particular, in the rHC for the PAL system, a frequency conversion circuit (for normal rotation of the V-axis signal component) is used to process the C signal.
31), (33), (34) and a frequency conversion circuit for inverting the V-axis signal component (35), (36)
.

(37), and also a frequency conversion circuit (8) for converting the low frequency conversion color signal to the high frequency within the VTR.

+9), (10), (11) etc. are required,
Frequency conversion circuit (17), (1B), (19) that converts C signal to low frequency for inputting to TBC
, (20) and other complicated processing circuits are required.

The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to perform high-frequency conversion of the low-frequency converted carrier color signal in the reproduced PAL color video signal to the original carrier color signal. A frequency conversion circuit for converting the frequency back and a frequency conversion circuit for obtaining a carrier color signal obtained by high-frequency conversion with the polarity of the V-axis signal component unchanged or inverted, The object of the present invention is to propose a PAL color video signal reproducing device with a simple circuit configuration.

[Means for solving problems]

In the present invention, a carrier color signal formed by modulating a subcarrier with a frequency fsc with a color signal has a carrier frequency fc (<fsc
), the frequency f1 is approximately (f sc + f c
) and a first frequency conversion signal generation circuit (48) that generates a first frequency conversion signal whose frequency f2 is approximately (fHc
-fc), a second frequency-converted signal generation circuit (56) that generates a second frequency-converted signal, and a regenerated PAL
A low frequency conversion carrier color signal in a color video signal of the system is inputted, and is converted to a high frequency signal by a first frequency conversion signal,
A first frequency conversion circuit (45) that obtains a first carrier color signal
Then, the low-frequency converted carrier color signal in the reproduced PAL color video signal is input, is converted to a high frequency signal by the second frequency conversion signal, and is converted into the ■axis signal included in the first carrier color signal. a second frequency conversion circuit (53) for obtaining a second carrier color signal having a V-axis signal component with a polarity opposite to that of the component; Equipped with a discrimination circuit (61) that discriminates whether the phases of color burst signals match, and a switch circuit S W 1 that selectively outputs first and second carrier color signals based on the output of the discrimination circuit (61). It is made up of

[Effect]

According to the PAL color video signal reproducing apparatus of the present invention, the first and second frequency conversion circuits (45).

(53), the low-band converted carrier color signal in the reproduced PAL color video signal is high-band converted and returned to the 9 carrier color signal, and the carrier color signal obtained by high-band conversion It is possible to obtain a signal with the polarity of the (1) axis signal component unchanged or with the polarity reversed.

〔Example〕

Hereinafter, one embodiment of the reproducing apparatus of the present invention will be described in detail with reference to FIG.

FIG. 1 shows a PAL system VTR (40) as a whole. In FIG. The FM-Y signal from the input terminal (41Y) is separated into the reproduced low-frequency conversion carrier color signal (FM-Y signal) and the reproduction low-frequency conversion carrier color signal (C'-fold signal.The FM-Y signal from the input terminal (41Y) is
) is FM demodulated and converted into a luminance signal (Y signal), and the third
through the delay circuit (44) of the third adder circuit (62).
supplied to

The second automatic chroma amplitude adjustment circuit (ACC) receives the C' multiplied signal from the input terminal (41C), adjusts the amplitude with (43), and converts the frequency conversion circuit (71) for normal rotation of the axis signal component.
and a fifth frequency conversion circuit (45) constituting a frequency conversion circuit (72) for inverting the ■-axis signal component, and a sixth frequency conversion circuit (53).

Fifth and sixth frequency conversion circuits (45), (53
), carrier frequency f c =
It is converted to a low frequency of 924KHz. The fifth and sixth frequency conversion circuits (45) and (53) have a frequency of 9
24) [l1z(7) If the C' signal has a carrier frequency of 4.
The second signal is converted to a high frequency conversion color signal (C signal) of 43MHz.
and a third BPF (46).

The 4.43 MHz C signal is taken out through (54) and supplied to the fixed contacts (i) and (c) of the switch circuit SWI.

The contact a of the switch circuit SWL is supplied with an external video signal from the input terminal 'rt to the 0 discrimination circuit II (61) in which switching and selection is performed by the output of the line odd-even coincidence discrimination circuit (61). The output of the first BPF (46) is input, and these are compared to determine if the lines are odd or even. As will be described later, the second BPF (46)
A carrier color signal in which the V-axis signal component is normally rotated is taken out from the 3rd BPF (54), and a carrier color signal in which the ■-axis signal component is inverted is taken out from the third BPF (54). Switch circuit SW by switching to fixed contact or C side
The Crfi signal obtained by inverting or not inverting the ■-axis signal component is taken out as the output of No. 1, and is sent to the third adder circuit (
62). The third adder circuit (62) adds the C signal whose polarity of the ■-axis signal component changes for each ° line and the Y signal, and supplies the result to the third A/D conversion circuit (63). Digitized by the A/D conversion circuit (63) (C+
The Y) signal is stored in a memory circuit (66) for the (C+Y) signal.

Clock signal generation circuit and phase-locked loop circuit (GK-
PLL (64) is connected to the output side of the third delay circuit (44) and supplied with the Y signal. GK・PLL (64)
Then, the frequency is 4 from the synchronization signal H including jitter in the Y signal.
The clock signal CK s of f sc is activated. 1′
6], a phase-locked loop (P L
In the PAL system, when determining the color subcarrier frequency, tsc = (284-1/4)
f H + f M /625, and the correction term f H/625-25Hz in this equation is to make the dot interference of the color subcarrier in the screen less noticeable. 25Hz offset is also obtained at the same time, and the frequency is 4 f sc-4X 4.433
The 618.75Hz clock signal CKs is sent to the A/D conversion circuit (63), the TBG memory circuit (66), and the 1z
The (C+Y) signal supplied to the 4 frequency divider circuit (65) and A/D converted by the clock signal CKs is used as the clock signal to be written into the memory circuit (66). In the 1z4 frequency divider circuit (65), a clock (i
'1iJ-cK, divided by 1/4, the frequency is rsc
The clock signal of
phase shifters (52), (60) and seventh and eighth phase comparison circuits (52), (60).

The oscillator (67) generates a read clock signal, supplies this read clock signal CKs to the memory circuit (66) and the D/A conversion circuit (68), and supplies the read clock signal CKs to the memory circuit (66).
The digital (C+Y) signal read out from the converter is converted into an analog (C+Y) signal and supplied to the fourth adder circuit (70) through the output processing circuit (69). In the fourth adder circuit (70), the input terminal 'I'2 is supplied with,
A reference burst signal and a reference synchronization signal synchronized with the color burst signal and synchronization signal of the external reference color video signal are added, and the composite video signal is output to the output terminal T.
3 is output.

With the above configuration, the frequency conversion circuit for normal rotation of the V-axis signal component (7
1) and the frequency conversion circuit (72) for inverting the axis signal component (2) will be explained in more detail. As mentioned above, the C' spear number from the second ACC (43) is connected to the fifth and sixth frequency conversion circuits (45), (53) and the second and third BPF.
Switch circuit SWI through (46) and (54)
is supplied to the second and third BPF (46),
The C signal containing jitter with a frequency of 4.43MH2 output from (54) is the 5th. Seventh phase comparator circuit (50
), (51) and 6th. Eighth phase comparison circuit (5
B), (59) and the burst signal in the C signal supplied to the seventh and eighth phase comparator circuits (51), (59) is also supplied to the 174 frequency divider circuit (65).
It is compared with a reference subcarrier signal having a color subcarrier frequency of f sc supplied from the subcarrier signal, and outputs an output according to the phase difference! 181 and the second phase chic (52).

(60), phase thick (52), (6
A subcarrier signal of 4.43 MHz whose phase is controlled by
56) Also ff15 and the sixth phase comparator circuit (50)
, (5B).

Fifth and sixth phase comparison circuits (50), (5B)
Now, the phase of the burst signal of the C signal which is the output of the BPF (46) and the first and second phase shifters (52).

The phases of the 4 and 43 MH2 color subcarrier signals whose phases have been controlled by (60) are compared, and the error signals are transferred to the fifth and sixth (
7) Supply VCO (49) and (57). In the fifth and sixth VCOs (49) and (57), 9
Generates a reference oscillation signal of 241Hz, which is used by the first and second frequency signal generation circuits (4B), (56)
supplied to

The first frequency signal generation circuit (48) generates a signal based on the 4.43M)lx subcarrier signal from the first phase shifter (52) and the 924Hz oscillation signal from the fifth VCO (49). So, f sc + f c = 4.43MHz
+924KHz-5,351'lHz frequency conversion is performed and gjS5 is converted through the fourth BPF (47).
A conversion signal of 5.353'lHz is supplied to the frequency conversion circuit (45).

The second frequency signal generation circuit (56) receives the 4.43 MHz color subcarrier signal from the second phase shifter (60) and the (D924 KHz (D)) from the sixth (7) VCO (57).
Based on the signal, f sc −f c = 4.431
'lHz - 924 KHz = 3.5 MHz frequency conversion is performed, and a 3.5 MHz conversion signal is supplied to the sixth frequency conversion circuit (53) through the fifth BPF (55).

As mentioned above, according to the configuration shown in Fig. 1, the conventional 17) shown in Fig. 2
VTR (frequency conversion circuit (8) in 21, (9
), (10).

(11) is converted into a frequency conversion circuit (71) for normal rotation and one inversion.
.

(72), and by using a 4fsc clock signal as the clock signal generation circuit (64) for C signal processing, the output of this clock signal generation circuit (64) can be divided into 1/4. Using this, we were able to construct an extremely simple processing circuit.

(Effects of the Invention) Since the present invention is configured as described above, the frequency at which the low-pass converted carrier color signal in the reproduced PAL color video signal is high-pass converted and returned to the original carrier color signal is a conversion circuit;
The circuit configuration is simplified by using a frequency conversion circuit for obtaining the polarity of the V-axis signal component of the carrier color signal obtained by high-frequency conversion, with the polarity unchanged or with the polarity inverted. Accordingly, it is possible to obtain a reproducing apparatus for PAL color video signals.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an embodiment of the reproducing apparatus of the present invention, and FIG. 2 is a system diagram of a conventional reproducing apparatus. -, (40) is a VTR, (71) is a frequency conversion circuit for normal rotation of the V-axis signal component, and (72) is a frequency conversion circuit for inversion of the -axis signal component.

Claims (1)

[Claims] A carrier color signal formed by modulating a subcarrier with a frequency of f_s_c with a color signal has a carrier frequency of f_c (<f_s_c
), a first frequency-converted signal whose frequency f_1 is approximately (f_s_c+f_c); a first frequency-converted signal generation circuit that generates a second frequency-converted signal whose frequency f_2 is approximately (f_s_c-f_c); a first frequency conversion circuit that receives the low frequency converted carrier color signal in the color video signal and converts it to a high frequency signal using the first frequency converted signal to obtain a first carrier color signal; The low frequency converted carrier color signal in the converted PAL color video signal is input, and is converted to a high frequency signal by the second frequency converted signal to produce a V-axis signal included in the first carrier color signal. a second frequency conversion circuit for obtaining a second carrier color signal having a V-axis signal component having a polarity opposite to that of the component; and a phase of a color burst signal of the first or second carrier color signal and a reference color burst. A PAL comprising: a discrimination circuit that discriminates whether the phases of the signals match; and a switch circuit that selectively outputs the first and second carrier color signals based on the output of the discrimination circuit. color video signal reproducing device.