JPS623591A - Color video signal reproducing device - Google Patents

Abstract

PURPOSE:To perform both of the time base correction and the phase correction of a carrier chrominance signal after a frequency conversion with performing simultaneously the phase correction by detecting the time base fluctuation of a low-pass conversion chrominance signal from its burst phase and performing the time base correction with the state of the low-pass conversion chrominance signal. CONSTITUTION:The mixing wave of a modulation luminance signal and the low-pass conversion chrominance signal from a terminal 1 is respectively separated at a Y/C separator 12 and as for the low-pass chrominance signal, the burst portion of the low-pass conversion chrominance signal CL, after passed through an ACC amplifier 7, is taken out at a burst gate 18 and is supplied to the one input of a phase comparator 19. To the other input of the phase comparator 19, a low-pass conversion carrier generated from the oscillating output of a voltage control oscillator (VCO) 22 by a dividing process at a carrier generating circuit 23 is supplied. The phase comparator 19 performs the phase comparison between the burst portion of the low-pass conversion chrominance signal CL and the generate low-pass carrier. Following that, the oscillation phase of the VCO22 is controlled so that the low-pass conversion carrier, from the carrier generating circuit 23, which is inputted to the phase comparator 19 is synchronized with the burst portion of the low-pass conversion chrominance signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to a video tape recorder (hereinafter referred to as VTR) or a video disc (hereinafter referred to as VD), etc., in which an FM-modulated luminance signal and a low frequency-converted carrier chrominance signal are The present invention relates to a color video signal reproducing device that can be effectively used to convert multiplexed and recorded signals into standard television signals during reproduction.

Conventional technology In recording media on which color video signals are recorded at high density, such as the magnetic tape of a video tape recorder or the disc of a video disk, an FM-modulated luminance signal and a low-frequency-converted carrier color signal are usually frequency-multiplexed and recorded. ing.

For example, when recording an NTSC color video signal on a VH3 color VTR, the color subcarrier frequency is fsc (= 3.58 MHz). The signal is frequency-converted to a low-frequency converted color signal (629 KHz), mixed with an FM-modulated modulated luminance signal, and recorded on a magnetic tape. To reproduce the signal recorded on the magnetic tape, the low frequency conversion color signal in the reproduced signal extracted from the magnetic head is inversely converted to the original carrier color signal, and the modulated luminance signal is demodulated to the demodulated luminance signal. Then, a color video signal is obtained by adding it to the inversely transformed carrier color signal.

A conventional example of a color video signal reproducing apparatus that performs reproduction processing among the above-mentioned recording and reproduction processing will be described below with reference to the drawings.

FIG. 5 is a system diagram of a color video signal reproducing device for inputting signals reproduced from a tape through terminal 1 and converting them into original signals for color television.6 The signals recorded on the tape are As shown in Figure 6, the low frequency conversion color signal CL
(In the case of a VHS system VTR, the carrier frequency wave fc = 6
29K HZ) and FM-modulated modulated luminance signal YFM
It is a mixed wave of The mixed wave is reproduced by a magnetic head and inputted from terminal 1, and the modulated luminance signal is output to the HPF.
(bypass filter) 2, and the low frequency conversion color signal is separated by LPF (low pass filter) 3. The modulated luminance signal separated by the HPF 2 is supplied via the limiter 4 to the FM demodulator 5 as a modulated luminance signal YF1j that can be demodulated, and then unnecessary components are removed by the LPF 6 to become the demodulated luminance signal Y. The low-pass converted color signal separated by the LPF 3 becomes a low-pass converted color signal CL with level fluctuations removed by the ACC amplifier 7, and is supplied to the multiplier 8, and the frequency-converted output is passed through a BPF (band pass filter).
9, the original carrier frequency fsc(N
In the case of the TSC method, a carrier color signal Csc of 3.58 MHZ') is obtained. The demodulated luminance signal Y and the carrier color signal C
sc is mixed in an adder 10, and as a result, a color video signal is obtained at an output terminal 11.

In rotary head type VTRs, the signals reproduced from the tape have time axis fluctuations due to expansion and contraction of the tape and jitter of the rotating cylinder.In particular, when reproducing the carrier color signal, the subcarrier in the reproduced carrier color signal C5C Since the phase of the carrier color signal C8c itself is shifted, the hue of the reproduced screen is shifted. Therefore, during frequency conversion in the multiplier 8, a carrier wave (frequency is fsc+fc=4.2MHZ in the case of VH3 system) having the same amount of variation as the phase variation of the low-pass converted color signal Ct is converted into AFC/APC (
AFC and APC circuits) 12 are used to frequency-convert the low frequency converted color signal Ct using the carrier wave to cancel the phase fluctuation of the reproduced carrier color signal esc (for example, -29676).

Problems to be Solved by the Invention However, in the above configuration, the time axis variation of the luminance signal Y is not corrected, and the carrier color signal esc
Also, only the carrier phase is corrected, and the time axis variation is not essentially removed. Furthermore, the carrier color signal es is
Since the carrier frequency of c has no time axis variation, the frequency interleave relationship between the demodulated luminance signal Y and the carrier color signal esc is disrupted, leading to deterioration of the image quality on the television screen. Also,
Both the demodulated luminance signal Y and the low frequency conversion color signal Csc are essentially not corrected for time axis fluctuations, so if you repeat dubbing from tape to tape on a VTR, the time axis fluctuations will be added and the image quality will further deteriorate. .

In order to remove such time axis fluctuations, time axis fluctuations are removed through a time axis fluctuation compensator (hereinafter referred to as TBC). If time axis correction is applied to a signal that has been corrected only for the carrier phase, on the contrary, the carrier phase will have a phase fluctuation and a hue shift will occur on the reproduced screen.

The present invention solves the above-mentioned problems, and is capable of reproducing the luminance signal Y and the carrier color signal esc without destroying the frequency interleave relationship, and correcting the time-axis fluctuations of each reproduced signal, thereby correcting the hue fluctuations. The present invention provides a color video signal reproducing device with little deterioration in image quality.

Means for Solving the Problems In order to solve the above problems, the color video signal reproducing apparatus of the present invention uses a Y/ C separator;
a time axis having at least one address generation circuit that generates an address having the same time axis error as the mixed wave from the two storage circuits and the recording medium, and an address generation circuit that operates with a reference clock; a corrector;
The control clock for the address generation circuit, which is equipped with a frequency converter and an adder and generates an address with the same time axis error as the mixed wave, is created from a burst of the low frequency converted color signal, and the mixed wave is After separation by the C separator, the luminance signal is demodulated by the FM demodulator and the time axis is corrected by the time axis corrector, and the low frequency conversion color signal is subjected to time axis correction by the time axis corrector. A frequency converter converts it into a carrier color signal of a predetermined carrier frequency, and an adder adds the demodulated luminance signal after time axis correction and the frequency-converted carrier color signal to obtain a color video signal. .

The present invention has a sophisticated configuration, and as a method for correcting the hue shift that occurs on a television screen due to the time axis variation of the carrier color signal Cs, conventionally, the phase variation of the carrier wave applied to the frequency converter is reduced. In contrast, the phase fluctuation of the frequency-converted carrier color signal esc was corrected by controlling the carrier of the range-converted color signal CI4 to be the same as the phase fluctuation caused by time axis fluctuation.
By performing time axis correction in the state of the low-pass converted color signal C, phase fluctuations of the low-pass converted color signal CL are removed.
The demodulated luminance signal Y is also subjected to the same time axis correction processing as the low frequency conversion color signal CL. Then, by setting the frequency of the carrier wave so that the color subcarrier frequency of the carrier color signal after frequency conversion has an appropriate value with respect to the horizontal frequency of the demodulated luminance signal after time axis correction, and applying it to the frequency converter, In addition to correcting the carrier phase of the carrier color signal as before, it also makes it possible to reproduce a color video signal that is close to the actual television broadcast wave and maintains the frequency interleaving relationship between the carrier color signal and demodulated luminance signal. There is. Furthermore, by performing time axis correction on the demodulated luminance signal, it is also possible to prevent image quality deterioration due to time axis fluctuations in tape playback signals during dubbing operations of conventional VTRs.

Embodiment A color video signal reproducing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a system diagram of a color video signal reproducing apparatus according to an embodiment of the present invention.

In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and redundant explanation will be omitted. In Figure 1, 12
is a Y/C separator, and HPF2 and LP of the conventional example shown in FIG.
It has the same function as F3. 13.14 is a memory circuit, +5°16 is an address generation circuit, and 17 is a horizontal synchronization separation circuit.

18 is a burst gate, 19 is a phase comparator, 20 is an adder, 21 is an LPF, 22 is a voltage controlled oscillator (VCO)
, 23 is a carrier generation circuit, 24 is a frequency comparator, 25
is an XCO (crystal oscillator), 26 is a synchronization signal generation circuit, and 27 is a carrier generation circuit.

In the color video signal reproducing device according to one embodiment of the present invention configured as described above, first, a mixed wave of a modulated luminance signal and a low-frequency conversion color signal from the terminal 1 is separated by the Y/C separator 12, and then modulated. After passing through the limiter 4, the luminance signal is supplied to the FM demodulator 5 as a modulated luminance signal YFM that can be demodulated, and after passing through the LPF 6, it is supplied to the storage circuit 13 as a demodulated luminance signal Y. On the other hand, after passing through the ACC amplifier 7, the low frequency converted color signal is supplied to the storage circuit 14 as a low frequency converted color signal cL with level fluctuations removed.

The memory circuits 13 and 14 are analog shift registers such as COD or digital shift registers that can store data of 3H or more (LH is the horizontal same period), or analog memory or digital data that can be randomly accessed and has a storage capacity of IH or more. It consists of RAM (Random Access Memory) that handles
An A/D converter is required before, and a D/A converter is required after. FIG. 2 shows the input/output and waveforms of each part in the memory circuits 13 and 14 of FIG. 1.

The method for creating write addresses for memory circuits 13 and 14 is as follows:
For example, the burst portion of the low frequency converted color signal OL after passing through the ACC amplifier 7 is taken out by the burst gate 18 and supplied to one input of the phase comparator 19 .

The other input of the phase comparator 19 is supplied with a low frequency converted carrier created by a carrier creation circuit 23 through branch processing from the oscillation output of the VCO 22. Phase comparator 19
compares the phase of the burst portion of the low frequency converted color signal CL and the created low frequency carrier.

After the phase comparison result passes through an adder 20, harmonic components are removed by an LPF 21 and the result is supplied to a voltage controlled oscillator 22.

The phase comparison 19 and adder 20 as described above. LPF 21
．． A field pack loop of the VCO 22 and the carrier generation circuit 23 constitutes a PLL (phase locked loop), and the VCO 22 converts the low frequency conversion carrier from the carrier generation circuit 23, which is input to the phase comparator 19, into a low frequency conversion color signal. The oscillation phase is controlled so as to be phase-synchronized with the burst portion of . However, since the burst portion of the low-pass conversion color signal is an intermittent wave, the created low-pass conversion carrier has a stable point for each horizontal frequency, and if the frequency does not match the burst of the low-pass conversion color signal, There is. In order to avoid such a state (hereinafter referred to as a side-locked state), the horizontal synchronizing signal H is separated from the demodulated luminance signal Y by the synchronization separation circuit 17, and the frequency of said H and the frequency of the output GK of the VCO 22 are compared by the frequency comparator 24. Compare the frequencies,
By supplying the comparison result to adder 20, VCO2
2 and the horizontal synchronizing signal H is kept constant to avoid the side lock state. The oscillation output CK of the VCO 22 is supplied to the address generation circuit 15 as a write control clock. The address generation circuit 15 uses analog memory or RAM as a storage element of the storage circuit 13.14.
When using, for example, a counter is formed internally, the clock CK is counted, and the counter is reset at the rising edge of the horizontal synchronizing signal H, or the frequency of the clock CK is n times the frequency of the signal H (n is a positive integer)
In this case, by directly using the count value of a counter that divides the clock generated by itself into 1/n, it is possible to obtain a signal that has the same time axis error as the mixed wave taken out from the recording medium and that is equal to the horizontal synchronization signal. It is possible to obtain an address that keeps a constant value at the rising edge and repeats n types of numerical values at the IH period. When analog memory or RAM is used as the memory element of the memory circuits 13 and 14, the write addresses wy, w can be set using the method described above.
c is created, and the demodulated luminance signal Y and low-frequency conversion color signal CL are written. Here, wy, wc demodulated luminance signal Y
The count frequency may be set to sufficiently pass the frequency band of the low-pass conversion color signal OL, and the same address may be used. Alternatively, the count frequency may be lowered considering the band of the low-pass conversion color signal, and the storage capacity of the storage circuit 14 may be reduced. It may be designed with less. In particular, when the number of addresses in the memory circuit 14 for low-frequency conversion color signals is set to 1, which is a power of 2, with respect to the number of addresses in the memory circuit 13, the write address in the memory circuit 13 is set as the write address in the memory circuit 14. It is also possible to use a reduced number of address bits by truncating the lower bits of the address generator 15 and to configure the address generator 15 with a single counter.

3H when using a shift register as a storage element
A device with the above storage capacity is rotated and used for each IH, and the configuration is such that data for 18 periods is written and then data for 18 periods is read, and writing and reading to the IH shift register are time-critical. Control in a similar manner. In this case, the address generation circuit selects the shift register to be written from among several H shift registers.
For example, the shift register may be switched at an appropriate timing based on the rising edge of the horizontal synchronizing signal or the count value of a counter that is a component of the frequency multiplier circuit.

As described above, the method for reading the data of the signal Y and the signal C written in the memory circuits 13, 1.4 is to generate a read address in the address generation circuit 16 and use the clock CK to control the address generation circuit 16. ' is XCO
25 reference oscillation outputs are used.

A reference horizontal synchronizing signal H' is generated from the oscillation output of the XCO 25 by a synchronizing signal generating circuit 26 and is used as a horizontal synchronizing signal separated from the demodulated luminance signal Y necessary for writing. The method of creating the read addresses RY and RC of the address generation circuit 1G is almost the same as the method of the address generation circuit 15, so the explanation will be omitted here. When a shift register is used as a storage element, the rising edge of the horizontal synchronization signal generated by the synchronization signal generation circuit 21 is used as the switching timing of the IH shift register to be read.

By performing writing and reading in the memory circuits 13 and 14 through this operation, the demodulated luminance signal Y and the low-frequency conversion color signal CL are demodulated in synchronization with the synchronization signal generated by the synchronization signal generation circuit 26, with time axis fluctuations removed. Luminance signal Y
' and a low frequency converted color signal CL' are extracted. after that,
The low-pass converted color signal CL' is multiplied by the carrier wave from the carrier generation circuit 27 in the frequency converter 8, and the frequency-converted carrier color signal C6c' is extracted as the output of the BPF 9. The carrier generation circuit 27 is composed of a frequency dividing circuit or a frequency multiplication circuit, and generates a carrier wave for frequency conversion from the reference oscillation output from the XCO 25. The extracted carrier color signal CGe' is added to the demodulated luminance signal Y' in an adder 10, and is outputted to an output terminal 11 as a signal for color television.

Next, a configuration example of the address generation circuit 15 in the color video signal reproducing apparatus of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing an example of the configuration of the address generation circuit 15 in the embodiment shown in FIG. 1, and the components of devices connected externally are the same as those in the system diagram of FIG. A reference numeral is given and the explanation is omitted. FIG. 4 is a waveform diagram of each part in FIG. 3. In Figure 3,
Inverter 31 and flip-flops 32a-32e,
AND gates 33b to 33e, flip-flops 34b to 34e, AND gates 36b to 36e,
The OR gates 35, 37, 38, and the AND gate 39 constitute a variable delay circuit 50, the inverter 40, flip-flops 41a, 41b, and the NAND gate 42 constitute a reset circuit 51 that resets the counter, and the comparator 43 and the flip-flop 44a , 44-b, A
The ND gate 45 constitutes a control circuit 52 that controls the amount of delay of the variable delay circuit 50. 30 is mono multi, 48 is 1
/4 frequency divider, 42 is an n-ary counter (n is a positive integer).

The burst of the low-frequency conversion color signal is the color WAW of the low-frequency conversion color signal.
The frequency and phase are synchronized with the i transmission wave, and the frequency is an integral multiple of the frequency fH of the horizontal synchronization signal H, or an integral multiple of 1 in the power of 2 (for example, an integral multiple of 1/4° 1/8) being chosen by Therefore, as explained in FIG. 1, the phase comparator 19, the adder 20, the LPF 21, the VCO 22, and the carrier generation circuit 23 output the output of the VCO 22 from the burst part of the low-pass conversion color signal C by the PLL. ni fH
If the mixed wave input from terminal 1 in Figure 1 has time axis fluctuations, the VCO
The clock CK which is the output of 22 can also have the same time axis fluctuation. However, the frequency of the color subcarrier of the low-pass conversion color signal itself is the frequency fH when created by multiplying the horizontal frequency fH of the horizontal synchronization signal during recording.
In some cases, jitter occurs with respect to the frequency fH of the horizontal synchronizing signal H, and furthermore, during reproduction, jitter occurs in the clock CK with respect to the frequency fH of the horizontal synchronizing signal H due to the tracking characteristics of the PLL. When an address is generated by the address generator 15 using a clock GK having jitter with respect to such a frequency fo, and the address is to be reset at the rise timing of the horizontal synchronization signal H, for example, the timing of the address change point and the horizontal synchronization If the rise timings of signal H are close to each other, the address reset timing becomes unstable, and I
The number of addresses for each H is no longer uniform. For example, I Hti
When generating addresses divided by -n (n is a positive integer), addresses from O to n-1 are normally output repeatedly, but at the timing described above, the frequency relationship between the horizontal synchronization signal H and the clock CK is approximately Since it is constant, the state in which the address per IH is from 0 to n-2 or from O to n is alternately repeated. In this state, the memory circuit 13.
14, the corrected signal Y' or CL' causes discontinuity in the vicinity of the reference horizontal synchronization signal H', and discontinuity also occurs in the signal output from the terminal 11, which is preferable. do not have. In order to avoid the above-mentioned situation, it is possible to adjust the phase relationship between the horizontal synchronization signal and the color subcarrier of the low-band conversion color signal in advance, but the horizontal synchronization signal and the low-band conversion color signal during recording may be The phase relationship between the color subcarriers of the signal is not particularly defined. Also, during recording, the color subcarrier frequency of the low frequency conversion color signal may not be generated from fH, but is given by a fixed oscillator, so in this case, the phase of the horizontal synchronization signal and the low frequency conversion color subcarrier wave changes from moment to moment. Conditions in which the above-mentioned discontinuities are likely to occur occur periodically. Therefore, the address generation circuit 15 shown in FIG. 3 detects when the above-mentioned address change point and the rising retiming of the horizontal synchronizing signal H are close to each other, and avoids consecutive discontinuities. Do the action.

In FIG. 3, the horizontal synchronization signal H supplied from the horizontal synchronization separation circuit 17 has unnecessary parts such as equivalent pulses of the vertical synchronization period removed by a monomulti 30, and is supplied to the variable delay circuit 50 as HmIll. The variable delay circuit 50 uses the clock /CK inverted by the inverter 31 to select one of the signals H0 to H4 obtained by delaying I(■ by one tarok of /CK by the flip-flops 32a to 32d, and outputs the signal to the OR gate 37. The reset circuit 51 detects the rise of the signal HdJ1 and generates a reset pulse /CL.The generated pulse /C
L resets the n-ary counter 49 and, as a result, resets the addresses wy and wc supplied to the memory circuits 13 and 14. Here, to simplify the explanation, WY and WC are assumed to be the same address [), but considering the frequency band of the low-pass conversion color signal, some upper bits of WY are used as the address WC to store the data in the memory circuit 14. It may be designed with a smaller capacity. The n-ary counter 49 receives the clock CK from the VCO 22.
The clock WCK whose frequency is divided by the 1/4 frequency divider 48 is counted to create addresses wy and wc. Here, the 49 n-ary counters normally repeatedly generate addresses from 0 to n-1, and the reset pulse /CL is at address wy, and wc is at n.
It is applied uniformly at the -1 position. However, the address WY, W
If the change timing of C and the acquisition timing of the signal Hd are close, and if there is jitter that swings back and forth in the clock CK, the timing of the reset pulse /CL supplied to the n-ary counter 49 as described above will be the same as the address WY, W.
It is assumed to be in an unstable state, which is often at the n or n-'2 position of C. In order to avoid this situation, the address generation circuit 15 of FIG.
But address WY.

When the signal Hd1 is present at a position other than n-1 of the WC, the delay amount of the signal Hd1 is changed by the method described below so that the n-ary counter 49 can be reset stably.

For example, in the waveform of each part in FIG. 4(a), the signal Hdm
However, since the phase of H++ua has changed to be delayed with respect to WCK, the addresses WY and WC from the n-ary counter 49 have been changed to n. Address WY was generated at position t' of -1.

The WC has changed to the t position where it is 0. At this time, the signal Hg
is taken in by the clock /WCK obtained by inverting the clock WCK by the inverter 40, so if the phase of HIIlm advances a little after IH and becomes HIII11' in FIG. 4(a), it will be reset again at the position t', The addresses wy and wc at this time have the previous reset timing /W
Due to the delay of one clock of CK, the result is n-2 as shown in FIG. 4(b).

Therefore, there is a high probability that addresses wy and wc will be reset at n-2 or O.

Therefore, the control circuit 52 includes a comparator 43, and when the addresses wy and wc are other than n-1, the comparator 43
A logic level 'H' signal is output, and this signal is latched by the flip-flop 44a at the falling edge of /CL, and a detection signal Ed is created by the flip-flop 44b and the AND gate 45. The signal of L(H11 is supplied to the OR gate 38 of the variable delay circuit 50. In addition to the detection signal E, the signal from the NOR gate 35 is input to the ○R gate 38 of the variable delay circuit 50. When this signal is 'H', it is passed through the AND gate 39 to the flip-flops 34b to 3.
4e is supplied with the same clock WCK as the clock CNT. The variable delay circuit 50 receives each delay signal Hnv+ generated by the flip-flops 32a to 32d.
From □~H4, AND gates 33b~33e create detection signals D1~D4 of the rising edges by the outputs of flip-flops 32b~32e, and these detection signals D1~
D, and the flip-flop 3 using the clock CNT.
4b-34e, AND gate 36b-36e.

A delayed signal that is stably relatted by the OR gate 37a is selected from among the signals H-H4, and the signal Hd is generated.

The signal is supplied to the reset circuit 51 as a signal. NOR gate 35
are detected signals D1 to D when the circuit malfunctions or when the power is turned on.
4 become the logic level "L I+", the signal Hd becomes a stable state of 11 L 11, and the reset pulse /CL is no longer generated, so it is detected and the clock CNT is forcibly generated. death.

It functions to return to normal operation. The variable delay circuit 50 of the circuit diagram of FIG. 3 described above. Reset circuit 51
FIG. 4(a) shows the waveforms of each part of the control circuit 52. In FIG. 4(b), these operations select the delayed signal H2 as the signal Hd&, and as a result, the phase of the signal Hmm changes. For example, even if the position Hmm' in FIG. 4(b) is reached, the reset pulse /CL is at the address wy.
, wc are stably generated at the position n-1, and the memory circuit 13
．． The number of times that discontinuities occur in the signals y', c, . . . after time axis correction in step 14 can be reduced. Above,
Address generation circuit 1 of color video signal reproducing device of the present invention
Regarding the configuration and operation of No. 5, we have described the case where the phase of the signal Hmn+ is delayed and the pulse /CL is generated at the 0 position of addresses wy and wc, but the phase of the signal Hmm is advanced and the pulse /CL is generated at the address WY.

When generated at the n-2 position of WC, a stable reset pulse /CL is generated from the first horizontal period by a similar operation.

In addition, in FIGS. 3 and 4, the memory circuits 13 and 14
Although we have described the case where analog memory or RAM is used as the storage element, a shift register may also be used as the storage element. In this case, WCKK is used as the drive clock of the shift register and the falling timing of pulse /CL or address Wy, By setting the timing at which wc becomes 0 as the timing for switching the shift register that performs writing, the number of times discontinuity occurs in the signals y' and cL' after time axis correction by the memory circuits 13 and 14 can be calculated using the same method. It can be reduced.

Effects of the Invention As described above, the present invention provides FM data taken out from a recording medium.
Y/
A C separator, an FM demodulator, two storage circuits, an address generation circuit that generates an address having the same time axis error as the mixed wave from the recording medium, and an address generation circuit that operates with a reference clock. The control clock for the address generation circuit, which is equipped with a time axis corrector, a frequency converter, and an adder, and generates an address with the same time axis error as the mixed wave, is derived from the burst of the low-frequency conversion color signal. After separating the mixed wave with a Y/C separator, the time axis correction is performed on the signal demodulated with the FM demodulator for the a degree signal using the time axis corrector, and the time axis correction is performed on the low frequency conversion color signal. After the time axis is corrected using a frequency converter, the signal is converted to a carrier color signal of a predetermined carrier frequency using a frequency converter, and the demodulated luminance signal after time axis correction and the carrier color signal after frequency conversion are added together using an adder. I am trying to get a color video signal,
Conventional color video signal reproducing devices correct only the carrier phase of the reproduced carrier color signal, but by detecting the time axis fluctuation of the burst phase of the low-frequency conversion color signal,
By performing time axis correction in the state of the low frequency converted color signal, phase correction is also performed at the same time.As a result, it is possible to perform both time axis correction and phase correction of the carrier color signal after frequency conversion. This has the effect that a reproduced carrier color signal can be obtained. Further, since the luminance signal Y is also time-base corrected, it is possible to reproduce a color video signal in which the frequency interleave relationship is maintained.

Furthermore, as means for creating a control clock for an address generation circuit that generates an address with the same time axis error as that of the mixed wave, a voltage controlled oscillator and a voltage control oscillator whose output signal has the same frequency as the burst of the low frequency converted color signal are used. Equipped with a carrier creation circuit that creates a low-frequency carrier and a phase comparator,
The burst of the low-frequency conversion color signal and the low-frequency carrier from the carrier generation circuit are phase-compared by the phase comparator, the oscillation frequency of the voltage-controlled oscillator is controlled based on the comparison result, and the output signal of the voltage-controlled oscillator is used for control purposes. By creating a clock, it is possible to provide the control clock with both time axis fluctuation error information and carrier phase information of the low frequency conversion color signal using a relatively simple circuit, and the resulting color It is possible to easily prevent a video signal from causing a hue shift on a playback screen.

Furthermore, an address generation circuit that generates an address having the same time axis error as the mixed wave of the FM demodulated luminance signal and the low frequency conversion color signal taken out from the recording medium is connected to a variable delay circuit and a waveform after passing through the variable delay circuit. The counter is composed of a counter that is reset by the timing of a horizontal synchronization signal and a control circuit that controls the delay time of the variable delay circuit, and is more stable than the horizontal synchronization signal after passing through the variable delay circuit and the count timing of the counter. By detecting the timing and controlling the delay amount of the variable delay circuit, discontinuities can be caused in the demodulated luminance signal Y' and the low frequency converted color signal C' which have been time-base corrected by the memory circuits 13 and 14. The number of occurrences can be reduced, resulting in the effect of reproducing stable color video signals.

[Brief explanation of drawings]

FIG. 1 is a system diagram of a color video signal reproducing device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part in FIG. 1,
3 is a circuit diagram of one configuration example of the address generation circuit 15 in FIG. 1, FIG. 4 is a waveform diagram of each part in FIG. 3, and FIG. 5 is a system diagram of a conventional color video signal reproducing device. FIG. 6 is a frequency spectrum diagram of a recorded color video signal recorded on a recording medium. 5...FM demodulator, 8...Frequency converter, 10.2
0... Adder, 12... Y/C separator, 13.1
4... Memory circuit, 15, 16... Address generation circuit, 17... Horizontal synchronization separation circuit, 18... Burst gate, 19... Phase comparator, 21... LPF, 22
-V C0123,27-* -? U7 creation circuit,
30...Mono multi, 48...174 frequency divider, 49
...N-ary counter, 50...Variable delay circuit, 51.
...Reset circuit, 52...Control circuit

Claims (1)

[Claims] 1. A Y/C separator that separates a mixed wave of an FM modulated luminance signal and a low frequency converted color signal extracted from a recording medium, an FM demodulator, two storage circuits, and the recording medium. Equipped with a time axis corrector, a frequency converter, and an adder, each having at least one address generation circuit that generates an address with the same time axis error as the mixed wave from and one address generation circuit that operates with a reference clock. A control clock for an address generation circuit that generates an address with the same time axis error as the mixed wave is created from a burst of low-frequency conversion color signals, and after separating the mixed wave with a Y/C separator, a luminance signal is generated. For the signal demodulated by the FM demodulator, the time axis is corrected by the time axis corrector, and for the low frequency converted color signal, the time axis is corrected by the time axis corrector, and then the frequency converter is used to convert the signal to a predetermined carrier frequency. A color video signal reproducing device configured to convert the signal into a carrier color signal and add the demodulated luminance signal after time axis correction and the carrier color signal after frequency conversion using an adder to obtain a color video signal. 2. As a means for creating a control clock for an address generation circuit that generates an address with a time axis error, a voltage controlled oscillator and a low frequency carrier having the same frequency as the burst of the low frequency converted color signal from the output signal of the voltage controlled oscillator are used. The phase comparator compares the phases of the burst of the low-frequency conversion color signal and the low-frequency carrier from the carrier generation circuit, and the comparison result determines the oscillation frequency of the voltage-controlled oscillator. 2. The color video signal reproducing apparatus according to claim 1, wherein a control clock is generated from the output signal of the voltage controlled oscillator. 3. An address generation circuit that generates an address with the same time axis error as the mixed wave has a variable delay circuit, a counter set by the timing of the horizontal synchronization signal after passing through the variable delay circuit, and a delay time of the variable delay circuit. A control circuit is provided to control the amount of delay of the variable delay circuit by detecting a stable counter reset timing from the horizontal synchronization signal passed through the variable delay circuit and the count timing of the counter. A color video signal reproducing device as claimed in claim 1.