JPH05304156A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH05304156A
JPH05304156A JP11049892A JP11049892A JPH05304156A JP H05304156 A JPH05304156 A JP H05304156A JP 11049892 A JP11049892 A JP 11049892A JP 11049892 A JP11049892 A JP 11049892A JP H05304156 A JPH05304156 A JP H05304156A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
electrode
solder
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11049892A
Other languages
Japanese (ja)
Inventor
Naoaki Inoue
尚明 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP11049892A priority Critical patent/JPH05304156A/en
Publication of JPH05304156A publication Critical patent/JPH05304156A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To provide a semiconductor integrated circuit for flip-chip having electrode parts durable against a plurality of times of mounting and does not collapse even if the electrode part is pressed by some extent from the rear at the time of bonding and in which nondestructive measurement of electrical characteristics can be made after formation of electrode. CONSTITUTION:Electrode part of the semiconductor integrated circuit has a structure wherein aluminum pads 2, a barrier metal 1a, and the like are formed on a semiconductor substrate 1 and the barrier metal layer 4 is applied with a metal core 6 having outer periphery thinly coated with a solder layer 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電気回路を高密度に集
積実装することを目的とした例えばフリップチップ用半
導体集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for flip chips, for example, for the purpose of integrated mounting of electric circuits at high density.

【0002】[0002]

【従来技術】従来のフリップチップ用半導体集積回路
は、その電極のほとんどがハンダで構成されている。例
えば図5に示すように、半導体基板41上に形成された
アルミパッド42に保護膜43のコンタクトホールを介
してバリアメタル層44が形成され、さらにその上部に
接合用のハンダバンプ45が形成されており、ハンダ電
極を構成している。
2. Description of the Related Art In a conventional flip-chip semiconductor integrated circuit, most of its electrodes are composed of solder. For example, as shown in FIG. 5, a barrier metal layer 44 is formed on an aluminum pad 42 formed on a semiconductor substrate 41 through a contact hole of a protective film 43, and a solder bump 45 for bonding is formed on the barrier metal layer 44. And constitutes a solder electrode.

【0003】[0003]

【発明が解決しようとする課題】上述したような構造で
あると半導体集積回路を基板に実装し、加熱してハンダ
を溶融し、基板側の電極と電気的に接続させる際、自重
だけではうまく接合しないことがあるため、自重に加え
て集積回路の基板裏面からある一定の力を加えて、接合
することが行われている。電極自体がハンダで構成され
ている場合は、裏面からの力によってハンダ自体が潰れ
てしまい、隣接したハンダ電極とショートする危険性が
生じるという問題点がある。図6(A)に示すように、
より確実な接合のために加圧加温による接合を試みた場
合、図6(B)のようにハンダバンプ45自体が潰れて
しまい、隣接するハンダ電極同士が短絡してしまうとい
う不都合があり、加圧操作が困難である。
With the above structure, when mounting the semiconductor integrated circuit on the substrate, heating it to melt the solder, and electrically connecting it to the electrodes on the substrate side, the weight alone is sufficient. Since there is a case where they are not joined, joining is performed by applying a certain force from the back surface of the substrate of the integrated circuit in addition to the dead weight. When the electrode itself is composed of solder, there is a problem that the solder itself is crushed by the force from the back surface and there is a risk of short-circuiting with an adjacent solder electrode. As shown in FIG. 6 (A),
When attempting joining by heating under pressure for more reliable joining, there is a disadvantage that the solder bump 45 itself is crushed as shown in FIG. 6B, and adjacent solder electrodes are short-circuited. Pressure operation is difficult.

【0004】また一度基板に搭載した半導体集積回路
を、再度加熱してひき剥しても、基板側と半導体集積回
路側に残されるハンダの量は不均一であり、再度基板に
搭載することが困難であるという問題点がある。すなわ
ち図7に示すように従来のハンダ電極ではICチップや
配線基板に不良が発生した場合に配線基板47を加温し
て半導体基板41を取り外し工具50で取り外しても、
半導体基板41と配線基板47側にそれぞれ残されるハ
ンダの量を制御することは困難であり、配線基板47に
多くハンダ48が残される場合や少ない場合49がラン
ダムに生じ、結果的に再利用することが困難である。
Further, even if the semiconductor integrated circuit once mounted on the substrate is peeled off by heating again, the amount of solder left on the substrate side and the semiconductor integrated circuit side is uneven, and it is difficult to mount it again on the substrate. There is a problem that is. That is, as shown in FIG. 7, in the conventional solder electrode, when a defect occurs in the IC chip or the wiring board, the wiring board 47 is heated and the semiconductor substrate 41 is removed by the removal tool 50.
It is difficult to control the amount of solder left on the side of the semiconductor substrate 41 and the amount of solder left on the wiring substrate 47 side. Is difficult.

【0005】さらに、ハンダは室温でも柔らかく、ま
た、メッキしたハンダを一度融点以上の温度で熱処理を
行うと球状に変形してしまうため、半導体集積回路の電
気的特性を評価する際に、プローブの針がハンダを損傷
させたり、プローブの針が半導体集積回路の電極全部に
確実に接触できない場合が生じるという問題点がある。
すなわち図8に示すように従来のハンダ電極では、電極
全体がハンダで形成されているため、例えば動作検査時
に細い金属針52でプロービングすると、金属針52が
ハンダバンプ45に容易に食い込み、ハンダバンプの4
5の形状を著しく変化させたり、電極自体を剥離してし
まうという不都合がある。
Further, the solder is soft even at room temperature, and when the plated solder is once heat-treated at a temperature higher than the melting point, the solder is deformed into a spherical shape. Therefore, when evaluating the electrical characteristics of the semiconductor integrated circuit, There is a problem that the needle may damage the solder, or the needle of the probe may not surely contact all the electrodes of the semiconductor integrated circuit.
That is, as shown in FIG. 8, in the conventional solder electrode, since the entire electrode is formed of solder, for example, when probing with a thin metal needle 52 at the time of operation inspection, the metal needle 52 easily digs into the solder bump 45 and the solder bump 4
There are inconveniences that the shape of No. 5 is remarkably changed and the electrode itself is peeled off.

【0006】本発明は、複数回の搭載に耐え、また、電
極形成後に非破壊の電気的特性の測定ができ、また、接
合時には裏面から加圧しても、ある一定以上潰れない電
極構造を有する半導体集積回路を提供するものである。
The present invention has an electrode structure capable of withstanding multiple times of mounting, non-destructive measurement of electrical characteristics after electrode formation, and not crushed to a certain degree or more even when pressure is applied from the back surface at the time of bonding. A semiconductor integrated circuit is provided.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに本発明は、半導体集積回路に直接とりつける電極の
内部に高融点金属のコアを形成し、その外周を低融点の
金属で覆った構造としたことを特徴としている。
In order to achieve the above object, the present invention forms a core of a high melting point metal inside an electrode directly attached to a semiconductor integrated circuit, and covers the outer periphery of the core with a low melting point metal. It is characterized by having a structure.

【0008】[0008]

【作用】半導体集積回路に直接とりつける電極の内部に
高融点金属のコアを形成し、その外周を薄い低融点の金
属で覆っているために接合時には裏面から加圧しても、
隣接するハンダ電極同士が短絡してしまうということが
なく、接合部分が再利用でき、また動作検査時に電極自
体を剥離することがない。
[Function] A high melting point metal core is formed inside an electrode directly attached to a semiconductor integrated circuit, and its outer periphery is covered with a thin low melting point metal.
The adjacent solder electrodes are not short-circuited with each other, the joint portion can be reused, and the electrodes themselves are not peeled off during the operation inspection.

【0009】[0009]

【実施例】本発明の一実施例について、図1〜図4を用
いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

【0010】図1は、本発明の一実施例における半導体
集積回路の電極部の構造断面図である。本発明による半
導体集積回路は、図1のような電極部を多数有している
もので、この電極部は、半導体基板1上に形成されたア
ルミパッド2に保護膜3のコンタクトホールを介してバ
リアメタル層4が形成されており、バリアメタル層4の
上に、内部が銅などの高融点金属である金属コア6によ
って占められており、低融点金属であるハンダ層7がそ
の金属コア6の外周を薄くコーティングした部分を有す
る構造となっている。
FIG. 1 is a structural sectional view of an electrode portion of a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit according to the present invention has a large number of electrode portions as shown in FIG. 1, and the electrode portions are formed on the aluminum pad 2 formed on the semiconductor substrate 1 through the contact holes of the protective film 3. The barrier metal layer 4 is formed, and the inside of the barrier metal layer 4 is occupied by a metal core 6 which is a high melting point metal such as copper, and the solder layer 7 which is a low melting point metal is the metal core 6 thereof. It has a structure having a thinly coated outer periphery.

【0011】この金属コア6は高融点金属で導電性のあ
るものであればよく、他にニッケル等が考えられる。ま
た金属コア6の外周を薄くコーティングしている低融点
金属としては、他にインジウム、インジウム−ガリウ
ム、スズ等が考えられる。
The metal core 6 may be a refractory metal having conductivity and nickel or the like may be used. In addition, indium, indium-gallium, tin, and the like can be considered as the low-melting-point metal that thinly coats the outer periphery of the metal core 6.

【0012】図2は、本発明の一実施例における半導体
集積回路の電極部と他の配線基板との加圧加温による接
合状態の断面図である。本発明によれば、電極の内部が
銅などの金属コア6を形成しているために、加圧加温接
続を試みた場合、表面のハンダ層7のみが潰れて配線基
板と溶融接続され、金属コア6は潰れずに配線基板の電
極10に接触した状態が保たれる。よって、隣接する電
極のハンダが短絡することなく、高い確率で電極同士を
接合させることができる。
FIG. 2 is a cross-sectional view of a state in which an electrode portion of a semiconductor integrated circuit and another wiring substrate according to an embodiment of the present invention are joined together by heating under pressure. According to the present invention, since the metal core 6 made of copper or the like is formed inside the electrode, when pressure heating connection is attempted, only the solder layer 7 on the surface is crushed and melted and connected to the wiring board. The metal core 6 is not crushed and is kept in contact with the electrode 10 of the wiring board. Therefore, the electrodes can be bonded to each other with a high probability without short-circuiting the solder of the adjacent electrodes.

【0013】図3は、本発明の一実施例における半導体
集積回路の接合部分のリペア性の模式図である。本発明
によれば加温時に溶融するハンダ8は金属コア6の外周
にしか存在せず、しかも絶対量が従来に比較して著しく
少ないために、半導体基板1の金属コア6の外周上と配
線基板の電極10にそれぞれ残されるハンダの量は、ど
の電極もほぼ同等となり、再度搭載して再利用すること
ができる。
FIG. 3 is a schematic diagram of the repairability of the junction portion of the semiconductor integrated circuit in one embodiment of the present invention. According to the present invention, the solder 8 that melts during heating exists only on the outer circumference of the metal core 6, and the absolute amount is significantly smaller than that of the conventional one. The amount of solder left on each of the electrodes 10 on the substrate is almost the same for all electrodes, and the electrodes can be mounted again and reused.

【0014】図4は本発明の一実施例における半導体集
積回路の動作検査の状態の模式図である。本発明による
半導体集積回路の電極部では、その内部に金属コア6を
有しているため、動作検査時の金属針12によるプロー
ビングでは金属コア6内部まで針が侵入できず、電極表
面の物理的ダメージを著しく軽減できる。
FIG. 4 is a schematic view showing the state of the operation inspection of the semiconductor integrated circuit in the embodiment of the present invention. Since the electrode portion of the semiconductor integrated circuit according to the present invention has the metal core 6 therein, the probe cannot be penetrated into the metal core 6 by probing with the metal needle 12 at the time of operation inspection, and the physical surface of the electrode is not physically penetrated. Can significantly reduce damage.

【0015】[0015]

【効果】本発明によれば、電極と基板側の金属パッドを
高い確率で接続させるために、加温時に半導体集積回路
の裏面よりある一定の力を加えた場合でも、コアを形成
する高融点金属が潰れずに支柱となって電極同士のショ
ート等の問題を回避できる。
According to the present invention, in order to connect the electrode and the metal pad on the substrate side with high probability, even if a certain force is applied from the back surface of the semiconductor integrated circuit at the time of heating, the high melting point forming the core It is possible to avoid problems such as short-circuiting between electrodes by forming a pillar without crushing the metal.

【0016】また、一度実装したフリップチップ用半導
体集積回路を組立の都合により、再度別の基板に搭載し
て用いることができる。
Further, the flip-chip semiconductor integrated circuit mounted once can be mounted on another substrate and used again for convenience of assembly.

【0017】さらに、内部にハンダと比較して融点の高
い金属コアを有しているためにハンダ電極を形成した後
でも、少ないダメージでプロービングができ、半導体集
積回路の電気的特性を評価できる。
Further, since the metal core having a higher melting point than that of solder is provided inside, probing can be performed with little damage even after the solder electrode is formed, and the electrical characteristics of the semiconductor integrated circuit can be evaluated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体集積回路の電
極部の構造断面図
FIG. 1 is a structural cross-sectional view of an electrode portion of a semiconductor integrated circuit according to an embodiment of the present invention.

【図2】本発明の一実施例における半導体集積回路の電
極部と配線基板との加圧加温による接合状態断面図
FIG. 2 is a cross-sectional view of a state in which the electrode portion of the semiconductor integrated circuit and the wiring board according to one embodiment of the present invention are joined by heating under pressure

【図3】本発明の一実施例における半導体集積回路の接
合部分のリペア性の模式図
FIG. 3 is a schematic diagram of repairability of a junction portion of a semiconductor integrated circuit according to an embodiment of the present invention.

【図4】本発明の一実施例における半導体集積回路の動
作検査の状態の模式図
FIG. 4 is a schematic diagram of a state of operation inspection of a semiconductor integrated circuit in an embodiment of the present invention.

【図5】従来の半導体集積回路の電極部の構造断面図FIG. 5 is a structural sectional view of an electrode portion of a conventional semiconductor integrated circuit.

【図6】従来の半導体集積回路の電極部と配線基板との
加圧加温による接合状態断面図
FIG. 6 is a sectional view showing a state in which a conventional semiconductor integrated circuit electrode portion and a wiring board are joined together by heating under pressure.

【図7】従来の半導体集積回路の接合部分のリペア性の
模式図
FIG. 7 is a schematic diagram of repairability of a junction portion of a conventional semiconductor integrated circuit.

【図8】従来の半導体集積回路の動作検査の状態の模式
FIG. 8 is a schematic diagram of a conventional semiconductor integrated circuit operation inspection state.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 多数のハンダバンプの電極をその回路上
に有し、他の基板とこのバンプを介して接合されるもの
において、このバンプの内部を高融点の金属で形成し、
その外周を低融点金属の膜で覆った電極構造としたこと
を特徴とする半導体集積回路。
1. In one having a large number of solder bump electrodes on its circuit and joined to another substrate via this bump, the inside of this bump is formed of a high melting point metal,
A semiconductor integrated circuit having an electrode structure having an outer periphery covered with a film of a low melting point metal.
JP11049892A 1992-04-28 1992-04-28 Semiconductor integrated circuit Pending JPH05304156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11049892A JPH05304156A (en) 1992-04-28 1992-04-28 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11049892A JPH05304156A (en) 1992-04-28 1992-04-28 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH05304156A true JPH05304156A (en) 1993-11-16

Family

ID=14537290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11049892A Pending JPH05304156A (en) 1992-04-28 1992-04-28 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH05304156A (en)

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