JPH05303563A - Signal processor - Google Patents

Abstract

PURPOSE:To count many signals in pulse density representation at a high speed while maintaining the parallelism of a neural network. CONSTITUTION:The signal processor has a signal processing network formed by connecting plural signal processing means, which each have a 1st arithmetic means for logical arithmetic between plural input signals in pulse density representation and a coupling coefficient held in a memory, a grouping means for dividing the arithmetic result of the 1st arithmetic means into two stimulative and suppressive coupling groups, an OR means for 0Ring the groups, and a coupling coefficient varying means for varying the coupling coefficient in the memory by calculating a new coupling coefficient on the basis of plural error signals, in a network shape; and this signal processor is provided with a two-dimensional light emitting means 55 which develops the respective output means of the signal processing means with time and outputs them to the final output stage of the signal processing network at the same time and an output counter 54 paired with a linear photodetecting means 56 made to correspond to the two-dimensional light emitting means 55 on the same plane.

Description

Detailed Description of the Invention

[0001]

INDUSTRIAL APPLICABILITY The present invention is applicable to control of various movements such as recognition of images and voices, position control of robots, temperature control of air conditioners, orbit control of rockets, etc. The present invention relates to a signal processing device such as a neuro computer.

[0002]

2. Description of the Related Art The function of a nerve cell (neuron), which is a basic unit of information processing of a living body, is mimicked, and further, this "nerve cell mimicking element" (nerve cell unit) is connected to a network to process information in parallel. The aim is a so-called neural network. Although it is easy to perform character recognition, associative memory, motion control, etc. in a living body, there are many things that conventional Neumann computers cannot easily achieve. Attempts to solve these problems by imitating the neural system of a living body, in particular, the functions peculiar to the living body, that is, parallel processing, self-learning, etc., by a neural network are being actively made, centering on computer simulation.

First, a conventional neural network model will be described. FIG. 8 is a diagram showing a certain nerve cell unit A, and FIG. 9 is a network thereof. A ₁ , A ₂ , and A ₃ each represent a nerve cell unit. One neuronal cell unit is coupled to a number of other neuronal cell units and processes the signals received from them to produce an output. In the case of FIG. 9, the network is hierarchical, and the nerve cell unit A ₂ receives a signal from the nerve cell unit A _{1 in the} previous layer (left side) and the nerve cell unit A _{1 in the} next layer (right side). Output to ₃ .

A more detailed description will be given. First, in the nerve cell unit A of FIG. 8, the degree of coupling between another nerve cell unit and its own unit is called a coupling coefficient, and the coupling coefficient of the i-th nerve cell unit and the j-th nerve cell unit The coupling coefficient is generally represented by T _ij . To join,
Excitatory coupling in which the larger the signal from the other unit (the unit that sends a signal to the own unit) is, the larger the own unit output is, and the larger the signal from the other unit is, the smaller the own unit output is suppressed. Sex connection, where T _ij > 0 represents excitatory connection and T _ij <0 represents inhibitory connection. Now, assuming that the own nerve cell unit is the j-th unit, and the output of the i-th nerve cell unit is y _i , T _ij y _{i obtained} by multiplying this by the coupling coefficient T _ij is the input to the own unit. Becomes As described above, since one nerve cell unit is connected to many nerve cell units, ΣT _ij y _{i, which} is the result of adding T _ij y _i for these units, is It becomes an input to the unit. This is called the internal potential and is represented by u _j .

[0005]

[Equation 1]

Next, a threshold value is added to this input (internal potential) to perform non-linear processing, and the result is output from the nerve cell unit. The function used at this time is called a nerve cell response function, and the sigmoid function as shown in equation (2) and FIG. 10 is used as the nonlinear function.

[0007]

[Equation 2]

When such a nerve cell unit is configured in a network as shown in FIG. 9, each coupling coefficient T _ij
And parallel calculation of the equations (1) and (2) one after another makes it possible to perform parallel processing of information and obtain a final output.

In such a hierarchical neural network, a desired neural network is constructed by performing learning such that the coupling coefficient T _ij is updated so that a desired result is output for a certain input. .. The most widely used such learning method is the error back-propagation method, so-called back-propagation method.

An example of a so-called neurocomputer in which such a network is realized by an electronic circuit and is systemized is disclosed in Japanese Patent Laid-Open No. 236658/1990. In these cases, the number of output pulse densities is counted as an output value.

Here, as an example, as a digital neuron model with a self-learning function, Japanese Patent Application No.
A configuration example and an operation of a signal processing device proposed by the present applicant as No. 4124048 and Japanese Patent Application No. 3-29342 will be described with reference to FIGS. The neural network that is the premise of the proposed example is a digital circuit equipped with a self-learning circuit having a coupling coefficient variable circuit and a coupling coefficient generating circuit that generates a variable coupling coefficient value of the coupling coefficient variable circuit based on an error signal for a teacher signal. It is configured by connecting a signal processing means composed of a plurality of nerve cell mimicking elements by a logic circuit in a mesh.

First, the neural network in the proposed example is implemented by hardware by a digital configuration, but the basic idea is that the neural network unit input / output signals, intermediate signals,
The coupling coefficient, the teacher signal, etc. are all represented by a binary pulse train of "0" and "1". The amount of signal inside the network is represented by the pulse density (the number of "1" s within a certain fixed time). The calculation in the nerve cell unit is represented by a logical operation between pulse trains. The pulse train of the coupling coefficient is placed in the memory. Learning is realized by rewriting this pulse train. For learning, an error is calculated based on the given teacher signal pulse train, and the coupling coefficient pulse train is changed based on the error. At this time, the calculation of the error and the change of the coupling coefficient are all performed by the logical operation of the pulse train of "0" and "1". It was done like this.

This idea will be described below. First,
Regarding signal processing by a digital logic circuit, signal processing in the forward process will be described. FIG. 11 shows a portion corresponding to one nerve cell unit (nerve cell mimicking element) 20, and the entire neural network is of a hierarchical type as shown in FIG. 12, for example. Input and output are all
The one that is binarized into “1” and “0” and synchronized is used. The intensity of the input signal y _i is represented by the pulse density, and is represented by the number of states of “1” within a certain fixed time as in the pulse train shown in FIG. 13, for example. That is, the example of FIG.
4/6, and the signal "1" is 4 in 6 sync pulses.
There are two "0" s. At this time, it is desirable that the arrangement of "1" and "0" is random.

On the other hand, the coupling coefficient T _ij indicating the degree of coupling between the nerve cell units 20 is similarly expressed by pulse density,
The pulse train of "0" and "1" is prepared in advance in the memory. The example of FIG. 14 is an expression representing “101010” = 3/6. Also in this case, it is desirable that the arrangement of "1" and "0" is random.

Then, this pulse train is sequentially read from the memory in response to the synchronous clock, and the AND gate 21 takes the logical product with the input signal pulse train as shown in FIG. 11 (y _i ∩ T _ij ). This is used as an input to the nerve cell j. In the case of the above example, the input signal is “10110
When "1" is input, the pulse train is called from the memory in synchronization with this and "101000" as shown in FIG. 15 is obtained by sequentially performing AND, which means that the input y _i is the coupling coefficient T _ij. And the pulse density is 2 /
6 is shown.

The pulse density of the output of the AND gate 21 is
It is approximately the product of the pulse density of the input signal and the pulse density of the coupling coefficient, and has the same function as the analog coupling coefficient. This is because the longer the signal train is, the more "1"
The more random the arrangement of "0" and "0", the closer to the product of numerical values it has. Not random means
It means that "1" (or "0") is dense (close). When the pulse train of the coupling coefficient is shorter than the input pulse train and there is no data to be read, the head of the data may be returned to and the reading may be repeated.

Since one nerve cell unit 20 has multiple inputs, there are also many "ANDs of the input signal and the coupling coefficient" described above, and the OR circuit 22 then takes the logical sum of these. Since the inputs are synchronized, for example, the first data is "101000" and the second data is "01000".
In the case of “0”, the OR of both is “111000”. If multiple inputs are simultaneously calculated and output, for example, when the number of inputs is m, the result is as shown in FIG. This corresponds to the sum calculation and the non-linear function (sigmoid function) part in the analog calculation.

When the pulse density is low, the pulse density of its OR is approximately equal to the sum of the respective pulse densities. As the pulse density increases, the OR circuit 22
Since the output of is gradually saturated, it does not match the sum of pulse densities, and nonlinearity appears. In the case of OR, the pulse density does not become larger than 1 and does not become smaller than 0, and is a monotonically increasing function, which is approximately equivalent to the sigmoid function.

By the way, the coupling has excitability and inhibition, and in the case of numerical calculation, it is represented by the sign of the coupling coefficient, and in the case of an analog circuit, when T _ij is negative (inhibition coupling), an amplifier is used. It is used to invert the output and _connect it to another nerve cell unit with a resistance value corresponding to T _ij . In this regard, in the proposed digital method, first, each coupling is divided into two groups of excitatory coupling and inhibitory coupling according to the positive / negative of T _ij , and then “A of the pulse train of the input signal and the coupling coefficient is divided into two groups.
The OR of “ND” is calculated for each group. And when only the output of the excitatory coupling group is "1",
"1" is output, and in other cases, "0" is output. In order to realize such a function, the AND of the output of the inhibitory coupling group and the output of the excitatory coupling group may be ANDed. That is, it becomes as shown in FIG. When expressed by a logical expression, it is expressed by the following expressions (3) to (5).

[0020]

[Equation 3]

The network of nerve cell units 20 is
Hierarchical type similar to backpropagation (ie, FIG.
2). If the entire network is synchronized, each layer can be calculated by the functions described above.

Next, the signal calculation processing in learning (back propagation) will be described. Basically, the error signal may be obtained by the following a or b, and then the value of the coupling coefficient may be changed by the method of c.

A. Error signal in the final layer The error signal in each nerve cell unit is calculated in the last layer, and the coupling coefficient relating to the nerve cell unit is changed based on the error signal calculated. The calculation method of the error signal for that is described. Here, the "error signal" is defined as follows. When expressing the error by a numerical value, generally, both positive and negative can be taken, but in the case of pulse density, both positive and negative cannot be expressed at the same time, so there are a signal representing + component and a signal representing − component. The error signal is expressed using two types. That is, j
The error signal of the th neuron unit is shown in FIG. In other words, the + component of the error signal is the portion (1, 0) or (0,
Among 1), the pulse existing on the teacher signal side, on the other hand, the-component is the pulse existing on the output side as well. In other words,
Error signal + pulse is added to the output pulse, and error signal −
Removing the pulse will result in a teacher pulse. That is, when these positive and negative error signals δ _{j (+)} and δ _{j (-)} are expressed by logical expressions, the expressions (6) and (7) are obtained. In the formula, EX
OR represents an exclusive OR. The coupling coefficient is changed based on such an error signal pulse as described later.

[0024]

[Equation 4]

B. Error Signal in Intermediate Layer First, the above-mentioned error signal is back-propagated to change not only the coupling coefficient between the final layer and the layer immediately before it but also the coupling coefficient of the layer before that. Therefore, it is necessary to calculate the error signal in each nerve cell unit in the middle layer. Signals were propagated from the neuron unit with an intermediate layer to each neuron unit in the next layer, which is exactly the reverse of the procedure of collecting error signals in each neuron unit in the next layer. And use it as its own error signal. This means that the above-mentioned arithmetic expressions (3) to (5) in FIG.
It can be performed in the same manner as in the case shown in FIGS. However, the difference from the above-mentioned processing in the nerve cell unit is that y is one signal, while δ has two signals as positive and negative signals, and both signals are considered. It is necessary. Therefore, it is necessary to divide into four cases depending on whether the coupling coefficient T is positive or negative and the error signal δ is positive or negative.

First, the case of excitatory coupling will be described. In this case, for a nerve cell unit having an intermediate layer, the error signal + at the j-th nerve cell unit of the next layer (final layer in FIG. 12), the nerve cell unit and the self unit (intermediate in FIG. 12) AND of the coupling coefficient with the j-th nerve cell unit with a layer) (δ _{j (+)}
∩ T _ij ) is obtained for each nerve cell unit, and the OR between them is taken {∪ (δ _{j (+)} ∩
T _ij )}. This is the error signal δ _{j (+)} of the self unit. That is, assuming that the number of nerve cell units in the layer one layer ahead is n, the result is as shown in FIG.

Similarly, the error signal δ _{j (-)} of the self unit is obtained by ANDing the error signal − and the coupling coefficient in the nerve cell unit of the layer one layer ahead and further ORing them. And That is, it becomes as shown in FIG.

Next, the case of inhibitory binding will be described. In this case, the AND of the error signal in the nerve cell unit of the layer one layer ahead and the coupling coefficient of the nerve cell unit and the self is taken, and further the OR between them is taken. This is the error signal δ _{j (+)} of the layer of the self unit. That is, it becomes as shown in FIG.

Further, by ANDing the error signal + which is one ahead and the coupling coefficient, and further ORing them, the error signal δ _{j (-)} of the self unit is similarly obtained. That is, it becomes as shown in FIG.

Since one neuronal cell unit is excitatoryly coupled to another neuronal cell unit and the other neuronal cell unit is inhibitoryly coupled, an error signal δ obtained as shown in FIG. 19 is obtained. _{j (+)} and the error signal δ obtained as shown in FIG.
The OR with _{j (+)} is taken as the error signal δ _{j (+)} output from the self unit to the nerve cell unit of the immediately preceding layer. Similarly, the error signal [delta] _j determined as in FIG. 20 _(-) and the error signal [delta] _j determined as in FIG. 22 _(-) takes the OR of, it of the previous layer from the self-unit nerves The error signal δ _{j (-)} is output to the cell unit. To summarize the above,
It becomes as shown in the equation (8).

[0031]

[Equation 5]

Further, a function corresponding to the learning rate (learning constant) may be provided. When the rate is 1 or less in the numerical calculation, the learning ability is further enhanced. This can be realized by thinning out the pulse train in the pulse train calculation. Here, a counter-like idea is adopted, and the ones shown in FIGS. 23 and 24 are adopted. For example, at the learning rate η = 0.5, every other pulse train of the original signal is thinned out, but even if the pulses of the original signal are not evenly spaced, the original pulse train can be thinned out. 23 and 24, when η = 0.5, every other pulse is thinned out, when η = 0.33, every two pulses are left, and when η = 0.67, two pulses are left.
Indicates that every other thinning is performed once. In this way, the function of the learning rate is provided by thinning out the error signal.

C. Method of changing each coupling coefficient by error signal The signal flowing through the line (see FIG. 12) to which the coupling coefficient to be changed belongs and the error signal are ANDed (δ _j ∩
y _i ). However, in this embodiment, the error signal has two values of + and −.
Since there are two signals, each of them is calculated and obtained as shown in FIGS. The two signals thus obtained are designated as ΔT _{ij (+)} and ΔT _{ij (-)} , respectively.

Next, based on this ΔT _ij , a new T
_ij is obtained. Since this T _ij is an absolute value component, it is classified depending on whether the original T _ij is excitatory or inhibitory. In the case of excitability, the component of ΔT _{ij (+)} is increased with respect to the original T _ij , and ΔT
Reduce the components of _{ij (-)} . That is, it becomes as shown in FIG. On the contrary, in the case of the suppressive property, the component of ΔT _{ij (+)} is reduced and the component of ΔT _{ij (−)} is increased with respect to the original T _ij . That is, FIG.
As shown in 8.

The above is summarized as in equation (9).

[0036]

[Equation 6]

The network is calculated based on the above learning rule.

Next, an actual circuit configuration based on the above algorithm will be described. 29 and 30 show examples of the circuit configuration, the configuration of the entire network is similar to that of FIG. FIG. 29 shows a circuit corresponding to a line (connection) in FIG. 12, and FIG. 30 shows a circuit corresponding to a circle (each nerve cell unit 20) in FIG. By forming the circuits for obtaining the error signals in FIGS. 29 and 30 or the final layer into a network as shown in FIG. 12,
A digital neural network capable of self-learning can be realized.

First, FIG. 29 will be described. In the figure, 25 is an input signal to the nerve cell unit and corresponds to FIG. The value of the coupling coefficient as shown in FIG. 14 is stored in the shift register 26. The shift register 26 has an outlet 26a and an inlet 26b, but may be any one having the same function as a normal shift register, for example,
It may be a combination of a RAM and an address controller. The input signal 25 and the coupling coefficient in the shift register 26 are ANDed by a logic circuit 28 having an AND gate 27 and performing the processing shown in FIG.
The output of the logic circuit 28 must be divided into groups depending on whether the coupling is excitatory or inhibitory, but it is better to prepare the outputs 29 and 30 for each group in advance and switch which one is output. It is highly versatile.
Therefore, here, a bit indicating whether the coupling is excitatory or inhibitory is stored in the grouping memory 31, and the switching gate circuit 32 switches using the information. The switching gate circuit 32 includes two AND gates 32a and 32b.
And an inverter 32c interposed at one input.

Further, as shown in FIG. 30, gate circuits 33a and 33b having a plurality of OR gates for performing respective input processes (corresponding to FIG. 16) are provided. Furthermore, as shown in the figure, the excitatory coupling group shown in FIG. 17 is “1”,
A gate circuit 34 including an AND gate 34a and an inverter 34b that outputs an output "1" only when the inhibitory coupling group is "0" is provided.

Next, the error signal will be described. The processing as shown in FIGS. 19 to 22 for calculating the error signal in the intermediate layer is performed by the gate circuit 42 having the AND gate structure shown in FIG.
44 is obtained. As described above, it is necessary to classify the connection depending on whether it is excitatory or inhibitory. In this case, the information on excitatory or inhibitory stored in the memory 31 and the +,-signals 45 and 46 of the error signal are used. The gate circuit 47 having AND and OR gate configurations is used. Further, the calculation formula (8) for collecting the error signals is performed by the gate circuit 48 having the OR gate structure shown in FIG. Further, the processing of FIGS. 23 and 24 corresponding to the learning rate is performed by the frequency dividing circuit 49 shown in FIG. Finally, the part for calculating a new coupling coefficient from the error signal, that is, the part corresponding to the processing of FIGS.
This is performed by the gate circuit 50 having the OR gate configuration, and the content of the shift register 26, that is, the value of the coupling coefficient is rewritten. This gate circuit 50 also needs to be classified depending on the excitability and inhibitory property of the coupling, but the gate circuit 47 performs this.

[0042]

However, since such a neural network is originally for performing parallel processing, it is necessary that the data of the input signal and the data of the output signal are also parallel to each other. is there. In particular, in the case of handling the signal of the pulse density expression system as in the above-mentioned proposed example, it is necessary to prepare a counter for each neuron of each output layer on the output side and convert the signal of the pulse density expression into binary data. Therefore, when the number of neurons in the output layer is N, N counters are also required, and when the value of N becomes large, it becomes physically impossible to configure with a discrete device.

Incidentally, as a method for solving such a drawback, there is a method in which a pulse for one data is latched and then only one counter counts. However, according to such a method, the time series processing is performed, and a great deal of processing time is required. For example, assuming that the number of neurons in the output layer is N and the maximum pulse width in one data is p, the time series processing causes an extra time of N · p as compared with the case of parallel processing. is there. Further, the output calculation must be stopped during the counting process. After all, parallelism cannot be maintained.

[0044]

According to a first aspect of the present invention, there is provided a memory for holding a coupling coefficient for each of a plurality of input signals represented by a pulse density, and a logical operation between each corresponding input signal and the coupling coefficient. First computing means for performing, grouping means for dividing the computation result by the first computing means into an excitatory coupling group and an inhibitory coupling group, and a logical sum computing means for computing a logical sum in each group, Second arithmetic means for performing a logical operation of the arithmetic result of these logical sum arithmetic means, and coupling coefficient variable means for calculating a new coupling coefficient based on the input of a plurality of error signals to change the coupling coefficient on the memory. In a signal processing device in which a plurality of signal processing means having the above are connected to form a signal processing circuit network, each output signal of the signal processing means is temporally expanded to the final output stage of the signal processing circuit network. It provided the output counter by a pair of one-dimensional light receiving means planarly to correspond to the two-dimensional light-emitting device and the two-dimensional light emitting means for outputting simultaneously Te.

According to the second aspect of the invention, branching means is provided on the input side of the two-dimensional light emitting means for branching the output signal into the error signal generating means and the two-dimensional light emitting means.

In the third aspect of the invention, the A / D conversion means for converting the output signal from the one-dimensional light receiving means into a digital signal is provided on the output side of the one-dimensional light receiving means.

Further, in the invention of claim 4, the A / D
The output side of the converting means is provided with signal selecting means for transferring an arbitrary output signal onto the data bus.

[0048]

According to the first aspect of the present invention, since the output counter has an optical device configuration including a pair of the two-dimensional light emitting means and the one-dimensional light receiving means, a large number of output signal data can be output while maintaining parallelism. It can count and output at high speed. In addition, since the configuration is relatively simple, a large amount of output signal data can be handled with a smaller occupied area than in the case of using an electronic device. Furthermore, since the output from the one-dimensional light receiving means of the output counter is obtained as a digital signal converted into an analog signal, a new D / A converter is not required in the output portion.

According to the second aspect of the present invention, the output signal is branched by the branching means in the preceding stage of the two-dimensional light emitting means for error signal generation and two-dimensional light emitting means.
The learning calculation function can be exerted while maintaining the function of the forward calculation according to the invention of claim 1.

Further, according to the invention of claim 3, 1
Since the A / D converting means for converting the output signal from the three-dimensional light receiving means into a digital signal is provided and the final output is a digital signal, it can be used for more signal processing.

According to the invention described in claim 4, in addition to the invention described in claim 3, a signal selecting means for transferring an arbitrary output signal onto the data bus is provided, so that an information processing apparatus such as a computer is provided. Output data can also be taken in and various processing is possible.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. The basics of the configuration and operation of a digital signal processing circuit network (neural network) that handles signals of pulse density expression are shown in FIGS.
It is based on the proposal example shown in. This embodiment relates to the final output stage of the network,
On the circuit board 51, the integrated circuit 52 that executes the neuro operation as in the above-described proposed example is mounted. In addition, the integrated circuit 52 and the transmission line 53 are provided on the circuit board 51.
An output counter 54 to which an output pulse, which is a result of the neural network operation output through the input, is input is mounted. This output counter 54 is based on an optical device, and has an LED matrix array 55 provided as a two-dimensional light emitting means provided on the input side and a PD array 56 provided as a one-dimensional light receiving means provided on the output side in a closely contacting plane. Are opposed to each other and are laminated. An output transmission line 57 extends from the PD array 56.

In such a configuration, the neural network of the present invention performs bit logic operation on the signal of pulse density expression as in the proposed example. Therefore, the signal transmitted on the transmission line 53 is also a signal represented by pulse density. Further, the signal is transmitted in parallel even when there are a plurality of transmission lines 53. In this embodiment, the number of transmission lines 53, that is, the number of neurons in the output layer is 100. Further, it is assumed that the maximum number of pulses in the pulse density expression is 100, and a pulse signal as shown in FIG. 2 is transmitted through 100 transmission lines 53, for example. That is, the data is expressed by the number of pulses in 100 pulses of the clock CLK.

The LED matrix array 55 is for converting such a signal into a spatial optical signal. For example, as shown in FIG. 3, 100 rows and 100 columns = 10,000 LEDs 58.
It is composed by. Here, each row of the LED matrix array 55 is individually assigned to each output layer neuron, and time is assigned to each column direction. FIG. 3 shows a pulse train signal as shown in FIG.
Row = 10,000 LEDs 58 are assigned and converted into a spatial optical signal.
Eight portions show a lighting state in which the pulse is on (H level). Although any LED driving method may be used, at least the required LED 58 must be turned on when one data input is completed. As such a driving method, there is a matrix driving method.

The PD array 56 which receives the spatial light signal from the LED matrix array 55 is shown in FIG.
As shown in FIG. 5, it is composed of, for example, 100 photodetector elements (PD) 59 which are not divided in the row direction but are formed in a strip shape corresponding to each neuron. Here, the light-emitting side is two-dimensional, but the light-receiving side is one-dimensional, and the dimension is reduced because the signal of the pulse density expression obtained from the LED matrix array 55 is converted into binary data. .. That is, each photodetecting element 59 formed in a strip shape serves as a counter that counts the number of pulses (that is, in the row direction) by utilizing the portion where the relationship between the output value and the input light intensity changes linearly. The sum of the light intensities of the LEDs 58 that are lit is obtained). Therefore, the operation output signal by the neural network is obtained from the PD array 56 in the state of an analog signal.

As described above, according to the present embodiment, since the output counter 54 has an optical device configuration, it is possible to count and output a large number of output signal data at high speed while maintaining parallelism. In addition, since the configuration is relatively simple, a large amount of output signal data can be handled with a smaller occupied area than in the case of using an electronic device. Furthermore, since the output from the PD array 56 in the output counter 54 is obtained as a digital signal converted into an analog signal, a new D / A is added to the output portion.
No conversion device required.

The LED matrix array 55 and the PD
The array 56 does not necessarily have to be in close contact with the array 56 as illustrated, and an optical element such as a condenser lens may be interposed therebetween. In short, it is only necessary that they have a corresponding layout relationship when viewed two-dimensionally. The one-dimensional light receiving means is structurally L
It may be a two-dimensional one such as the ED matrix array 55, and the point is that the result can be handled one-dimensionally, and a CCD or the like may be used.

Next, an embodiment of the invention described in claim 2 will be described with reference to FIG. The same parts as those shown in the above-mentioned embodiments are designated by the same reference numerals (the same applies to the following embodiments). In this embodiment, it is assumed that the integrated circuit 52 receives an output layer output and a comparison signal of the teacher signal from the outside, and the output signal from the integrated circuit 52 is branched on the transmission line 53 into two systems. The branching means 60 is provided. The branching means 60 outputs the output signal from the integrated circuit 52 to the LED matrix array 55 as in the above embodiment.
While outputting as a signal for the pulse density transmission line 61
Is transmitted to the output-teacher signal comparison device 62 for error signal generation, and is output from the output-teacher signal comparison device 62 to the integrated circuit 52 through the comparison signal transmission line 63.

In such a structure, the output signal from the integrated circuit 52 for performing the neuro operation is branched by the branching means 60 into the signal for the LED matrix array 55 and the signal for the output-teacher signal comparing device 62. In response to this, L
On the ED matrix array 55 side, the same processing as in the above-described embodiment is performed and an output signal is obtained. On the other hand, the output-teacher signal comparison device 62 generates a comparison signal based on the algorithm and outputs it to the integrated circuit 52.

Therefore, according to the present embodiment, the learning operation function can be exerted while maintaining the same forward operation function as in the above embodiments.

Further, an embodiment of the invention described in claim 3 will be described with reference to FIG. In this embodiment, the output side of the output counter 54, that is, the output side of the PD array 56 is provided with A / D conversion means 64 for converting the output signal (analog signal) of each photodetection element 59 into a digital signal. It is a thing.
It should be noted that the A / D conversion means 64 has an input side which amplifies the output from each photodetection element 59 to obtain the A / D conversion means 6.
4 is provided with an analog drive circuit section 65.

In such a configuration, each photodetector element 5
The output signal from 9 is amplified by the analog drive circuit section 65, input to the corresponding A / D conversion means 64, converted into a digital signal, and output to the outside through the output transmission line 57. At this time, the bit number of the A / D conversion means 64 is set to a value larger than the maximum pulse number.

Therefore, according to this embodiment, since the final output is a digital signal, it can be used for more signal processing.

If an analog signal is desired to be obtained as the final output, branching means may be provided in front of the A / D converting means 64 so that a signal not passing through the A / D converting means 64 can be obtained. ..

Further, an embodiment of the invention described in claim 4 will be described with reference to FIG. In the present embodiment, in addition to the configuration of the above-described embodiment, a selector 66 is provided as a signal selection means so that any one of the outputs of the plurality of A / D conversion means 64 can be selected. The signal selected by the selector 66 is the data bus 67 located outside the circuit board 51.
The data is sent to the upper side and output to a computer or the like via the data bus 67.

In such a configuration, only one of the output signals converted into a digital signal and held by each A / D conversion means 64 is selected by the selector 66 and sent to the data bus 67. It The signal transmitted on the data bus 67 is taken into a computer or the like. Therefore, according to the present embodiment, the output data can be taken in the information processing device such as a computer and various processings can be performed.

[0067]

According to the first aspect of the present invention, the output counter has the optical device structure including the pair of the two-dimensional light emitting means and the one-dimensional light receiving means. Therefore, many output counters are maintained while maintaining parallelism by the signal processing network. Output signal data can be counted and output at high speed, and because the configuration is relatively simple, it is possible to handle a large number of output signal data with a smaller occupied area compared to the case of using an electronic device. Furthermore, since the output from the one-dimensional light receiving means of the output counter is obtained as a state in which a digital signal is converted into an analog signal, a new D / A conversion device is not required in the output portion.

According to the second aspect of the invention, the branching means is provided in the preceding stage of the two-dimensional light emitting means so that the output signal is branched into the error signal generating and the two-dimensional light emitting means. The learning calculation function can be exerted while maintaining the function of the forward calculation according to the invention described in Item 1.

Further, according to the invention of claim 3, 1
Since the A / D converting means for converting the output signal from the three-dimensional light receiving means into a digital signal is provided and the final output is a digital signal, it can be used for more signal processing.

According to the invention of claim 4, in addition to the invention of claim 3, a signal selecting means for transferring an arbitrary output signal onto the data bus is provided, so that an information processing apparatus such as a computer is provided. Output data can also be taken in and various processing is possible.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing an embodiment of the invention described in claim 1.

FIG. 2 is a timing chart showing a pulse density signal.

FIG. 3 is a plan view schematically showing a configuration example of an LED matrix array.

FIG. 4 is a plan view schematically showing a PD array configuration example.

FIG. 5 is a schematic plan view showing an embodiment of the invention described in claim 2.

FIG. 6 is a schematic plan view showing an embodiment of the invention as set forth in claim 3;

FIG. 7 is a schematic plan view showing an embodiment of the invention as set forth in claim 4;

FIG. 8 is a conceptual diagram showing one unit configuration showing a conventional example.

FIG. 9 is a conceptual diagram of the neural network configuration.

FIG. 10 is a graph showing a sigmoid function.

FIG. 11 is a logic circuit diagram for performing basic signal processing in the already proposed example.

FIG. 12 is a schematic diagram showing a network configuration example.

FIG. 13 is a timing chart showing an example of logical operation.

FIG. 14 is a timing chart showing an example of logical operation.

FIG. 15 is a timing chart showing an example of logical operation.

FIG. 16 is a timing chart showing an example of logical operation.

FIG. 17 is a timing chart showing an example of logical operation.

FIG. 18 is a timing chart showing an example of logical operation.

FIG. 19 is a timing chart showing an example of logical operation.

FIG. 20 is a timing chart showing an example of logical operation.

FIG. 21 is a timing chart showing an example of logical operation.

FIG. 22 is a timing chart showing an example of logical operation.

FIG. 23 is a timing chart showing an example of logical operation.

FIG. 24 is a timing chart showing an example of logical operation.

FIG. 25 is a timing chart showing an example of logical operation.

FIG. 26 is a timing chart showing an example of logical operation.

FIG. 27 is a timing chart showing an example of logical operation.

FIG. 28 is a timing chart showing an example of logical operation.

FIG. 29 is a logic circuit diagram showing a configuration example of each unit.

FIG. 30 is a logic circuit diagram showing a configuration example of each unit.

[Explanation of symbols]

 20 signal processing means 25 input signal 26 memory 27 first operation means 32 grouping means 33 logical sum operation means 34 second operation means 50 coupling coefficient changing means 54 output counter 55 two-dimensional light emitting means 56 one-dimensional light receiving means 60 branching means 64 A / D conversion means 66 Signal selection means 67 Data bus

Claims (4)

[Claims] 1. A memory for holding a coupling coefficient for each of a plurality of input signals expressed in pulse density, a first arithmetic means for performing a logical operation between the corresponding input signal and the coupling coefficient, and the first arithmetic means. Grouping means for halving the result of the calculation by the excitatory coupling group and the inhibitory coupling group, a logical sum computing means for computing the logical sum in each group, and a logical computation of the computational results of these logical sum computing means Do the second
A signal processing circuit in which a plurality of signal processing means, each having a computing means and a coupling coefficient varying means for calculating a new coupling coefficient based on the input of a plurality of error signals to change the coupling coefficient on the memory, are connected in a mesh form. In a signal processing device having a net formed therein, a two-dimensional light emitting means for temporally expanding and simultaneously outputting each output signal of the signal processing means to a final output stage of the signal processing circuit network, and a plane for the two-dimensional light emitting means. Corresponding to 1
A signal processing apparatus comprising an output counter provided as a pair with a three-dimensional light receiving means. 2. The signal processing apparatus according to claim 1, further comprising branching means provided on the input side of the two-dimensional light emitting means for branching an output signal into an error signal generating means and a two-dimensional light emitting means. 3. An A / D for converting an output signal from the one-dimensional light receiving means into a digital signal on an output side of the one-dimensional light receiving means.
The signal processing device according to claim 1 or 2, further comprising conversion means. 4. A signal processing apparatus according to claim 3, wherein signal output means for transferring an arbitrary output signal to the data bus is provided on the output side of the A / D conversion means.