JP3302712B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing for a neural computer or the like which imitates a nerve cell, which can be applied to control of various movements such as position control of a robot, temperature control of an air conditioner, orbit control of a rocket, and the like. Related to the device.

[0002]

2. Description of the Related Art In recent years, in the fields of character recognition, movement control, and associative memory, researches on systems that imitate the functions of nerve cells (neurons), which are basic units of information processing in living bodies, have been actively conducted. . A so-called neural network aims at parallel processing of information by using such a “neural cell mimic element” as a network. Many studies using computer simulations have been reported to realize such a neural network. However, since the amount of computation of the neural network is extremely large, it is indispensable to implement the hardware. For this reason, various types of hardware neural networks are currently being researched and developed, but those using conventional computers and software are generally used.

In this regard, for example, according to Japanese Patent Application Laid-Open No. Hei 2-201607, an attempt has been made to apply a neural network to a device having an unknown or complicated control system by hardware or software. FIG. 48 is a view showing the gist of this. In the applied control system for performing identification and control on the control target 1 and causing the output of the control target 1 to follow a target value, the past control input u (t) and control output A control device 2 that calculates an internal signal having y (t−d) as a component by a neural network 2a and generates a control input from the calculation result and a target value, and calculates the internal signal by a neural network 3 and calculates the calculation result And an identification device 3 for generating an identification value from the control output and the control output, and using the control input as a teacher signal to calculate the neural network 2a,
A learning device 4 for calculating the weight of 3a, and an input / output memory 5 for storing a control input u (t) and a control output y (t-d) and generating an internal signal are provided.

[0004]

However, when performing control in a system in which the input changes with time, in such a system using a conventional neural network,
Since some of the input / output information is stored in advance and the network is learned, it becomes very complicated, and a large-scale system configuration such as a computer and a memory is required for learning. In addition, when the condition of the system changes, it is necessary to re-learn each time, which is troublesome and not practical.

[0005]

According to the first aspect of the present invention, there is provided a signal processing means in which a plurality of neural cell imitating means are connected in a mesh by a digital logic circuit in which a self-learning means is attached to a neural cell imitating element; Signal converting means for converting an output signal from the signal processing means into an input signal for supplying the signal processing means, and an output signal converting means for converting an output signal from the signal processing means into an output signal for supplying the control target Means, a teacher signal generating means for automatically generating a teacher signal for learning the signal processing means in real time with the converted input signal and output signal as inputs,
Error signal generating means for generating an error signal to be input to the signal processing means based on the teacher signal generated by the teacher signal generating means and the output signal converted by the output signal converting means; and teaching with respect to the signal processing means and the converted input signal and the delayed signal by a predetermined time delay the input signal converted by the input signal conversion means as input and converted output signal by the output signal conversion means and the input signal to generate a signal, and another signal processing means for a plurality of neuronal cells mimicking means annexed to self-learning means into neurons mimic elements were connected to the network, a signal generated by the further signal processing means and said The input signal converted by the input signal conversion means is compared with a control target value and generated by the another signal processing means.
The converted signal is converted by the input signal converting means.
And a comparator that outputs a signal for causing the signal processing unit to learn only when the input signal is closer to the control target value than the input signal.

[0006]

[0007]

According to the hardware configuration of signal processing means in which a plurality of neuron mimic means are connected in a net by a digital logic circuit in which self-learning means is attached to a neuron mimic element,
Very fast processing speed including real-time learning,
Even if the signal from the control target changes over time, learning can be performed in real time, and control of the control target, which is impossible or difficult with a conventional system, can be performed accurately.

[0008]

An embodiment of the invention of EXAMPLES This will be described with reference to FIGS. 1 to 40. First, the principle configuration of the present embodiment will be described with reference to FIG. The controlled object 6 that attempts to control the movement is
It consists of a system that changes over time, but the change is
Self or something else, such as the surrounding environment, or both. The output signal x from the control target 6
Is a neural network 8 which is input to an input unit 7 serving as input signal conversion means and serves as an input signal i as signal processing means.
Is input to The output signal o of the neural network 8 is processed by an output unit 9 serving as output signal conversion means, and is input to the control target 6 as an output signal y for control.
Here, the neural network 8 has a self-learning function as described later, and the output signal j converted by the output unit 9 is output to the teacher unit 10 serving as teacher signal generation means.
Is input to the error signal generating unit 11 serving as an error signal generating means together with the true control output from the controller or the teacher signal m corresponding thereto, and an error signal d for learning is generated and input to the neural network 8. Therefore, the neural network 8 performs learning using the error signal d, and a signal y that is desired for the signal x in the control target 6 is obtained.
Is obtained.

As the signal y at the time of learning, a signal obtained by directly processing the teacher signal t at the output unit 9 may be used. Further, control may not be performed during learning, or conversely, learning may not be performed during control. The error signal d may be generated not using the teacher signal m and the signal j from the output unit 9 but using the signal j and the signal x from the control target 6. Furthermore, the error signal d does not always have to always correctly learn the network 8, and when it is determined that the current signal y output from the network 8 is not appropriate, a different signal y can be obtained. The signal d may be used.

The control system 12 is applied to, for example, attitude control, and is applied to a two-dimensional inverted pendulum control as shown in FIG. 2 as an example. This control system 12 is a pulse density type digital neuro LS
3 is used to control the pendulum 13 to be controlled 6 so that the pendulum 13 is always standing vertically. The pendulum 13 has a drive unit 14 at the top. The drive unit 14 has four propellers 15a to 15d provided around the pendulum 13 and motors 16a to 16d as shown in the plan view of FIG. It is supported so that it can fall in all directions. Such an installation section 17 is provided with an angle detection section 19 provided with a potentiometer 18 for detecting the tilt angle (angle information) of the pendulum 13. In addition,
The angle detection is not limited to the potentiometer 18, but a general angle detector such as a rotary encoder may be used.

The pendulum 13 rotates about the installation portion 17 by the propulsive force generated by the rotation of the propeller 15, and the tilt angle changes. Here, the potentiometer 18 is perpendicular to the two as shown in FIG.
Direction (X direction and Y direction).
Is detected, and the analog signal is input to the input unit 7. The input unit 7 converts the tilt angle information into digital data using the A / D converter 100, and converts the digital data into digital data.
By inputting and comparing the digital data of the previous time latched by the latch 101 with the comparator 102,
The binarized angular velocity of the pendulum 13 is obtained. At this time, the angular velocity may be obtained by using a subtractor or the like.
A third angular acceleration may be obtained. These digital data are converted into a pulse train by the pulse generator 103 and input to the neural network 8 to perform arithmetic processing. The pulse train generator 103 may be composed of, for example, a combination of an M-sequence random number generator including a multi-stage shift register and a comparator for comparing the output of the M series random number data such as angle. The configuration and operation of the neural network 8 will be described later.

The neural network 8 sends the output pulse train signal after the operation to the output unit 9. In the output unit 9, the pulse train signal is counted by the counter 104, and the comparator 105 performs threshold processing such as "1" when the count value exceeds a certain value, and "0" when the count value is less than a certain value. Output the processing result. Since the processing so far is performed at a high speed, the motor control signal from the output unit 9 becomes a pulse train and drives the motor 16 by PWM (pulse width modulation). However, the motor 16 may be driven by an analog voltage value (or current value) based on the value counted by the output unit 9 without being limited to the PWM drive, or the output pulse train signal itself is used without counting. Thus, it is also possible to perform PWM driving. When the rotation of the motor 16 is transmitted to the propeller 15, the drive unit 14 drives the pendulum 13 and is controlled to maintain the pendulum 13 in a vertical state.

For learning of the neural network 8, a remote controller operated by a human is used as the teacher unit 10. For this reason, the teacher unit 10 includes a plurality of potentiometers 107 and a comparator 108 which converts analog outputs from these potentiometers 107 into binary signals for turning on / off the motor 16. At the time of learning the system, the motor 16 is controlled by using a signal (teacher signal) from the teacher unit 10 so that the pendulum 13 is operated to stand vertically.
At this time, the control of the motor 16 is performed by the neural network 8.
May be used after processing the output from. This switching is performed by the selector 106.
Learning is performed by inputting an error signal generated by comparing the output signal from the network 8 with the teacher signal from the teacher unit 10 to the neural network 8 by the error signal generation unit 11 (the circuit configuration will be described later). Do.
The teacher signal provided from the teacher unit 10 is not limited to a binary signal of ON / OFF, and may be, for example, an analog signal similar to the signal obtained from the angle detection unit 17. What is necessary is just to convert into a digital signal.

Next, the basic concept of the neural network 8 having a neuron element configuration using a digital logic circuit having a self-learning function for performing the above-described processing at a high speed and various configuration examples will be described with reference to FIGS. . The neural network 8 of the present embodiment includes:
A plurality of neural cell mimic means provided with a self-learning means provided in a neural cell mimic element, having a coupling coefficient variable means and a coupling coefficient generating means for generating a variable coupling coefficient value of the coupling coefficient variable means based on an error signal with respect to a teacher signal. Are connected in a net shape.

First, the neural network 8 in the present embodiment is implemented by hardware using a digital configuration. The basic concept is as follows: input / output signals, intermediate signals,
The coupling coefficient, the teacher signal, and the like are all represented by binary pulse trains of “0” and “1”. The amount of the signal inside the network is represented by the pulse density (the number of “1” within a certain time). The calculation in the nerve cell unit is represented by a logical operation between pulse trains. The pulse train of the coupling coefficient is placed on the memory. Learning is realized by rewriting this pulse train. For learning, an error is calculated based on a given teacher signal pulse train, and the coupling coefficient pulse train is changed based on the error. At this time, the calculation of the error and the calculation of the change in the coupling coefficient are all performed by the logical operation of the pulse train of “0” and “1”. It is like that.

Hereinafter, this concept will be described. First, a neural cell unit using a digital logic circuit and signal processing by the network circuit will be described, and then, input and output of an analog signal to and from the network circuit will be described.

First, regarding signal processing by a digital logic circuit, signal processing in a forward process will be described. FIG. 4 shows a part corresponding to one nerve cell unit (neural cell mimic element) 20, and the entire network (neural network 8) is of a hierarchical type as shown in FIG. 5, for example. All inputs and outputs are binarized to “1” and “0” and synchronized. The intensity of the input signal y _i is represented by a pulse density, for example, by the number of states of “1” within a certain time as in a pulse train shown in FIG. That is, the example of FIG. 6 represents 4/6, and four signals “1” and two signals “0” are included in six synchronization pulses. At this time, the arrangement of “1” and “0” is desirably random as described later.

On the other hand, a coupling coefficient T _ij indicating the degree of coupling between the respective neuron units 20 is similarly expressed by a pulse density.
A pulse train of “0” and “1” is prepared in the memory in advance. The example in FIG. 7 is an equation representing “101010” = 3/6. Also in this case, it is desirable that the arrangement of “1” and “0” be random. How to determine specifically will be described later.

Then, this pulse train is sequentially read out from the memory in accordance with the synchronous clock, and each pulse train is read out as shown in FIG.
The ND gate 21 takes a logical product with the input signal pulse train (y _i Ｔ T _ij ). This is an input to the nerve cell j. In the case of the above example, the input signal is “10110
When it entered as 1 ", which the call pulse train from the memory in synchronization, by taking sequential AND," 101000 "is obtained as shown in FIG. 8, which is the input y _i is the coupling coefficient T _ij And the pulse density is 2/6
It is shown that it becomes.

The pulse density of the output of the AND gate 21 is:
It is approximately the product of the pulse density of the input signal and the pulse density of the coupling coefficient, and has the same function as the analog coupling coefficient. This means that the longer the signal sequence, the more "1"
The more random the arrangement of "0" and "0", the closer the function to the product of numerical values. Not random
It means that "1" (or "0") is dense (close). When the pulse train of the coupling coefficient is shorter than the input pulse train and there is no more data to be read, it is sufficient to return to the beginning of the data and repeat the reading.

Since one nerve cell unit 20 has a large number of inputs, there are also a large number of "ANDs between input signals and coupling coefficients", and the logical sum of them is then obtained by an OR circuit 22 which is a logic circuit. Since the inputs are synchronized, for example, if the first data is “101000” and the second data is “010000”, ORing the two results in “1”.
11000 ". If this is calculated and output as multiple inputs simultaneously, for example, the result is as shown in FIG. This corresponds to the sum calculation and the non-linear function (sigmoid function) in the analog calculation.

In the case where the pulse density is low, the pulse density obtained by taking the OR thereof approximately matches the sum of the respective pulse densities. As the pulse density increases, the OR circuit 22
Since the output becomes increasingly saturated, the output does not match the sum of the pulse densities, and nonlinearity appears. In the case of OR, the pulse density does not become larger than 1 and does not become smaller than 0, and furthermore, it is a monotonically increasing function, which is approximately equivalent to the sigmoid function.

By the way, the coupling has excitability and suppression. In the case of numerical calculation, it is represented by the sign of the coupling coefficient. In the case of an analog circuit, when T _ij is negative (suppression coupling), the amplifier is connected. The output is inverted to _connect to another neuron unit with a resistance value corresponding to T _ij . In this regard, in this embodiment of the digital system, first, each coupling is divided into two groups, an excitatory coupling and an inhibitory coupling, _{depending on} the sign of T _ij . The OR of “AND” is calculated for each group. And when only the output of the excitatory connection group is “1”,
It outputs “1” and outputs “0” when only the output of the inhibitory connection group is “1”. When both are “1” or “0”, either “1” or “0” may be output, or “1” may be output with a probability of about ２. In this example, the output “1” is output only when the output of the excitatory connection group is “1” and the output of the inhibitory connection group is “0”. In order to realize this function, AND of (NOT of the output of the inhibitory connection group) and (output of the excitatory connection group) may be obtained. That is,
As shown in FIG.

When expressed by logical expressions, they are expressed by the following expressions (1) to (3).

[0025]

(Equation 1)

The network of the neuron unit 20 is
Hierarchical type similar to back propagation (ie, FIG. 5)
And Then, if the entire network is synchronized, the calculation can be performed for each layer by the above-described function.

On the other hand, each connection is divided into two groups, excitatory connection and inhibitory connection, _{depending on} the sign of T _ij .
OR of "AND of pulse train of input signal and coupling coefficient"
Is calculated for each group, and then the output of the excitatory connection group is “0” and the output of the inhibitory connection group is “1”.
If an output is to be output other than in the case of (1), the OR of (NOT of the output of the inhibitory connection group) and (the output of the excitatory connection group) may be obtained.

Next, a signal calculation process in learning (back propagation) will be described. Basically, an error signal may be obtained by the following a or b, and then the value of the coupling coefficient may be changed by the method c.

First, an error signal in the last layer will be described as a. In the final layer, an error signal in each neuron unit is calculated, and based on the error signal, a coupling coefficient relating to the neuron unit is changed. The method of calculating the error signal for that purpose will be described. Here, in the present embodiment, the “error signal” is defined as follows. When the error is expressed numerically,
In general, both + and-can be taken. However, in the case of pulse density, since both positive and negative can not be expressed simultaneously, an error is calculated using two types of signals, ie, a signal representing a + component and a signal representing a-component. Express the signal. That is, the error signal of the j-th nerve cell unit is shown as in FIG. That is, the + component of the error signal is a pulse existing on the teacher signal side in the part (1, 0) or (0, 1) where the teacher signal pulse and the output pulse are different, while the-component is similarly output. This is the pulse present on the side. In other words, adding an error signal + pulse to the output pulse and removing the error signal-pulse results in a teacher pulse. That is, when these positive and negative error signals δ _{j (+)} and δ _{j (−)} are expressed by logical expressions, (4) and (5)
It looks like an expression. In the formula, EXOR represents exclusive OR. Based on such an error signal pulse, the coupling coefficient is changed as described later.

[0030]

(Equation 2)

Next, a method for obtaining an error signal in the intermediate layer as b will be described. First, the above error signal is back-propagated, so that not only the coupling coefficient between the final layer and the immediately preceding layer but also the coupling coefficient of the preceding layer changes. Therefore, it is necessary to calculate an error signal in each neuron unit in the intermediate layer. The error signal in each neuron unit in the next layer is collected in exactly the opposite way that the signal is propagated from the neuron unit in the middle layer to each neuron unit in the next layer. And uses it as its own error signal. This can be performed in the same manner as in the above-described arithmetic expressions (1) to (5) and the cases shown in FIGS. 6 to 10 in the nerve cell unit. However, the difference from the above-described processing in the nerve cell unit is that while y is a single signal, δ has two signals as positive and negative signals, and both signals are considered. It is necessary. Therefore, it is necessary to divide into four cases according to the sign of the coupling coefficient T and the sign of the error signal δ.

First, the case of excitatory coupling will be described. In this case, for a neuron unit having an intermediate layer, an error signal + at the k-th neuron unit in the next layer (final layer in FIG. 5) and the neuron unit and its own (the intermediate layer in FIG. 5) The AND of the coupling coefficient with the neuron unit with the difference (δ _{k (+)} ∩ T _jk ) is obtained for each neuron unit, and the OR between them is calculated as ｛∪ (δ _{k (+)} {T _jk )}. This is taken as the error signal + of this layer. That is, the result is as shown in FIG.

Similarly, an AND between the error signal and the coupling coefficient in the neuron unit in the next layer is obtained, and an OR between them is obtained to obtain an error signal in this layer. That is, the result is as shown in FIG.

Next, the case of inhibitory coupling will be described. In this case, the AND of the error signal in the neuron unit of the next layer and the coupling coefficient between the neuron unit and the self is obtained, and further, the OR of these is obtained. This is defined as an error signal + of this layer. That is, the result is as shown in FIG.

Further, the AND of the error signal + and the coupling coefficient, which is one step ahead, is obtained, and the OR between them is obtained, thereby similarly obtaining the error signal − of this layer. That is, FIG.
It becomes as shown in.

Since there are some excitatory couplings from one neuron unit to another neuron unit and some couplings with an inhibitory coupling, the error signal δ obtained as shown in FIG. _{j (+)} and the error signal δ obtained as shown in FIG.
OR with _{j (+)} and use it as the error signal δ _{j (+)} of the own nerve cell unit. Similarly, the error signal [delta] _j determined as in FIG. 13 _(-) and the error signal [delta] _j determined as in FIG. 15 _(-)
And the result is taken as the error signal δ _{j (−)} of the own nerve cell unit.

The above is summarized as shown in equation (6).

[0038]

(Equation 3)

Further, a function corresponding to the learning rate (learning constant) may be provided. When the rate is 1 or less in the numerical calculation, the learning ability further increases. This can be realized by thinning out the pulse train in the calculation of the pulse train. In the present embodiment, the concept of a counter is used, and the configuration is as shown in FIGS. For example, at the learning rate η = 0.5, every other pulse train of the original signal is thinned out, but even if the pulses of the original signal are not at equal intervals, the original pulse train can be thinned out. In FIGS. 16 and 17, every other pulse is thinned out when η = 0.5, every other pulse is left when η = 0.33, and two pulses are left when η = 0.67. Indicate that it is thinned once every other time.

In this way, the function of the learning rate is provided by thinning out the error signal. Such thinning of the error signal can be easily realized by performing a logical operation on the output of a commercially available counter or using a flip-flop. In particular, when a counter is used, the value of the learning constant η can be set arbitrarily and easily, so that the characteristics of the network can be controlled.

Incidentally, it is not necessary to always multiply the error signal by a learning constant. For example, it may be used only for the calculation for obtaining the coupling coefficient described below. Further, the learning constant used when the error signal is propagated in the opposite direction may be different from the learning constant used in the calculation for obtaining the coupling coefficient. This means that the characteristics of the nerve cell units on which the network 8 is placed can be individually set, and an extremely versatile system can be constructed. Therefore, it is possible to appropriately adjust the performance of the network.

Further, as c, a method of changing each coupling coefficient by such an error signal will be described. The AND between the signal flowing through the line (see FIG. 5) to which the coupling coefficient to be changed belongs and the error signal is obtained (δ _j ∩y _i ). However, in this embodiment, since there are two error signals, + and-, the error signals are calculated and obtained as shown in FIGS. Each of the two signals thus obtained is represented by ΔT
_{ij (+)} and ΔT _{ij (-)} .

Next, based on this ΔT _ij , a new T
_ij is obtained. Since T _{ij in the} present embodiment is an absolute value component, cases are classified depending on whether the original T _ij is excitatory or inhibitory. In the case of excitability, the component of ΔT _{ij (+)} is increased with respect to the original T _ij , and the component of ΔT _{ij (−)} is reduced. That is, the result is as shown in FIG. Conversely, in the case of inhibitory ΔT to the original T _ij
The component of _{ij (+)} is reduced and the component of ΔT _{ij (-)} is increased. That is, the result is as shown in FIG.

The network is calculated based on the above learning rules.

Next, an actual circuit configuration based on the above algorithm will be described. FIGS. 22 to 24 show examples of the circuit configuration. The configuration of the entire network 2 is the same as that of FIG. FIG. 22 shows a circuit corresponding to a line (connection) in FIG. 5, and FIG. 23 shows a circuit corresponding to a circle (each nerve cell unit 20) in FIG. FIG.
Shows a circuit for obtaining an error signal in the final layer from the output of the final layer and the teacher signal. These FIGS. 22 to 2
By forming the three circuits of the four configurations into a network as shown in FIG. 5, a digital neural network capable of self-learning can be realized.

First, FIG. 22 will be described. In the figure, reference numeral 25 denotes an input signal to the nerve cell unit, which corresponds to FIG. The values of the coupling coefficients as shown in FIG. 7 are stored in the shift register 26. The shift register 26 has an outlet 26a and an inlet 26b, but may have the same function as a normal shift register.
It may be a combination of an AM and an address controller. The input signal 25 and the coupling coefficient in the shift register 26 are ANDed by a logic circuit 28 having an AND gate 27 and performing the processing shown in FIG. The outputs of the logic circuit 28 must be grouped according to whether the coupling is excitatory or inhibitory. However, it is better to prepare the outputs 29 and 30 for each group in advance and switch to which output. It becomes highly versatile. Therefore, in the present embodiment, a bit indicating whether the coupling is excitatory or inhibitory is stored in the grouping memory 31 and the switching is performed by the switching gate circuit 32 using the information. The switching gate circuit 32 includes two AND gates 32a and 32b
And an inverter 32c interposed at one input.

As shown in FIG. 23, gate circuits 33a and 33b having a plurality of OR gates for processing each input (corresponding to FIG. 9) are provided. Further, as shown in FIG. 10, the excitatory connection group shown in FIG.
Thus, there is provided a gate circuit 34 including an AND gate 34a that outputs an output "1" only when the suppressive coupling group is "0" and an inverter 34b.

Next, the error signal will be described. The logic circuit 35 using the combination of AND and exclusive OR shown in FIG. 24 generates an error signal in the last layer, and corresponds to the equations (4) and (5). That is, error signals 38 and 39 are generated by the output 36 from the last layer and the teacher signal 37. The processing as shown in FIGS. 12 to 15 for calculating the error signal in the intermediate layer is performed by the gate circuit 42 having the AND gate configuration shown in FIG.
3, 44 are obtained. As described above, it is necessary to divide the case depending on whether the coupling is excitatory or inhibitory. In this case, information on whether the coupling is excitatory or inhibitory and the +/− signals 45 and 46 of the error signal are stored. AND, OR, depending on
This is performed by a gate circuit 47 having a gate configuration. The calculation formula (6) for collecting error signals is performed by a gate circuit 48 having an OR gate configuration shown in FIG. Further, the processing of FIGS. 16 and 17 corresponding to the learning rate is performed by the frequency dividing circuit 49 shown in FIG. Finally, a part for calculating a new coupling coefficient from the error signal, that is, a part corresponding to the processing of FIGS. 18 to 21 is performed by the gate circuit 50 having the AND, inverter, and OR gate configuration shown in FIG. The content of the shift register 26, that is, the value of the coupling coefficient is rewritten. The gate circuit 50 also needs to be classified according to the excitability and the suppression of the connection.

Here, the grouping method and the output determining method shown in FIGS. 22 and 23 are extracted and shown in FIG.
become that way. That is, side dishes grouped at the input stage, the input 25 shift register 26 memory comprising storing the coupling coefficient with respect _{ij ij} are provided separately, a memory 31 for grouping the logical result of the AND gate 27 _ij
Is divided into two groups via a switching circuit 32 in accordance with the contents of
The OR gate 33b obtains a logical sum on the side of the OR gate 33b. Thereafter, the gate circuit 3
4 to determine the output.

It should be noted that such a method of grouping the excitatory connection and the inhibitory connection may be configured as shown in FIG. 26, for example. That is, at the input stage, a group of excitatory couplings a and a group of inhibitory couplings b are grouped in advance, and a memory of at least 2 bits or more storing a coupling coefficient T _ij for each input 25 _ij , specifically Is provided with a shift register 51. Thereafter, the same processing may be performed for each group through the OR gates 33a and 33b. 52 is an AND gate.

The gate circuit 34 is shown in FIG.
As shown in (1), the OR operation may be performed by using an OR gate 34c instead of the AND gate 34a.

As shown in FIG. 28, a learning constant setting means 62 for arbitrarily setting the learning constant used in the coupling coefficient variable circuit from outside may be provided. That is, the learning constant (learning rate) used at the time of learning indicated by
Is variable, and a network circuit with performance that is suitable for the application is obtained. Function is added.

First, the learning constant setting means 62
A counter 63 to which an error signal is input is provided in place of the frequency dividing circuit 49 shown therein.
, And OR gates 64 to 67 and one AND gate 68 for performing a logical operation on the output of. More specifically, when all the switches Sa to Sd provided on the respective inputs of the OR gates 64 to 67 connected to the binary outputs A to D of the counter 63 are set to the H level, η = 1.0
Η = 1/16 when the switches Sa to Sd are all set to the L level. Therefore, if the number of switches on the H level side is N, η = (2 N) / 16. Therefore, the learning constant can be arbitrarily set by using a switch (or an external signal instead of the switch). When the pulse density is used as the clock input of the counter 63, an AND gate 69 may be appropriately provided for the input of the error signal. The learning constant setting means 62 is not limited to such a circuit configuration. In addition, by providing a plurality of such learning constant setting means 62 or by appropriately controlling the learning constant using an external signal, the value of the learning constant used for calculating the coupling coefficient and the value of the learning constant used for back-propagation of the error signal can be reduced. Can be different.

Further, it may be configured as shown in FIGS. 29 to 31. That is, as described above, two types of coupling coefficients, excitatory and inhibitory, are prepared in the basic idea described above, and the operation result for the input signal is calculated based on the result of using each coupling coefficient. Decide by majority from the ratio to increase network flexibility. Function is added.

First, one neuron unit has two coupling coefficients, excitatory and inhibitory. The output result of “AND between input signal and coupling coefficient” is the same as that for excitatory coupling. In this case, the treatment is performed at the ratio of the case of the inhibitory binding. Here, the processing by the ratio means the number of cases where the output result obtained by using the excitatory coupling coefficient is “1” for a plurality of input signals calculated in synchronization, Is compared with the number when the output result obtained is “1”, and when the latter is larger than the former, “0” is output, otherwise, “1” is output by the neuron unit. Means that. Alternatively, when both are equal, “0” may be output.

FIGS. 29 and 30 show examples of the circuit configuration for this purpose. First, for each input 25, one set of memories, specifically, a shift register 70a,
70b is provided. These shift registers 70
a and 70b have a data take-out port and a data entrance similarly to the shift register 26, but one shift register 70a stores an excitatory coupling coefficient and the other shift register 70b stores an inhibitory coupling coefficient. It was done. The contents sequentially read out from these shift registers 70a and 70b by reading means (not shown) are
Are input to the corresponding AND gates 71a and 71b, and are logically ANDed. There are two types of such logical results, one of which is excitatory and the other of which is inhibitory.
The signal is input to the majority circuit 72 and the output is determined. That is,
The digital signal of the operation group using the excitatory coupling coefficient based on the shift register 70a is added by the amplifier 73a. Similarly, the digital signal of the operation group using the suppressive coupling coefficient based on the shift register 70b is output from the amplifier 73b. The addition processing is performed, and the magnitude of the two is determined by the comparator 74 by majority decision. The majority circuit 72
Is not limited to the illustrated example, and may be a general majority circuit.

FIG. 31 shows the extracted grouping method shown in FIG. 29. That is, the coupling coefficient between the excitatory coupling and the inhibitory coupling is stored for each input.
A pair of memories (shift registers) 70a and 70b are prepared, and a process until a logical product is obtained for each group divided into memory groups is performed.

In the example shown in FIG. 31, in place of the majority decision circuit 72, OR gates 33a and 33b and the like which take a logical sum for each group are shown as in FIGS. The gate circuit 34 in this case may be configured as shown in FIG.

In FIG. 31, since one set of shift registers 70a and 70b is provided for each input 25, rewriting of the coupling coefficient by the self-learning function is also performed for each shift register 70a and 70b. Therefore, FIG.
As shown in FIG. 9, a self-learning circuit 75 for performing the processes of FIGS. 12 to 15 and (6) to calculate a new coupling coefficient using the error signals of + and-is provided. It is connected to the data entry side of 70a, 70b. According to this method, the connection of the nerve cell units is not limited to excitatory or inhibitory, so that the network has flexibility and versatility in practical applications.

The frequency dividing circuit 49 in the case of FIG. 30 may be replaced with the learning constant setting means 62 as shown in FIG.

The output decision method by the majority circuit 72 is not limited to the method having two memories (shift registers 70a and 70b) for each input as shown in FIG. The same can be applied to those having the memory 26. That is, instead of the combination of FIG. 22 and FIG. 23, the combination of FIG. 22 and FIG.

Further, a configuration as shown in FIGS. 32 to 36 may be adopted. That is, when the neuron mimic element constituted by the circuits shown in FIGS. 4 to 31 (hereinafter referred to as a neuron circuit) and its network (circuit network) are considered in a higher concept, all of them are represented by circuits. The signal processing may be performed by software according to the above-described procedure without the configuration, and an example thereof is shown.

That is, the functions of the neurons constituting the network are realized by software. First, in the case of a network as shown in FIG. 5, signal processing is performed by software in an arbitrary neuron constituting the network. The number of neurons using software may be one or all, or may be determined for each layer forming a network. FIG. 32 shows the configuration of a neuron that does not perform signal processing by a neuron circuit. Here, the input / output device 81 is connected to another neuron using a neuron circuit or a device that inputs / outputs a signal to / from a network, and transmits / receives a signal. The memory 82 stores software and data for controlling the CPU 83, and signals are processed by the CPU 83. The signal processing procedure is as described above,
FIG. 33 and FIG. 34 show again. FIG. 33 shows an algorithm in the forward process, and such signal operation processing is performed in a digital circuit or a computer. FIG. 35 shows the context of the neuron during the processing shown in FIG. FIG. 34 shows an algorithm in the learning operation process, and such signal operation processing is performed in a digital circuit or a computer. FIG. 36 illustrates the anteroposterior relationship of the neurons during the processing shown in FIG. FIG. 33 and FIG.
Software is created according to the procedure shown in FIG.
2 is stored. Here, FIG.
It is also possible to make one of the neurons function as a plurality of neurons. However, it is necessary to process the signal in a time-division manner.

By adopting such a configuration, the network configuration can be changed only by rewriting the memory 82 without making any hardware changes, thereby constructing a highly flexible and versatile network. Can be.

Further, the configuration may be as shown in FIG. In this method, a part of the function is executed by software in one neuron. That is, in the configuration shown in FIG. 32, by storing software based on the signal processing procedure shown in FIG. 33 in the memory 82, a neuron using software capable of executing a forward process can be realized. it can. To realize a neuron having a learning function, the input / output device 81 needs to be configured as shown in FIG.
2 or a circuit as shown in FIG. 29 may be added. In any case, the right half of FIG. 23 and the circuit portion shown in FIG. 24 are necessary. The circuit illustrated in FIG. 28 may be provided as appropriate. FIG. 37 shows a circuit for providing such a learning function as a learning circuit 84. Again,
The network configuration can be changed only by changing the software, and a highly flexible and versatile network can be constructed.

Further, when practically considered, ordinary electronic devices are often provided with a CPU in advance, so that it can be said that it is not necessary to newly provide a component as shown in FIG. Furthermore, if the system does not require a learning function,
The amount of hardware can be greatly reduced.

Further, as shown in FIG. 38, the learning process function may be realized by software. FIG.
In the configuration shown in FIG. 2, by storing software based on the signal processing procedure shown in FIG. 34 in the memory 82, it is possible to realize a neuron using software capable of executing a learning process. To realize a neuron having a forward process function, an input / output device 81
The circuit shown in FIGS. 22 and 23 or the circuit shown in FIGS. 22 and 30 may be added. The circuit illustrated in FIG. 27 may be provided as appropriate. FIG. 38 shows a circuit for providing such a forward process function as a forward circuit 85. Also in this case, the network configuration can be changed only by changing the software, and a highly flexible and versatile network can be constructed. In particular, it is easy to respond to a change in the learning rule. Also, in this case, in a normal electronic device, the CP
Paying attention to the fact that U is often mounted in advance, it can be said that it is not necessary to newly provide a component as shown in FIG. Furthermore, if the system does not require a learning function,
Since the amount of software can be reduced, the amount of hardware such as memory can also be significantly reduced.

According to the embodiment using such software, since the signal processing method can be executed only by digital logic operation, the required software may be in a low-level language, and the speed of the software may be reduced. Execution is also possible.

By the way, as the network structure of the neuron, besides the one shown in FIG.
Or a structure as shown in FIG. FIG. 39 shows, when the first aggregate 90, the intermediate aggregate 91, and the final aggregate 92 are arranged in this order from the input side (the aggregates can be classified in this manner even in FIG. 5), the nerves included in a certain aggregate This shows a state in which the cell unit 20 (o indicates a logical operation means) is not connected to all of the nerve cell units 20 included in another assembly. In FIG. 5, all the neuron units 20 in a certain assembly mutually transmit and receive signals to and from all the neuron units in another assembly. As shown in FIG. Does not have to fully connect the nerve cell units 20 in each assembly.

FIG. 40 shows the first aggregate 90 and the final aggregate 9
The network is configured as a four-layer structure using two-layer intermediate assemblies 93 and 94 between the two. Generally, an appropriate number of intermediate assemblies may be provided.

In FIGS. 39, 40, and 5, the number of neuron units 20 included in each assembly is shown as four, but these numbers are specific to those in the embodiment. As described in the example, the number is arbitrary, and the number of nerve cell units may be different for each assembly.

In any case, if processing is performed using the neural network 8 having the configuration as shown in the above configuration example, it is possible to perform real-time learning even for an input that changes with time. The object can be controlled accurately.

[0073] Subsequently, Fig another embodiment of the invention of this 41
47 will be described. First, the principle configuration of the present embodiment will be described with reference to FIG. Basically, the configuration is the same as that shown in FIG. 1. An output signal x from the control target 6 is input to the input unit 7 and input to the neural network 8 as an input signal i. This neural network 8
Is output by the output unit 9 and input to the control target 6 as an output signal y for control. Here, the output signal j converted by the output unit 9 is input to the error signal generation unit 11 together with the true control output from the teacher unit 10 or the teacher signal m corresponding thereto, and the error signal d for learning is provided.
Is generated and input to the neural network 8. Therefore, the neural network 8 performs learning using this error signal d, and the signal x
To obtain a desired signal y.

Here, in this embodiment, the teacher unit 10 has a function of automatically generating the teacher signal m, as will be described in detail later, and the signal converted by the input unit 7 (input signal ) H and a signal (output signal) 1 converted by the output unit 9 to generate a teacher signal m.

In this case as well, control may not be performed during learning, or conversely, learning may not be performed during control. The signal h may be the same as the signal x or the signal i, and the signal j or the signal 1 may be the same as the signal y or the signal o. Further, the error signal d does not always have to always correctly learn the network 8,
The signal y or the signal o output from the current network 8
May be a signal d such that a different signal y or signal o is obtained when it is determined that is not appropriate.

Thus, such a control system is applied to, for example, translational motion control as conceptually shown in FIG. In this translational motion control system, a driving unit 121 is mounted on a rail 120, and the driving unit 121 is moved to a certain point 122 on the rail 120 by the propulsive force of a propeller and stopped. A control system 123 having a configuration as shown in FIG. 41 (excluding the control target 6) is provided in the drive unit 121, and the position, speed, acceleration (or some points in time series) of the drive unit 121 are provided. ) Or the position of the point 122 is input, and the voltage value applied to the motor 125 for rotating the propeller 124 is output.
Further, by applying a voltage to the rail 120 and applying a slope to the value depending on the position, position information of the drive unit 121 can be obtained, and speed and acceleration can be obtained using the position information. When the control of the drive unit 121 is performed after learning the control system 123 in advance or while learning, the drive unit 121 can be moved from any position on the rail 120 to the point 122 and stopped. .

Now, generation of a teacher signal for learning the neural network 8 will be described with reference to a system example shown in FIG. There are various kinds of teacher signal generation means. In the first method, the propeller 124
Using the controller, the position of the drive unit 121 is known visually or by a television camera or the like, and is controlled to operate the drive unit 121 to stop at the point 122, and the control signal for the motor 125 at that time is used as a teacher signal. It is.

As a second method, a control amount of the motor 125 is obtained by another control means, and the control amount is used as a teacher signal.

As a third method, a teacher signal is calculated based on the initial values of the system and the dynamic system as shown in FIG. 42, and the teacher signal is given based on the time from the start of the system. .

As a fourth method, the teacher signal m is automatically generated based on the input signal h and the output signal l. In the present embodiment, the teacher signal is generated by the fourth method. It was made. FIG. 43 shows an example of the configuration of the teacher unit 10 for this purpose. A signal hd obtained by converting the input signal x from the control target 6 by the input unit 7 and delayed by a delay unit 126 for a certain time, and the neural network 8 A signal l obtained by converting the generated signal o at the output unit 9 and a signal ld obtained by delaying the signal l by a delay unit 127 for a predetermined time are input.
As a result of the control, a neural network 128 (hereinafter, neural network 8 is referred to as a first neural network 8) as another signal processing means for outputting a signal ht obtained by converting an input signal xt at the next time coming from the controlled object 6 at the input unit 7 as an output. 8, the neural network 128 is referred to as a second neural network 128), and a signal h at the current time is given as a teacher signal of the second neural network 128. After a number of learnings, the second neural network 128 has the correct signal h
t (the same signal as the teacher signal) is output. As a result, the second
The neural network 128 can predict a future input signal output from the control target 6. At this time, the signals h and l are used as inputs.

Here, the second neural network 12
Switching of signals h and hd is performed by selector 129, and switching of signals l and ld is performed by selector 130, depending on whether 8 is a learning process or a forward process.

Further, a comparator 131 for comparing the signal ht with the current input signal h with respect to the target value h0 is provided. The comparator 131 learns the first neural network 8 only when the signal h is closer to the target value h0 than the signal ht as shown in the flowchart of FIG. m, and otherwise, a signal k for controlling the first neural network 8 not to learn.
Is output to the first neural network 8. The first neural network 8 receives the signal i as an input and the control amount o at that time as an output.
The neural network 8 also outputs a correct control amount o by performing learning several times.

The second neural network 128
FIG. 45 shows a configuration example of the teacher unit 10 when the forward process and the learning process are simultaneously performed. That is, a neural network 128a for learning and a neural network 128b for forward are separately provided, and the coupling coefficient value is determined by the neural network 12 for learning.
8a from the forward neural network 128
b.

FIG. 46 shows a more specific circuit example of the teacher section 10 shown in FIG. First, digital signals representing the position, speed, acceleration, and rotation speed of the left and right propellers 124 from the system shown in FIG. 42 are input. At the time of learning of the second neural network 128, the signal is converted into a pulse train by the pulse converters 133 and 134 via the delay units 126 and 127 and the selectors 129 and 130,
The data is input to the second neural network 128. As the teacher signal, data obtained by subjecting the current time position to pulse density conversion is used. The output of the second neural network 128 when data at the current time which does not pass through the delay units 126 and 127 is input is converted to an up / down counter 135.
And the position data at the current time is input to the up side of the up / down counter 136. Then, a signal from the pulse generator 137 that outputs the target position at the pulse density is input to the down sides of the up / down counters 135 and 136. Therefore, the comparator 131 compares the count results of the up / down counters 135 and 136 with each other, and outputs a learning control signal to the first neural network 8 when the output from the second neural network 128 is larger. And let them learn.

The teacher signal at this time is generated as follows.
First, the rotation speed signal of the propeller 124 (the pulse generator 1
34) are prepared as preset values, while the output value from the second neural network 128 and the position data at the current time are input to the comparator 140 via the counter 139, and the magnitude thereof is increased or decreased. Compare. As a result of the comparison, when the output value from the second neural network 128 is larger, a pulse is output from one terminal side of the comparator 140 to one up side and the other down side of the up / down counter 138,
If the position data at the current time is larger, the comparator 1
A pulse is output from the two terminals 40 to one down side and the other up side of the up / down counter 138.
Outputs of these up / down counters 138 become teacher signals m for the left and right propellers 124.

When the input data is a pulse train,
The teacher unit 10 may be configured as shown in FIG. That is, the comparator 131 and the converter 132 are each connected to the logical operation circuit 1
41 and 142.

The present embodiment is not limited to the hardware configuration as in the above example, but may be another hardware configuration having an equivalent function. Alternatively, all of them may be realized by software.

[0088]

According to the present invention, as described above, according to the hardware configuration which is a signal processing means in which a plurality of nerve cell mimic means are connected in a mesh by a digital logic circuit in which the self-learning means is attached to the nerve cell mimic element, Since the processing speed including learning is very high, control is performed by configuring such a signal processing unit and an input signal conversion unit, an output signal conversion unit, a teacher signal generation unit, and an error signal generation unit in a system. Even if the signal from the object changes with time, learning can be performed in real time, and the control object can be accurately controlled at high speed.

[Brief description of the drawings]

1 is a block diagram showing an embodiment of this invention.

FIGS. 2A and 2B show an example of application to a two-dimensional inverted pendulum control system, wherein FIG. 2A is a configuration diagram and FIG.

FIG. 3 is a block diagram illustrating a specific configuration example of FIG. 1;

FIG. 4 is a logic circuit diagram for performing basic signal processing.

FIG. 5 is a schematic diagram illustrating a network configuration example.

FIG. 6 is a timing chart showing a logical operation example.

FIG. 7 is a timing chart showing a logical operation example.

FIG. 8 is a timing chart showing a logical operation example.

FIG. 9 is a timing chart showing a logical operation example.

FIG. 10 is a timing chart showing a logical operation example.

FIG. 11 is a timing chart showing a logical operation example.

FIG. 12 is a timing chart showing a logical operation example.

FIG. 13 is a timing chart showing a logical operation example.

FIG. 14 is a timing chart showing a logical operation example.

FIG. 15 is a timing chart showing a logical operation example.

FIG. 16 is a timing chart showing a logical operation example.

FIG. 17 is a timing chart showing a logical operation example.

FIG. 18 is a timing chart showing a logical operation example.

FIG. 19 is a timing chart showing a logical operation example.

FIG. 20 is a timing chart showing a logical operation example.

FIG. 21 is a timing chart showing a logical operation example.

FIG. 22 is a logic circuit diagram illustrating a configuration example of each unit.

FIG. 23 is a logic circuit diagram illustrating a configuration example of each unit.

FIG. 24 is a logic circuit diagram showing a configuration example of each unit.

FIG. 25 is a logic circuit diagram showing a configuration example of each unit.

FIG. 26 is a logic circuit diagram showing a modification.

FIG. 27 is a logic circuit diagram showing a modification.

FIG. 28 is a circuit diagram showing a different configuration example.

FIG. 29 is a circuit diagram showing still another configuration example.

FIG. 30 is a circuit diagram.

FIG. 31 is a circuit diagram.

FIG. 32 is a block diagram showing another configuration example.

FIG. 33 is a flowchart showing processing in a forward process.

FIG. 34 is a flowchart showing processing in a learning process.

FIG. 35 is a schematic diagram showing the front-back relationship of the Euron.

FIG. 36 is a schematic diagram showing the before-and-after relationship of the Euron.

FIG. 37 is a block diagram showing still another configuration example.

FIG. 38 is a block diagram showing another configuration example.

FIG. 39 is a conceptual diagram showing a modification of the network structure.

FIG. 40 is a conceptual diagram showing a modified example having a different network structure.

FIG. 41 is a block diagram showing another embodiment of the present invention .

FIG. 42 is a schematic configuration diagram illustrating an example of application to a translational motion control system.

FIG. 43 is a block diagram illustrating a specific configuration example of a teacher unit.

FIG. 44 is a flowchart showing a control process.

FIG. 45 is a block diagram showing another specific configuration example of the teacher unit.

FIG. 46 is a block diagram showing a specific configuration example of FIG. 43;

FIG. 47 is a block diagram showing a different specific configuration example of FIG. 43;

FIG. 48 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 6 Control target 7 Input signal conversion means 8 Signal processing means 9 Output signal conversion means 10 Teacher signal generation means 11 Error signal generation means 128 Another signal processing means 131 Comparator

Continuation of the front page (56) References JP-A-2-201607 (JP, A) JP-A-3-11458 (JP, A) JP-A-60-134905 (JP, A) JP-A-2-226425 (JP) JP-A-2-299002 (JP, A) JP-A-4-377204 (JP, A) JP-A-5-143108 (JP, A) International Publication 90/2381 (WO, A1) Hirotoshi Eguchi, et al. , "Pulse-density neuron model with learning function and its implementation", IEICE Technical Report, Japan, The Institute of Electronics, Information and Communication Engineers, Japan, October 25, 1990, Vol. 90, No. 273 (CPSY 90-64 to 74), pp. 63-70, Patent Office CSDB Document No .: CS NT199900846009 Mitsuo Kawahito, "Motion Control and Neural Net", Journal of the Institute of Electronics, Information and Communication Engineers, Japan, Japan Electronics Association Published by The Institute of Telecommunications, July 25, 1990, Vol. 73, No. 7, p.p. 706-711, Patent Office CSDB Literature No .: CSN199901334005 Toshio Fukuda, Takanori Shibata, "Adaptive Control of Position and Force Using Neural Network", Journal of the Robotics Society of Japan, Japan, published by The Robotics Society of Japan, 1991 Vol. 9, No. 6, pp. 94-99, Patent Office CSDB Document Number: CS NT199900393008 Masazumi Katayama, Mitsuo Kawahito, "Parallel Hierarchical Control Neural Network Model for Motion Control of Muscle and Skeletal System", Transactions of IEICE, Japan , The Institute of Electronics, Information and Communication Engineers, published, August 25, 1990, Vol. J73-D-II, No. 8, pp. 1328-1335, Patent Office CSDB Document No .: CCNT 199800681030 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06N 1/00-7/08 G06G 7/60 G05B 13/00-13/04 CSDB (Japan Patent Office) JST file (JOIS)

Claims (1)

(57) [Claims] 1. A signal processing means in which a plurality of neuron mimic means are connected in a mesh by a digital logic circuit in which a self-learning means is attached to a neuron mimic element, and an output signal from a control object is supplied to the signal processing means. Signal conversion means for converting the output signal from the signal processing means into an output signal for supplying the control target, and the converted input signal and output signal A teacher signal generating means for automatically generating a teacher signal for learning the signal processing means in real time with a signal as an input, and converting the teacher signal generated by the teacher signal generating means and the output signal converting means Error signal generating means for generating an error signal to be input to the signal processing means based on the output signal obtained, and an input signal converted by the input signal converting means. Generating a teacher signal for the signal processing means as an input signal a delay signal obtained by a predetermined time delay the converted input signal by the input signal conversion means as input and converted output signal by No. and the output signal converting means for the further signal processing means for a plurality of neuronal cells mimicking means annexed to self-learning means into neurons mimic elements were connected to the network, a signal <br/> No. generated by the further signal processing means and said The input signal converted by the input signal conversion means is compared with a control target value to the another signal processing means
The signal generated by the input signal converting means
And a comparator for outputting a signal for causing the signal processing means to learn only when the input signal is closer to the control target value than the converted input signal.