JPH05303547A - Scsi controller - Google Patents

Abstract

PURPOSE:To reduce the chip size at the time of LSI-implementation by multiplying instruction fields of a microcode of a controller which controls SCSI protocol. CONSTITUTION:This SCSI controller has a ROM 2 for storing microcodes, a sequencer 1 which performs sequence control, a PLA 5 which decodes instructions of the sequencer, a condition selector PLA 4 which selects jump conditions, and a PLA 3 for external signal control; and the microcodes in the ROM 2 are multiply defined, the PLA 3 for external signal control, condition selector PLA 4 which selects the jump conditions, and the PLA 5 which decodes the instructions of the sequencer decode required instructions to operate according to the specific SCSI protocol.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SCSI (small computer) used for hard disks, floppy disks and the like.
system interface) A controller for protocol control.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of a conventional SCSI control system. In FIG. 6, 21 is a CPU, 2
2 is a SCSI controller for performing SCSI control, 23
Is a drive controller for controlling the device, and 24 is C
A ROM that stores the program of the PU 21 and a RAM that is necessary to execute the program. Reference numeral 25 is a data bus of the CPU 21, and the CPU 21 and the SCSI controller 2
2, drive controller 23 and ROM / RAM2
4 are connected. Reference numeral 26 is an interrupt signal or status signal from the SCSI controller 22. A SCSI bus 27 is connected to another SCSI device.

The operation of the conventional SCSI control system configured as above will be described. In the initial state, SCSI
The bus 27 is in a bus-free state, and is in a state of waiting for a command to come after the initialization processing on the partner device side is completed. When a command is received from the SCSI bus 27, S
The CSI controller 22 activates the interrupt signal or the status signal 26 to notify the CPU 21. CPU 21 is an interrupt signal or status signal 2
When 6 is activated, the status of the SCSI bus 27 is changed according to the instruction procedure written in the ROM of the ROM / RAM 24. The CPU 21 controls the status on the SCSI bus 27 to control the SCSI protocol. Thus, in the conventional example,
Since the CPU 21 controls the SCSI bus state, even if an attempt is made to strengthen the control function for the device, it cannot be easily strengthened due to the limited function of the CPU 21.

FIG. 7 is a block diagram showing a configuration realized by microprogramming by adding a SCSI bus state control function to the SCSI controller 22 itself shown in FIG. In FIG. 7, 1 is a sequencer and 2 is a ROM
The microcode is stored inside. The sequencer 1 and the ROM 2 are connected by a sequencer address line 7. 3 is a PLA (pr which sends a control signal to the outside such as a SCSI state signal through the external control signal line 15).
In the ogrammable logic array), a part of the output of the ROM 2 is connected by the external control command line 13. Reference numeral 4 is a PLA for generating a condition code. The external condition signal 8 is input, a part of the output of the ROM 2 is connected by the condition select signal line 14, and the output is connected to the sequencer 1 by the condition signal 9. A part of the output of the ROM 2 is a command signal of the sequencer 1. A part 12 of the output of the ROM 2 is a jump destination address of the sequencer 1.

FIG. 8 is a diagram showing a structure of a bit field of a microcode for operating the block of FIG. As described above, when the program is realized by the microprogram, the bit width of the microcode increases, the size of the ROM 2 for storing the microcode increases, and as a result, the number of gates of the SCSI controller increases.

[0006]

However, in the above-mentioned conventional SCSI control system, since the CPU performs SCSI state control, there is a problem that the load of the CPU becomes heavy and it is not easy to add a function. A method of introducing a microcode control method into the SCSI control chip is also conceivable, but it has a problem in feasibility by increasing the number of gates of the chip itself.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent SCSI controller which can reduce the code capacity even if a microcode is adopted.

[0008]

[Means for Solving the Problems]

(Means 1) In order to achieve the above object, the present invention is provided with a function of performing a multiplexing process according to the type of an instruction field of a sequencer that performs microcode sequence control.
This is an attempt to reduce the width of microcode.

(Means 2) In order to achieve the above object, the present invention provides a jump destination address field of an instruction for jumping to an arbitrary address among instructions of a sequencer for performing microcode sequence control and an instruction of another control block. It is intended to reduce the width of the microcode by providing a function of multiplexing processing with the field.

(Means 3) In order to achieve the above object, the present invention provides an arbitrary address field of an instruction which repeats between a current address and an arbitrary address among other instructions of a sequencer which performs microcode sequence control, and other It is intended to reduce the width of the microcode by providing a function of multiplexing the instruction field of the control block.

(Means 4) In order to achieve the above object, the present invention provides a field and another control block for selecting a condition code of an instruction to jump to an arbitrary address among instructions of a sequencer for performing microcode sequence control. It is intended to reduce the width of the microcode by providing a function of multiplexing the instruction field with.

(Means 5) In order to achieve the above-mentioned object, the present invention is provided with a function of multiplexing the instruction field relating to the state change of the SCSI bus and the instruction field signal of another control block by the instruction field of the sequencer. , Is to reduce the width of the microcode.

(Means 6) In order to achieve the above object, the present invention is provided with a function of multiplexing the instruction field in accordance with the type of the microcode instruction to reduce the width of the microcode. Is.

(Means 7) In order to achieve the above object, the present invention has a function of multiplexing an instruction field relating to a state change of a SCSI bus and an instruction field signal of another control block, and has a width of a microcode. Is intended to be reduced.

[0015]

According to this structure, by multiplexing the control signals, the bit number of the microcode is reduced, the chip size of the SCSI controller is reduced, and it is possible to realize a SCSI controller capable of advanced control.

[0016]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, 1 is a sequencer. Reference numeral 2 is a ROM, which is connected to the sequencer 1 by a sequencer address line 7 and stores microcode therein. Reference numeral 5 is a PLA that generates an instruction to the sequencer, and ROM by an instruction line 10.
2 and is connected to the sequencer 1 by the sequencer command line 11. Also instruction line 10
Is connected to the sequencer 1 as a jump destination address. 4 is a PLA that generates a condition code
Then, the instruction line 10 is connected as a condition code selector, and the external condition signal 8 is also input. And it is connected to the sequencer 1 by the condition signal 9. 3 is a PLA which generates an external control signal, and an instruction line 1
0 is connected to the ROM 2 and is output by the external control signal line 15. FIG. 2 is a diagram showing a structure of a bit field of microcode for operating the block of FIG.

Next, the operation of the first embodiment constructed as above will be described. In the first embodiment described above,
All blocks operate by the microcode written in ROM2. The output from the ROM 2 becomes an instruction decoded by the PLA 5 and enters the sequencer 1 to operate. It is assumed that the sequencer 1 has a continue instruction that advances to the next address of the current address and a jump instruction that branches to a specified address. To execute the jump instruction, it is necessary to give the jump destination address.
On the other hand, the execution of the continue instruction does not require the jump destination address. Therefore, as shown in FIG. 2, it is possible to overlay the instructions by using the sequencer instruction. That is, the PLA3, PLA4, and PLA5 decode the necessary signal by the instruction of the sequencer, so that the jump destination address and the external control instruction can be defined in an overlapping manner. The lower bit field is selectively used. as a result,
The microcode bit width can be shortened, the storage capacity of the ROM 2 can be small, and the number of gates of the chip can be small.

(Embodiment 2) FIG. 3 is a diagram showing the structure of a bit field of a microcode for operating the block of FIG. 1 in the second embodiment. Using FIG. 1 and FIG.
The operation of the second embodiment will be described. Assume that the sequencer 1 operates as a continue instruction that advances to the next address of the current address and a repeat instruction that repeats between the current address and the specified address a specified number of times. Execution of the repeat instruction requires giving a repeat destination address, while execution of the continue instruction does not require the repeat destination address. Therefore, as shown in FIG. 3, it is possible to overlay the instructions by using the sequencer instructions. That is, PLA3, PLA4, and PLA5 decode the necessary signal by the instruction of the sequencer, so that the repeat destination address and the external control instruction can be defined in an overlapping manner. As a result, similar to the first embodiment, the bit width of the microcode can be shortened, the storage capacity of the ROM 2 can be small, and the number of gates of the chip can be small.

(Third Embodiment) The operation of the third embodiment will be described with reference to FIGS. It is assumed that the sequencer 1 has a continue instruction that advances to the next address of the current address and a jump instruction that branches to a specified address. To execute the jump instruction, it is necessary to give a condition select for the jump condition, while for execution of the continue instruction, the condition select for the jump condition is not necessary. Therefore, as shown in FIG. 3, it is possible to overlay the instructions by using the sequencer instructions. That is, the PLA3, PLA4, and PLA5 decode the necessary signal by the instruction of the sequencer, so that the condition select of the jump condition and the external control instruction can be defined in an overlapping manner. As a result, similar to the first embodiment, the bit width of the microcode can be shortened, the storage capacity of the ROM 2 can be small, and the number of gates of the chip can be small.

(Embodiment 4) FIG. 4 is a block diagram showing the configuration of the fourth embodiment of the present invention. 4, the same reference numerals as those in FIG. 1 indicate the same names and functions. The difference from FIG. 1 is that a PL that generates an external control signal similar to PLA 3 is generated.
A6 is input by the instruction line 10 and output by the external control signal line 15.

FIG. 5 shows the structure of the bit field of the microcode in the fourth embodiment for operating the block of FIG.

Next, the operation of the fourth embodiment will be described with reference to FIG.
Will be described with reference to FIG. Similar to the first embodiment, the entire block operates by the microcode written in the ROM 2. Similar to the second embodiment, according to the instruction of the sequencer, the jump destination address and the bit field of the microcode of the external control instruction are overlaid. In all the operations, the PLA 3 decodes to the external control signal line that must be controlled, and the instruction is defined in the field of the external control instruction 1 in FIG.
PLA 6 is a decoder for controlling the SCSI bus state, and the instruction is defined in the field of the external control instruction 2 in FIG. The change in the SCSI bus state is less frequent compared to the cycle in which the microcode moves in one clock, and the change in state occurs when the internal loop is in the standby state as in the second embodiment. Absent. Focusing on such a relationship, the instruction fields can be defined in an overlapping manner. As a result, similar to the first embodiment, the bit width of the microcode can be shortened, the storage capacity of the ROM 2 can be small, and the number of gates of the chip can be small.

The output from the ROM 2 becomes an instruction decoded by the PLA 5 and enters the sequencer 1 to operate. It is assumed that the sequencer 1 has a continue instruction that advances to the next address of the current address and a jump instruction that branches to a specified address. To execute the jump instruction, it is necessary to give a condition select for the jump condition, while for execution of the continue instruction, the condition select for the jump condition is not necessary. Therefore, as shown in FIG. 2, it is possible to overlay the instructions by using the sequencer instruction. That is, PLA3 and PLA
4 and the PLA 5 can decode the necessary signal by the instruction of the sequencer so that the condition select of the jump condition and the external control instruction can be defined in an overlapping manner. Bit field of is used selectively. As a result, the bit width of the microcode can be shortened, the storage capacity of the ROM 2 can be reduced, and the number of gates of the chip can be reduced.

[0024]

As is apparent from the above embodiment, the present invention is such that the instruction fields of the microcode are duplicated, the bit width of the microcode can be reduced, and the ROM capacity for storing the microcode is small. In addition, the number of gates of the chip can be small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a SCSI controller in first, second and third embodiments of the present invention.

FIG. 2 is a diagram showing a structure of a microcode instruction field according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the structure of an instruction field of microcode in the second and third embodiments of the present invention.

FIG. 4 is a block diagram showing a configuration of a SCSI controller according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a structure of a microcode instruction field in a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration of a conventional SCSI control system.

FIG. 7 is a block diagram showing a configuration of a conventional SCSI controller.

FIG. 8 is a diagram showing a structure of a microcode instruction field of a conventional SCSI controller.

[Explanation of symbols]

 1 Sequencer 2 ROM 3, 4, 5 PLA

Claims (7)

[Claims] 1. A sequencer for performing at least sequence control, a ROM for storing microcode, and a plurality of PLs.
A SCSI controller which is composed of A and which controls a SCSI protocol by microcode, and which has a multiplexing processing function depending on the type of the instruction field of a sequencer, thereby reducing the width of the microcode. 2. The SCSI controller according to claim 1, which has a function of multiplexing a jump destination address field of an instruction to jump to an arbitrary address and an instruction field of another control block among the instructions of the sequencer. 3. The SCSI according to claim 1, which has a function of multiplexing an arbitrary address field of an instruction that repeats between a current address and an arbitrary address among the instructions of the sequencer and an instruction field of another control block. controller. 4. The SCSI controller according to claim 1, wherein the SCSI controller has a function of multiplexing a field for selecting a condition code of an instruction jumping to an arbitrary address among the instructions of the sequencer and an instruction field of another control block. 5. The SCSI controller according to claim 1, which has a function of multiplexing an instruction field relating to a state change of a SCSI bus and an instruction field signal of another control block by an instruction field of a sequencer. 6. A sequencer for performing at least sequence control, a ROM for storing microcode, and a plurality of PLs.
A device for controlling the SCSI protocol by microcode, which has a processing function of multiplexing the instruction field according to the type of microcode instruction, thereby reducing the width of the microcode.
controller. 7. The SCS according to claim 6, further comprising a function of multiplexing an instruction field relating to a state change of the SCSI bus and an instruction field signal of another control block.
I controller.