JPH02205925A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the chip size of a microprocessor by optimizing a microprogram entry address so that an idle area in a microprogram ROM is reduced and coding a programmable logic array (PLA). CONSTITUTION:The output of a microprogram entry address generating PLA 110 is latched in a microprogram entry address latch 111. In this case, the microprogram entry address corresponding to each instruction is freely set by the microprogram entry address generating PLA 110. Therefore, an idle area between microprograms is deleted. Thus, the chip size of the microprocessor is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram entry address generation circuit in a microprocessor using a microprogram control system, and particularly to a technique for efficiently utilizing a microprogram ROM.

[Conventional technology]

Conventionally, microprogram control type microprocessors have used the entire code of an instruction, only the operation description field, or both the operation description field and the addressing description field as the microprogram entry address.

An example of this is MicroPro, as shown in Figure 8.

The microprogram entry address to be input to the ROM (hereinafter referred to as microROM) in which Durham is stored should be set to the minimum N such that the maximum number of microprogram steps ≤ 2 to the N power. Signals used hereinafter in the present invention N
is set to N as described above unless otherwise specified), there is a mapping method by shifting the instruction code by N to the MSB side.

Regarding the prior art, furthermore, an instruction decoder in the microprocessor and a microphrogram RO in the instruction execution section
This will be explained in detail with reference to FIG. 1O, which is a block diagram of M and its control circuit, and FIG. 11, which shows a microprogram mapping situation when implementing the prior art.

As shown in FIG. 9, throughout this specification, the instruction code is assumed to have an operation description field of 7 bits, an addressing mode description field of 2 bits or more, and several bytes of immediate value data as necessary.

The instruction decoding unit 101 extracts the operation description field in the instruction and provides a microprogram entry vector latch 102 for notifying the instruction execution unit. an immediate data register 103 for extracting and storing the immediate data 209 in the instruction; z a decoding control section 104 including a decoder for generating various decoding control information 208 such as decoding sequence/effective address calculation specification/operand specification; It consists of a decode sequence control section 105 that notifies the instruction execution section of the completion of instruction decoding.

The instruction code is stored in the operation description field 202 so that it can be easily decoded in the decoding process or in the previous process.
．． Addressing mode description field 204. Generally, it is divided into immediate value data or address displacement 203, and in this example, the explanation will be given assuming that each field has already been divided in the pre-decoding process.

Further, an instruction ready signal 206 indicates that each instruction field is completed, and the decode sequence control unit 10
5 and becomes a decoding sequence start signal.

The decode completion signal 207, which is the output of the decode sequence control unit 105, is sent to the instruction execution control unit 301 via the microprogram entry vector 2, which is the output of the microprogram entry vector latch 102.
05. This indicates that various information necessary for executing the instruction, such as immediate data 209 which is the output of the immediate data latch 103, has been prepared.

Regarding the operation of the instruction decoding unit, the instruction decoding unit 101
The first diagram is an operation timing diagram of the instruction execution control unit 301.
This will be explained with reference to FIG. Note that the instruction decoding unit 101 and the instruction execution control unit 301 use two-phase clocks φ1. Assume that φ2 is used.

The instruction decoding unit 101 uses two clock cycles as an operation unit, and the operation description field 202. Addressing mode description field 204, immediate data or address displacement 203 become valid at the beginning of φ2 (hereinafter referred to as φ2 synchronization), and the command whose valid signal is the valid signal at the beginning of φ1 half a clock later (hereinafter referred to as φ1 synchronization) Ready signal 206 becomes active. When the instruction ready signal 206 becomes active, the decode control information 208 output from the decode control unit 104 is activated;
The operation description field 202 is latched into the microprogram entry vector latch 102 at φ1 synchronization one clock after the instruction ready signal 206.

The decode information 208 is generally used to specify the effective address calculation of the operand and to control the decode sequence, but the details will not be discussed here as it is off topic here.

Further, by setting the decoding completion signal 207 at φ1 synchronization two clocks after the instruction is ready, it is indicated to the instruction execution control unit 301, which will be described below, that the decoded instruction is ready.

The instruction execution control unit 301 includes an instruction execution sequence control unit 3
02. Microprogram ROM 303゜Microprogram address latch 304゜Microprogram address multiplexer 305, Microprogram entry address shifter 306. Microprogram address incrementer 307. It consists of a microprogram ROM data latch 308.

The instruction execution sequence control unit 302 includes the instruction execution sequence control unit 3
It is in charge of the state transition of the execution sequence of 01. In this example, in order to simplify the explanation, the instruction execution state is limited to two states: a state in which the instruction execution section is waiting for the instruction decoding section to complete decoding (hereinafter referred to as the decoded instruction waiting state), and an instruction execution state. This will be explained using FIG. 13, which is a state transition diagram showing the process of transitioning between the two states.

The instruction execution sequence control unit 302 selects the microprogram entry address 401 as the next microprogram address 403 which is the output of the microprogram address multiplexer 305 in the decoded instruction waiting state. - Enable address selection signal 406, increment microprogram address 40
The increment microprogram address selection signal 407 is disabled to inhibit the selection of 5, and the microprogram address latch 304 contains the microprogram entry address 401 that has passed through the microprogram address multiplexer 305 due to the above operation. The value of is set as the output microprogram address 404 (hereinafter, the operation of outputting the input of the latch as is is referred to as putting the latch in the through state).
A microprogram address latch strobe signal 408 is provided as shown in FIG.

Here, the method of synthesizing the microprogram entry address 401, which is a feature of the conventional example, is that the microphone t-7'
The microprogram entry address shifter 306 adds N bits of zeros 402 to the LSB side of the microprogram entry vector 205 generated by the instruction decoder 101.

In addition, in the decoded instruction waiting state, all outputs of the microprogram ROM data latch 308 that latches and masks the output of the microprogram ROM 303 are inactive (hereinafter referred to as inactive).
To do this, the microprogram ROM data mask control signal 415 is enabled, and the microprogram ROM data latch strobe signal 409 is enabled to put the microprogram ROM data latch 308 in the through state.

Next, the transition operation from the decoded instruction waiting state to the instruction execution state will be described. Instruction decoding section 101
When the decoding of the instruction is completed, the decoding completion signal 207 is sent.
becomes active at the rising edge of the clock.

The instruction execution sequence control unit 302 samples the decoding completion signal 207 only in the decoded instruction waiting state,
When the decoding completion signal 207 becomes active, a microprogram entry address selection signal is sent to the microprogram address multiplexer 305 to output the increment microprogram address 403 to the next microprogram address 403 one clock later. 406 and active the incremental microprogram address 407 while simultaneously inactivating the microprogram ROM data mask control signal 415 to unmask the output of the microprogram ROM data latch 308.

As described above, when the microprogram ROM data mask control signal 415 is made inactive, the microcontrol information 414 coded in the microprogram ROM is actively transmitted to each circuit to be controlled.

The microprogram address latch 304 further latches the increment microprogram address 407 that is sequentially output to the next microprogram address 403 via the microprogram address multiplexer 305 from the first clock onward. The microprogram address 404 is the microprogram entry address 40 at the time the decoding completion signal 207 becomes active.
The values are sequentially incremented starting with a value of 1.

When the microprogram processing is completed, the microcontrol information 414 needs to be made inactive again unless the decoding completion signal 207 is active at that point, so the microprogram ROM data mask control signal 4 is
15 is made active, but if the decoding completion signal 207 is active at the end of the microprogram processing, the microprogram ROM data mask control signal 415 is made inactive and execution of the instruction following the microprogram processing is started. .

- The end of microprogram processing for an instruction is one of the microprogram information 414.
The instruction execution sequence control unit 302 is notified by a step end signal 410.

Furthermore, if a wait such as an operand wait is required for microprogram step progression, the necessary conditions are output to the micro wait condition 411, which is a part of the micro control information 414, and the instruction execution sequence control unit 302 The micro rendezvous condition 411 and the micro rendezvous target signal 412 which is the target for determining whether the condition is met.
Input and determine if the condition is met.

If it is necessary to wait in the microprogram processing as a result of the microprogram waiting condition determination, the microprogram address latch 304 and the microprogram ROM data latch 308 are set to the data holding state, respectively.・Latch strobe 408 and microprogram R
Disable the OM data latch storm signal 409.

FIG. 14 shows a detailed block diagram of the decode control section, which is the main control section explained in this conventional example, and FIG. 15 shows a detailed block diagram of the instruction execution sequence control section.

In a microprocessor having an instruction decoding unit and an instruction execution unit configured as described above, the microprogram for processing each instruction needs to be stored in the microprogram ROM 303 at intervals of 2 N microsteps in terms of circuitry. The microprogram mapping at that time is as shown in Figure 11.

Here, since the number of microprogram steps required for each command for boat fishing is different, there is an empty space in the microprogram ROM as shown in the shaded area in FIG.

FIG. 18 shows an example in which a microprogram for a microprocessor having addition instructions and test-and-set instructions is stored in the conventional microprogram ROM 303, and an example of the microprogram is shown in FIG.

(a) in Figure 11 is an addition instruction between registers rl and 12, and the addition result is stored in r2, and can be written in two lines using the microprogram (a) in Figure 18, whereas (b) is an instruction for adding between registers rl and 12. The semaphore test and set instruction used for synchronization (1) locks the external bus, 2) reads the memory operand that is the semaphore, and (3) checks whether the memory operand is F F (+6). The result is reflected in the condition flag, (4) the memory operand is written to p F (11), and (5) the external path is unlocked, which is written in 6 lines as shown in (b) of ,
When considering only these two instructions, N must be 3 or more, and when N = 3, the inter-register addition instruction in (a) is 6
The test and set instruction in microprogram step (b) results in a redundancy of two microprogram steps.

Incidentally, the relationship between the ALU and the register/memory/operand of the conventional example described above is shown for reference in FIG.

In addition, if you change the microprogram step number of the test-and-set instruction in (b) from 6 to 10 by changing the microprogram, it is necessary to expand N from 3 to 4. The free space in mapping is 20 as shown in Figure 16.
This means that there are 12 more steps than the 8 in the case of FIG. 11.

[Problem to be solved by the invention]

In the conventional microprogram entry address generation circuit described above, it was necessary to shift the instruction code and assign it to the microprogram entry address depending on the instruction that requires the largest microprogram ROM area. The size of the microprogram area allocated to the microprogram area is uniquely determined, and the microprogram ROM corresponding to the number of microprogram steps given by the maximum value becomes circuit redundant, which hinders the reduction of the microprocessor chip size. This was one of the factors.

In addition, as explained at the end of the conventional example above, if a microprogram for a certain instruction requires addition of a program that exceeds 2N steps given by N set at the beginning of design, the microprogram ROM itself must be significantly changed. This will further increase the redundancy of the circuit.

[Means to solve the problem]

The microprocessor according to the present invention has a PLA coded so that the operation description field in the instruction food is input and the microprogram entry address corresponding to the instruction operation is output.
Or, a PLA coded to input an addressing mode description field in addition to the operation description field in the instruction code and output a microprogram entry address corresponding to the instruction operation, or an operation description field in the instruction code. and addressing mode description fields are input to a decoder for independently grouping them, and the PLA is coded to take the decode generation as input and output the microprogram entry address corresponding to the instruction.

Thus, the instruction operation description field and the addressing description field can be combined into a one- or two-stage PL.
By inputting it to A, the optimum microprogram entry address is decoded and generated by the PLA.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The instruction decoding unit 101 includes a microprocessor coded to decode the operation description field 202 of an instruction and output a microprogram entry address corresponding to the operation described above for the conventional microprogram control microprocessor. Program entry address generation PLAII
0 is added, and the instruction execution control unit 301 sends the microprogram entry vector as N bits) MSB
The microprogram entry address shifter 306 for shifting to the side has been deleted. Along with this, microprogram entry address 40
1 is supplied from the instruction decoding unit 101 to the instruction execution control unit 301, and the microprogram entry vector
Latch 102 has been replaced by microprogram entry address latch 111.

The microprogram entry address generation P
The output of the LAI 10 can be latched in the microprogram entry address latch 111 at the same timing as shown in the conventional example, and in this case, the microprogram entry address corresponding to each instruction is Since program entry address generation PLAIIO can be freely set, empty areas between each microprogram can be deleted.

In a microprogram control type microprocessor having the same instructions as the prior art example described above, the microprogram of the register-to-register addition instruction and the test-and-set instruction is successively executed at addresses 8 (II+) and A. FIG. 3 shows the mapping to the (H) address, and FIG. 2 shows an example of the button of the microprogram entry address generation PLA 110 in that case. In addition,
Here, the opcode of each of the above instructions is “000000”.
0 (2).

Let it be “0100001 m”.

FIG. 4 is a block diagram of an instruction decoding section of a microprocessor using a microprogram control system according to a second embodiment of the present invention, and an instruction execution control section 301 is the same as that of the first embodiment.

In addition to the microprocessor instructions shown in the first embodiment, there may also be instructions that require separate preparation of microprograms depending on the addressing mode, even if they are normally the same instruction.

Here, as an example of the above-mentioned instruction, regarding the instruction "PUSH" for pushing data onto the stack, in particular, the addressing mode is register, immediate data, or memory.
Explain when it is an operand.

In this embodiment, when generating a microprogram entry address, the addressing mode is also a factor in determining the microprogram entry address, so the microprogram entry address described in the first embodiment is
In addition to the operation description field 202, the addressing mode description field 204 is input to the address generation PLAIIO.

Figure 19 (a) shows the "PUSH register", Figure 19 (b) shows the "PUSH immediate value data", and Figure 19 (C) shows the "PUSH register".
Figure 6 shows an example of a microprogram with a "PUSH memory operand", and Figure 6 shows a situation where the above instructions are mapped to consecutive microprogram addresses in accordance with the spirit of the present invention. The 5th example of the slam of birth / birth PLAIIO
As shown in the figure.

Here, the instruction code of PTJSH is “0010000 (
2), the addressing mode description field is 2 bits, code “00 (2)” specifies register operand, code “01 < 2.” specifies immediate data, and other hoods specify memory operand. That's it.

FIG. 7 is a block diagram of an instruction decoding section of a microprocessor using a microprogram control system according to a third embodiment of the present invention, and an instruction execution control section 301 is the same as that of the first embodiment.

In the case of the second embodiment described above, the addressing mode is
It can be classified into three types: registers, immediate data, and memory operands. Further, the number of addressing modes that specify memory operands may be more than the two shown in the second embodiment, and the number of bits in the addressing mode description field is three or more. If the number of inputs to the PLA increases, this will also increase the amount of circuitry, so in the third embodiment, the addressing modes are classified into the three types and encoded, thereby making it possible to handle addressing modes including three or more types of memory operands. This allows the number of bits to be specified to be 2 bits.

In FIG. 7, the operation description field predecoder 112 pre-decodes what kind of instruction is in the operation description field 202, and extracts elements unrelated to the microprogram description, such as data size, from the operation description field 202. This is used to reduce the number of input signals of the microprogram entry address generation PLAIIO (hereinafter, the input signals are referred to as operation type information 211), and decoding using the addressing mode description field 204 in the figure as an input. The control unit 104 classifies the addressing modes into three types: register, immediate data, and memory, and encodes them into 2-bit information (the signal obtained as a result of the encoding is referred to as addressing type information 210).

Microprogram entry address generation PLA
IIO contains operation type information 211 and dressing type information 2 encoded as described above.
By using 10 as decode input, addressing/
The microprogram entry address 401 can be generated without increasing the circuit scale as the number of modes increases.

〔Effect of the invention〕

As explained above, the present invention uses the output of a PLA that receives a necessary part of an instruction code as an input as a microprogram entry address, and optimizes the microprogram entry address so that there is less free space in the microprogram ROM. turned into
By coding the PLA, redundant steps can be reduced in the microprogram ROM,
This is effective in reducing the chip size of microprocessors.

In addition, by using PLA to generate microprogram entry addresses, the number of microprogram steps for one instruction as described in the conventional example can be changed to the maximum number of microprogram steps set at the beginning of the design by changing the microprogram coding. Even if the number exceeds the minimum power of 2 N that includes , there is flexibility to easily deal with it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is an example of the button of the microprogram entry address generation PLA in FIG. 1, and FIG. 3 is a block diagram of the first embodiment of the present invention. Microprogram mapping diagram, Figure 4 is the second
FIG. 5 is a block diagram of the instruction decoding section of the embodiment of FIG.
and a button diagram of the third embodiment and microprogram entry address generation PLA, FIG. 6 is a microprogram mapping diagram of the second and third embodiments,
FIG. 7 is a block diagram of the instruction decoding section of the third embodiment;
FIG. 8 is a block diagram of the prior art, FIG. 9 is a bit map showing instruction code specifications used throughout the specification of this application, and FIG. 10 is a block diagram of an instruction decoding section and an instruction execution control section of the prior art. , FIG. 11 is the microprogram mapping diagram, and FIG. 12 is the conventional example and the first example of the present invention.
and an operation timing diagram of the second embodiment, FIG. 13 is a state transition diagram of the instruction execution control unit of the conventional example and the first to third embodiments of the present invention, and FIGS. 14 and 15 respectively,
a circuit diagram of a decode sequence control unit in the instruction decode unit and an instruction execution sequence control unit in the instruction execution control unit;
FIG. 16 is a diagram showing the microprogram mapping situation when N=3 in the conventional example, and FIG. 17 is a diagram used for explanation in the conventional example and the first to third embodiments of the present invention. Block diagrams of the arithmetic unit of the microprocessor during instruction execution, Fig. 18(a), (b) and Fig. 19(a)
, (b) and (c) are microprogram diagrams each corresponding to the instructions used to explain the present invention. 101...Instruction decoding section, 102...Microprogram entry vector latch, 10
3... Immediate data register, 104...
... Decode control section, 105 ... Decode sequence control section, 110 ... Microprogram entry address generation PLA, 111 ...
... Microprogram entry address latch, 112 ... Operation description field predecoder, 202 ... Operation description field, 203 ...; Immediate data or address displacement, 204 ...Addressing mode description field, 205...Microprogram entry vector, 206...Instruction ready signal, 207...Decoding completion signal, 20
8...Decoding control section information, 209...
Immediate value data, 301...Instruction execution control unit, 30
2...Instruction execution sequence control unit, 303...
...Micro program ROM, 304...
・Microprogram address latch, 305...
...Microprogram address multiplexer, 306...Microprogram entry address shifter, 307...Microprogram address incrementer, 308...
...Microprogram ROM data latch, 401
...Microprogram entry address, 402...N-bit zeψ, 403...
...Next microprogram address, 40
4...Microprogram address, 405
...Increment microprogram address, 406...Microprogram entry address selection signal, 407...Increment microprogram address selection signal, 4
08...Microprogram address latch strobe (1,409...Microprogram ROM data latch strobe signal, 410
・・・・・・Microprogram step end signal,
411...Micro meeting condition, 412.
...Micro meeting target signal, 414...
...Micro control information, 415...Micro program ROM data mask control signal. Agent Patent Attorney Hara Uchi Volume 2 Figure 1 Early 6 Figure Figure Figure 75 Turning 16 Figure Memory/Skills Vu; BU code 4 number diagram (α) IJSH Shishi star command order <b> LJSii w'V luck data PIJS? 1 Memory Oyara ↓ Do Iop = 747p Tsuryo Gunri

Claims (1)

[Claims] 1. A programmable logic device coded to take an operation description field in an instruction code as input and output a microprogram entry address corresponding to the operation description field.
A microprocessor with a built-in array (hereinafter referred to as PLA). 2. In the microprocessor according to claim 1, an addressing mode description field is input in addition to an operation description field in an instruction code, and a microprogram entry address corresponding to the instruction is output. PLA coded as
A microprocessor with a built-in. 3. In the microprocessor according to claim 2, the operation description field and the addressing mode description field in the instruction code are input to a decoder for independently grouping each, and the output of the decoder is used as the input. A microprocessor incorporating a PLA coded to output a microprogram entry address corresponding to the instruction.