JPH04153728A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To speed up the processing by performing continuous arithmetic processing and transfer processing for the same register while making the storage step and takeout step of the register overlap with each other when the arithmetic processing and transfer processing are performed for the same register. CONSTITUTION:A register coincidence decision device 8 decides whether an optional register selected among register 3 - 6 for the storage of an arithmetic result and an optional register selected among the registers 3 - 6 as the input of a computing element 9 for current execution are the same or not and makes a coincidence signal 105 active when so. Consequently, the output of a data latch 22 wherein the output of the computing element 9 is stored is inputted to a data latch 21. Consequently, the processing seems to be performed by referring to the value in a register A, which seems to be updated with an instruction, with an instruction 2. Consequently, the arithmetic processing is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic circuit that performs arithmetic processing in a pipeline manner in an information processing device.

[Conventional technology]

In general, processing using pipeline control breaks down instruction execution into multiple steps, each processing block operates independently, and receives new processing requests one after another from the preceding processing step. This is done by executing the process and sending it to the next step.

As a result, when focusing on a certain timing, all processing blocks are operating independently and at the same time, making it possible to perform high-speed processing because they operate as if they were executing one instruction per step. .

FIG. 4 shows a block diagram between registers and arithmetic units under conventional pipeline control. This example is Regis-pA,B
, C and register X, and stores the result in register A, B, or C again. It is assumed that each register is given an initial value in advance, and the calculation processing using that value will be described here.

The timing of the circuit shown in FIG. 4 is shown in FIG. 5. As will be seen from now on, in this example, execution of one instruction is broken down into three steps, and within each step, φ1. It is assumed that two processes are performed at the timing of φ2.

In Figure 4, 1 is a micro program sequencer, 2
is an instruction decoder, 3 to 6 are registers, 7 is an arithmetic unit, 10
11 are data selectors, and 20 to 22 are data latches. 100 to 101 are data select signals, 1
10 to 114 are data buses.

With these components, the register outputs the data stored in the φ2 period from the next φ1 to φ2 period. The data latch stores data during the period of the input clock, and the stored contents are output as they are.

The processing contents of each step will be explained below with reference to FIG.

(1) Step 1 φ1: Micro program instruction 8 Input period An instruction is output from the micro program sequencer 1 which controls the micro program.

φ2: Micro program instruction decoding period The instructions from the micro program sequencer 1 are decoded by the instruction decoder. This step determines the register input to the arithmetic unit and the register that stores the arithmetic unit output, and sends data select signals 101 and 10 to the data selectors 11 and 10.
Outputs 0. The data select signal 101 is output at the timing of step 2, and the data select signal 100 is output at the timing of step 3.

(2) Step 2 φ1: Register output period Output values from each register.

φ2: The value output from the register during the arithmetic unit input period φ1 is selected by the data selector 11 according to the data select signal 101, and the data latch 20.
By latching at 21, the value is input to the arithmetic unit 7.

(3) Step 3 φ1: Operation result output period The operation result is latched by the data latch 22 and the operation result is held.

φ2: Register input period - Data from the data latch 22 is input to the register selected by the data selector 10 according to the data select signal 100.

These three steps each operate independently, and each step executes the processing prescribed for that step and sends data to the next step, that is, as shown in FIG. As the instruction 2... is executed, each step is processed in a vibe-like manner.

[Problem to be solved by the invention]

In the above-described method, since pipeline control is performed when consecutive processing is performed on the same register, there are cases where processing cannot be performed efficiently.

For example, if the processing 'A = B +
If A+X' is executed, the A register is referenced by the instruction 2 before the operation result of the instruction 1 is stored in the register A, so the operation is performed in the A register before being updated.

In other words, in FIG. 6, the operation result of instruction 1 is stored in register A at timing F of execution of instruction 1, and its value can be referenced at the next timing φ1. Regardless, since the value is retrieved from register A during the execution of instruction 2 at timing C of the execution of instruction 2, the operation result of instruction 1 cannot be referenced. Therefore, instruction 2 does not perform any processing (N OP), the correct value cannot be obtained unless 'C=A+X' is executed in instruction 3.

Normally, during this NOP period, an attempt is made to improve performance by inserting another process, but the current situation is that there are many cases where it is unavoidable to insert a NOP due to the flow of processing. If such processing continues, the processing efficiency will be extremely poor.

[Means to solve the problem]

The arithmetic circuit according to the present invention includes a group of registers for storing arbitrary numerical values and an arithmetic unit connected thereto, the input/output of the registers and the input pressure of the arithmetic unit are controlled in a pipeline manner, and further, An arbitrary register in the register group selected to store the calculated operation result is the same as an arbitrary register in the register group selected as an input of the arithmetic unit for the current execution. a register match determiner that determines that the register is a register of
It is characterized by comprising a data selector that selects which of the arithmetic unit output and the register output is to be used as the arithmetic unit input based on the determination result of the determination unit.

In this way, arithmetic processing is sped up when the register that stores the arithmetic result and the register that will perform the next arithmetic operation are the same.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing the components in one embodiment of the present invention. Most of the components are the same as those shown in FIG. 4 for the prior art, but the difference is the register match determiner 8. A data selector 12 has been added, a match signal 105 has been added accordingly, and a data bus 114 has been connected to be an input to the data latch 21 via the data selector 12.

FIG. 2 is a diagram showing timing in an embodiment of the present invention.

Here, the first embodiment will be described with reference to the above-mentioned drawings.

First, the operations of the added components will be explained.

Register match determiner 8 receives data select signal 100
and 101, it is determined whether the registers selected by both parties are the same, and if they are the same, the match signal 105 is activated.

Data selector 12 selects data bus 114 when match signal 15 is active, and selects the signal from data selector 11 and inputs it to data latch 21 when match signal 15 is negative. do.

Processing by these added components will be explained with reference to FIG.

Let us consider again the case where the processes "A=B+X" and "C=A+X" are consecutive. In other words, in instruction 1, "A=B+X'
, it is assumed that "C=A+X" is executed in instruction 2.

If we pay attention to step 3 of instruction 1, at the same time instruction 2
Step 2 will be executed. At this time, the instruction decoder 2 sends the instruction l to the data select signal 100.
A signal for selecting register A to store the operation result of instruction 2 and a signal for selecting register A as an input for the operation of instruction 2 are outputted to the data select signal 101.

Therefore, the match signal 105 from the register match determiner 8
is activated and output, so the output of the data latch 22 in which the pressure of the calculator 8 is stored is input to the data latch 21.

In other words, the operation result of the instruction 1 is directly input to the arithmetic unit 8 instead of the register output.

As a result, processing can be performed as if the value of register A updated by instruction 1 was referenced by instruction 2.

Next, a second embodiment of the present invention will be described using the drawings.

FIG. 3 is a block diagram showing the components of the second embodiment. In the second embodiment, not only arithmetic processing but also transfer instruction processing between registers is realized.

In the figure, what has changed from the first embodiment is the instruction code;
7-The data select signal 102 is pressed from the data selector 2. Data selector 13 and data selector 13
0° theta was added as an input to .

Here, the operation of the second embodiment of the present invention will be explained based on FIG.

The data select signal 102 newly output from the instruction decoder 2 is a signal for determining whether the instruction interpreted by the instruction decoder 2 is an operation instruction or a transfer instruction. The data selector 13 selects the register 6 when the data select signal 102 is an arithmetic command, selects "0" data when the data select signal 102 is a transfer command, and inputs the result to the data latch 20.

In other words, at the time of a transfer command, the data latch 20 has 1()T.
is input, even if the arithmetic processing is performed by the arithmetic unit 7, the data of the data latch 21 is output as is and is stored in the data latch 22. In other words, transfer between registers can be performed in exactly the same way as arithmetic processing.

Therefore, if an arithmetic instruction is executed after a transfer instruction and the transfer destination register and the input register of the arithmetic unit match, or if a transfer instruction is executed after an arithmetic instruction,
Continuous processing is possible when the storage register of the operation result and the transfer source register match.

〔Effect of the invention〕

According to the present invention, when performing continuous arithmetic processing or transfer processing on the same register, the storage step and the access step to the register can be executed in an overlapping manner, thereby speeding up the processing.

Furthermore, since the programmer does not need to insert a NOP instruction or the like in consideration of the storage time in the register, programming is easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the components in the first embodiment of the invention, FIG. 2 is a diagram showing the timing in this embodiment, and FIG. 3 is a block diagram showing the components in the second embodiment of the invention. 4 is a block diagram showing the constituent elements in the conventional example, and FIG. 5 is a diagram showing the timing in the conventional example. 1...Micro program sequencer, 2
...Instruction decoder, 3-6...Register, 7...Arithmetic unit, 8--Register match determiner, 10-13...・Data selector,
20~22...Data latch, 100~10
2...Data select signal, 105...
... Match signal, 110-114 ... Data bus. Agent Patent Attorney Susumu Uchihara φlφ2 pI f2 f/ 41J2φ1 house 2 houses l Passφ/-2 Chisen Chita Diagram φ/ 2 pIφ2ψIφ2plφ2 pI pI
11'/p,? The 1st

Claims (1)

[Claims] In an arithmetic circuit that includes a group of registers that store arbitrary numerical values and an arithmetic unit connected thereto, and in which the input/output of the registers and the input/output of the arithmetic unit are controlled in a pipeline manner, the result of the most recently executed operation is Any register in the register group selected for storage and any register in the register group selected as an input of the arithmetic unit for current execution are the same register. and a data selector that selects which of the arithmetic unit output and the register output is to be used as the arithmetic unit input based on the judgment result of the judgment means. calculation circuit.