JPH05299552A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH05299552A JPH05299552A JP9994992A JP9994992A JPH05299552A JP H05299552 A JPH05299552 A JP H05299552A JP 9994992 A JP9994992 A JP 9994992A JP 9994992 A JP9994992 A JP 9994992A JP H05299552 A JPH05299552 A JP H05299552A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- insulating film
- coining
- chip
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＣＯＬ（Ｃｈｉｐ ｏｎ
Ｌｅａｄ）またはＬＯＣ（Ｌｅａｄ ｏｎＣｈｉｐ）
の半導体装置用リードフレーム、特にプレス加工リード
フレームに関する。The present invention relates to a COL (Chip on)
Lead) or LOC (Lead on Chip)
The present invention relates to a lead frame for a semiconductor device, in particular, a press-worked lead frame.
【０００２】[0002]
【従来の技術】図１は、ＣＯＬ構造リードフレームの一
例である。ＣＯＬ構造の場合、支持リード１（チップ固
定部）の上に絶縁フィルム２を接着剤４で接着し、その
上にチップが搭載される。従って、絶縁フィルム２のフ
ィルム面の平坦性（図１の場合、２枚のフィルムのねじ
れを含めた平坦性）が非常に重要である。2. Description of the Related Art FIG. 1 is an example of a COL structure lead frame. In the case of the COL structure, the insulating film 2 is adhered onto the support lead 1 (chip fixing portion) with the adhesive 4, and the chip is mounted thereon. Therefore, the flatness of the film surface of the insulating film 2 (in the case of FIG. 1, the flatness including the twist of the two films) is very important.
【０００３】エッチング加工リードフレームの場合は、
リードフレーム表面の平坦性は優れており、通常は問題
を生じない。In the case of an etching processed lead frame,
The flatness of the leadframe surface is excellent and usually causes no problems.
【０００４】プレス加工リードフレームの場合は、打抜
き側にダレ、反対側にバリが生じる。また、板厚と同じ
寸法幅程度の加工を行なうとバリ側面が三角状となり、
平坦性は非常に悪くなる。In the case of a pressed lead frame, sagging occurs on the punching side and burrs occur on the opposite side. In addition, if the width and width of the burr are the same, the side of the burr becomes triangular.
Flatness is very poor.
【０００５】従来よりプレス加工リードフレームの場合
は、ワイヤボンド可能な平坦部を確保するため、ワイヤ
ボンディング用インナーリード３先端部をコイニング
（他の部分より板厚が薄くなるまで平坦につぶす）する
方法が取られている。しかしながらリードフレームの絶
縁フィルム接着部分には特に平坦加工が行われた従来例
はない。Conventionally, in the case of a press-worked lead frame, in order to secure a flat portion capable of wire bonding, the tip end portions of the wire-bonding inner leads 3 are coined (crushed flat until the plate thickness becomes thinner than other portions). The method is taken. However, there is no conventional example in which the insulating film adhesion portion of the lead frame is particularly flattened.
【０００６】図５はＬＯＣ構造リードフレームの一例で
ある。ＬＯＣ構造の場合、通常曲げ加工を行ったリード
３の下側に絶縁フィルム２を接着剤４で接着し、絶縁フ
ィルム２の下側にチップ（図示せず）が固着されて搭載
される構造となっている。この場合においても、絶縁フ
ィルム２のフィルム面の平坦性が重要であり、ワイヤボ
ンディングを行うリード３の平坦性も重要である。FIG. 5 shows an example of a LOC structure lead frame. In the case of the LOC structure, the insulating film 2 is bonded to the lower side of the lead 3 which is normally bent by the adhesive 4, and a chip (not shown) is fixedly mounted on the lower side of the insulating film 2 to be mounted. Is becoming Also in this case, the flatness of the film surface of the insulating film 2 is important, and the flatness of the leads 3 for wire bonding is also important.
【０００７】[0007]
【発明が解決しようとする課題】前述したＣＯＬまたは
ＬＯＣ構造のリードフレームをプレス加工で製造する場
合には、支持リード１の絶縁フィルム２接着面の平坦性
がエッチング加工に比較し極めて劣っている。When the lead frame having the COL or LOC structure described above is manufactured by press working, the flatness of the insulating film 2 bonding surface of the supporting lead 1 is extremely inferior to that by etching. ..
【０００８】そのため図７に示す断面図のように前記フ
ィルム接着面に傾きや未接着部が生じ、接着平面積も減
少する。Therefore, as shown in the sectional view of FIG. 7, an inclination or an unbonded portion occurs on the film bonding surface, and the bonding flat area also decreases.
【０００９】さらに、支持リード１と絶縁フィルム２と
の間にボイド６（気泡）が発生しやすい。ボイド６が発
生したままのＩＣパッケージ完成品は耐湿性、耐クラッ
ク性ともに品質低下を生じる。従って、リードフレーム
の絶縁フィルム２接着面の平坦性は非常に重要となる。Further, voids 6 (air bubbles) are easily generated between the support lead 1 and the insulating film 2. The finished product of the IC package in which the void 6 is still generated has a deterioration in both moisture resistance and crack resistance. Therefore, the flatness of the bonding surface of the insulating film 2 of the lead frame is very important.
【００１０】本発明の目的は、前記した従来技術の欠点
を解消し、チップ搭載部のフィルム平坦性を向上させた
ＣＯＬまたはＬＯＣ構造のプレス加工リードフレームを
提供することにある。An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a press-worked lead frame having a COL or LOC structure in which the film flatness of the chip mounting portion is improved.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、チップを固定するための絶縁フィル
ムを接着したプレス加工によるリードフレームにおい
て、少なくとも前記リードフレームの絶縁フィルム接着
部分よりも広い範囲にわたる平坦なコイニング部を前記
接着部分を含む部分に有することを特徴とする半導体装
置用リードフレームが提供される。ここで平坦なコイニ
ング部は、コイニング加工で得られてもよいしデプレス
加工等の他の方法で得られたものでもよい。In order to achieve the above object, according to the present invention, in a lead frame by press working to which an insulating film for fixing a chip is adhered, at least an insulating film adhering portion of the lead frame is Also provided is a lead frame for a semiconductor device, which has a flat coining portion over a wide range in a portion including the adhesive portion. Here, the flat coining portion may be obtained by coining or by another method such as depressing.
【００１２】ここで前記コイニング部の範囲は、前記絶
縁フィルムの幅方向の少なくとも片側に０．０５ｍｍ広
く有するのが好ましい。Here, the range of the coining portion is preferably wider by 0.05 mm on at least one side in the width direction of the insulating film.
【００１３】以下に本発明をさらに詳細に説明する。本
発明において、リードフレーム、絶縁フィルムおよび接
着剤の材質等は限定しないが、例えばリードフレームは
Ｆｅ−４２％Ｎｉ合金、絶縁フィルムはポリイミドフィ
ルム、接着剤はポリエーテルアミドイミド系接着剤など
を挙げることができる。The present invention will be described in more detail below. In the present invention, the materials of the lead frame, the insulating film and the adhesive are not limited, but for example, the lead frame is a Fe-42% Ni alloy, the insulating film is a polyimide film, and the adhesive is a polyether amide imide adhesive. be able to.
【００１４】本発明において、絶縁フィルム２の貼り付
け部、すなわち図２、３に示すコイニング平坦部５のコ
イニング深さは限定しないが１μm 以上とするのがプレ
スバリの影響を取り除く上で好ましい。その上限はリー
ドフレーム板厚の１／３程度までとするのが材料の横方
向への伸びに対し形状を損なわないレベルであるという
意味で適切である。In the present invention, the coining depth of the pasting portion of the insulating film 2, that is, the coining flat portion 5 shown in FIGS. 2 and 3 is not limited but is preferably 1 μm or more in order to eliminate the influence of press burrs. It is appropriate that the upper limit is about 1/3 of the thickness of the lead frame plate in the sense that the shape is not impaired when the material is stretched in the lateral direction.
【００１５】本発明において、コイニングの範囲は、貼
り付ける絶縁フィルム２の幅方向の少なくとも片側に
０．０５ｍｍ広く有するのが好ましい。これよりも狭い
とフィルムの貼り付けの精度上、段差部にフィルムが掛
かるおそれが生じる。ＬＯＣの場合は、インナーリード
３の先端から曲げ加工部近傍までをコイニングすればよ
い。In the present invention, the coining range is preferably wider by 0.05 mm on at least one side in the width direction of the insulating film 2 to be attached. If the width is narrower than this, there is a possibility that the film may be caught on the stepped portion due to the accuracy of sticking the film. In the case of LOC, it is sufficient to coin from the tip of the inner lead 3 to the vicinity of the bent portion.
【００１６】図６はＬＯＣ構造の一実施例を示す断面図
である。絶縁フィルム２を接着するインナーリード２の
部分は、ボンディング部でありコイニングを施してい
る。この場合、ワイヤボンディングの平坦性確保であれ
ばもっと狭い範囲でコイニングしておけば十分である
が、絶縁フィルム２接合のためのコイニングの場合、少
なくとも絶縁フィルム２との接着面は全てコイニングさ
れる必要がある。図６はインナーリード３の曲げ加工部
も含めてコイニングし、コイニング後曲げ加工した例で
ある。符号７はＳｉチップを示す。FIG. 6 is a sectional view showing an embodiment of the LOC structure. The portion of the inner lead 2 to which the insulating film 2 is bonded is a bonding portion and is coined. In this case, in order to secure the flatness of the wire bonding, it is sufficient to coin in a narrower range, but in the case of coining for joining the insulating film 2, at least the entire bonding surface with the insulating film 2 is coined. There is a need. FIG. 6 shows an example in which the inner lead 3 including the bent portion is coined and then bent after coining. Reference numeral 7 indicates a Si chip.
【００１７】前記コイニングは、例えば公知の順送プレ
ス金型を用いたコイニング加工、デプレス加工等の方法
によって表面を平坦に加工することによって形成するこ
とができる。The coining can be formed by flattening the surface by a method such as coining or depressing using a known progressive press die.
【００１８】[0018]
【実施例】以下に本発明を実施例に基づき具体的に説明
する。EXAMPLES The present invention will be specifically described below based on examples.
【００１９】（実施例１）図２〜３に示すようにＣＯＬ
構造のリードフレーム（材質４２アロイ、厚さ０．２０
ｍｍ）をプレスにて作製した。チップ固定部１には、絶
縁フィルム２を接着するため、予め前記プレス加工時に
てコイニングを行なうことによりフィルムの平坦性を向
上させた。(Embodiment 1) As shown in FIGS.
Structural lead frame (material 42 alloy, thickness 0.20
mm) was prepared by pressing. Since the insulating film 2 is adhered to the chip fixing portion 1, the flatness of the film is improved by performing coining in advance during the press working.
【００２０】コイニング平坦部５は、コイニング深さ
ｂ：３μm 、１０μm 、３０μm とし、コイニング範囲
ａ：０．１ｍｍとした（本発明例１〜３）。比較のため
にコイニング範囲ａ：無しのものを加えた（比較例
１）。The coining flat portion 5 has a coining depth b: 3 μm, 10 μm, 30 μm, and a coining range a: 0.1 mm (invention examples 1 to 3). For comparison, one without coining range a was added (Comparative Example 1).
【００２１】本発明例１〜３および比較例１のコイニン
グ平坦部５に絶縁フィルム２（材質ポリイミド）を接着
剤４（ポリエーテルアミドイミド系接着剤）で接着し、
Ｓｉチップ（実装評価用チップ）を搭載したのち、いず
れも接着状態を断面研磨にて確認した。本発明例はいず
れも絶縁フィルム貼り付け位置精度が向上した。これら
のチップ固定部１と絶縁フィルム２との接着状態は図４
に示すようにボイド６や未接着部が生じなかったが、比
較例１のものは図７に示すようにボイド６および未接着
部が発生した。An insulating film 2 (polyimide material) was adhered to the coining flat portions 5 of Examples 1 to 3 of the present invention and Comparative Example 1 with an adhesive 4 (polyetheramide imide adhesive),
After mounting a Si chip (chip for mounting evaluation), the bonding state was confirmed by cross-section polishing. In each of the examples of the present invention, the accuracy of the insulating film attachment position was improved. The bonding state between the chip fixing portion 1 and the insulating film 2 is shown in FIG.
The void 6 and the non-bonded portion were not generated as shown in FIG. 7, but the void 6 and the non-bonded portion were generated in Comparative Example 1 as shown in FIG. 7.
【００２２】[0022]
【発明の効果】本発明は以上説明したように構成されて
いるので、チップ搭載部のフィルム平坦性が良く、ＣＯ
Ｌ構造やＬＯＣ構造のようにリードとチップの位置関係
についての厳しい要求に応えることができる。Since the present invention is constructed as described above, the film flatness of the chip mounting portion is good and CO
As with the L structure and the LOC structure, it is possible to meet strict requirements regarding the positional relationship between the lead and the chip.
【図１】 ＣＯＬ構造ＩＣリードフレームの一例を示す
平面図である。FIG. 1 is a plan view showing an example of a COL structure IC lead frame.
【図２】 本発明のＣＯＬ構造ＩＣリードフレームのフ
ィルム貼り付け部の一実施例を示す平面図である。FIG. 2 is a plan view showing an example of a film sticking portion of a COL structure IC lead frame of the present invention.
【図３】 図２の側面図である。FIG. 3 is a side view of FIG.
【図４】 本発明のリードフレームの支持リードと絶縁
フィルムとの接着状態を示す断面図である。FIG. 4 is a cross-sectional view showing a bonding state between a support lead of a lead frame of the present invention and an insulating film.
【図５】 ＬＯＣ構造ＩＣリードフレームの一例を示す
平面図である。FIG. 5 is a plan view showing an example of a LOC structure IC lead frame.
【図６】 本発明のＬＯＣ構造ＩＣリードフレームの一
実施例を示す断面図である。FIG. 6 is a sectional view showing an example of an LOC structure IC lead frame of the present invention.
【図７】 従来のリードフレームの支持リードと絶縁フ
ィルムとの接着状態を示す断面図である。FIG. 7 is a cross-sectional view showing an adhesion state between a support lead of a conventional lead frame and an insulating film.
１ 支持リード（チップ固定部） ２ 絶縁フィ
ルム ３ ワイヤボンディング用インナーリード ４ 接着剤 ５ コイニン
グ平坦部 ６ ボイド（気泡） ７ Ｓｉチッ
プ1 Support Lead (Chip Fixing Part) 2 Insulating Film 3 Inner Lead for Wire Bonding 4 Adhesive 5 Coining Flat Part 6 Void (Air Bubble) 7 Si Chip
Claims (2)
着したプレス加工によるリードフレームにおいて、 少なくとも前記リードフレームの絶縁フィルム接着部分
よりも広い範囲にわたる平坦なコイニング部を前記接着
部分を含む部分に有することを特徴とする半導体装置用
リードフレーム。1. A lead frame by pressing, to which an insulating film for fixing a chip is adhered, which has a flat coining portion covering at least a wider area than an insulating film adhering portion of the lead frame in a portion including the adhering portion. A lead frame for a semiconductor device, which is characterized in that
ルムの幅方向の少なくとも片側に０．０５ｍｍ広く有す
る請求項１に記載の半導体装置用リードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein the range of the coining portion is wider by 0.05 mm on at least one side in the width direction of the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4099949A JP2646934B2 (en) | 1992-04-20 | 1992-04-20 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4099949A JP2646934B2 (en) | 1992-04-20 | 1992-04-20 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05299552A true JPH05299552A (en) | 1993-11-12 |
| JP2646934B2 JP2646934B2 (en) | 1997-08-27 |
Family
ID=14260959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4099949A Expired - Lifetime JP2646934B2 (en) | 1992-04-20 | 1992-04-20 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2646934B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63306648A (en) * | 1987-06-08 | 1988-12-14 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device and manufacture thereof |
-
1992
- 1992-04-20 JP JP4099949A patent/JP2646934B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63306648A (en) * | 1987-06-08 | 1988-12-14 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2646934B2 (en) | 1997-08-27 |
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