JPH05298882A - Refreshment control system for dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the capacitance of an auxiliary power unit by restricting the peak current consumption of dynamic RAM refreshment. CONSTITUTION:When a refreshment requesting signal is inputted in a refreshment signal generating means 1a at the time of backing-up, the refreshment signal generating means 1a generates plural refreshment signals within a refreshing cycle. The plural refreshment signals are distributed to the respective memory blocks of dynamic RAM in a refreshment signal distributing means 1b and the respective memory blocks of dynamic RAM are divided and refreshed. At the normal time, the refreshment signal generating means 1a generates one refreshment signal within the refreshing cycle and the respective memory blocks of dynamic RAM are refreshed in a batch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control system for a dynamic RAM (hereinafter referred to as DRAM),
In particular, the present invention relates to a dynamic RAM refresh control method for suppressing the peak current consumption of the DRAM.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a conventional refresh control system. FIG. 11A shows a circuit configuration and FIG. 11B shows a time chart thereof. In FIG.
1 is a refresh control circuit, 101a is a timing control circuit, 101b to 101e are NOR gates, and 102a to 1
02d is a memory block of DRAM, RRAS is a refresh signal, * RAS0 to * RAS3 are refresh signals to each memory block, and TRAS0 to TRAS3.
Indicates an access timing signal to the memory block.

Further, in FIG. 1B, REF request signal "REF request" which is an input signal of the timing control circuit, refresh signal "RRAS" which is an output of the timing control circuit, and ~ are the memory blocks 10 respectively.
Refresh signal * RAS input to 2a to 102d
0 to * RAS3 (note that "*" indicates a negative signal, and the memory block is refreshed when * RAS0 to * RAS3 are at a low level).

In FIG. 11, when a REF request signal "REF request" is applied to the timing control circuit 101a from a timer (not shown), the timing control circuit 101a outputs a refresh signal RRAS. Refresh signal RR
AS is given to the NOR gates 101b to 101e, and the NOR gates 101b to 101e send the refresh signals * RAS0 to * R to the memory blocks 102a to 102d at the same timing as shown in FIG.
Output AS3.

The memory blocks 102a to 102d receive the refresh signals * RAS0 to * RAS3,
At the same time, the refresh operation is performed.

[0006]

In the conventional refresh control method described above, the memory blocks 102a to 102d are collectively refreshed in response to the refresh request signal, so that the peak current consumption at the time of refresh becomes large. .. Therefore, a large-capacity backup power supply for the DRAM is required.

The present invention has been made to remedy the above-mentioned drawbacks of the prior art.
An object of the present invention is to provide a DRAM refresh control system capable of reducing the capacity of a standby power supply by suppressing the peak current consumption of DRAM refresh during backup of M.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. In order to solve the above-mentioned problems, the invention of claim 1 of the present invention provides a dynamic RAM refresh control system comprising a dynamic RAM 2 comprising a plurality of memory blocks and a refresh means 1 for refreshing the dynamic RAM 2 at a predetermined refresh cycle. The refresh means 1 includes a refresh signal output means 1a for generating a plurality of refresh signals or one refresh signal within a refresh cycle according to the presence or absence of a backup signal when a refresh request signal is input, and a plurality of refresh signals. The refresh signal distributing means 1b distributes and outputs to each memory block of the dynamic RAM 2.

Then, the dynamic RA by the standby power source
At the time of backing up M2, the refresh signal output means 1a generates a plurality of refresh signals within the refresh cycle, and the refresh signal distribution means 1b outputs the plurality of refresh signals generated by the refresh signal output means 1a to each memory of the dynamic RAM 2. The plurality of memory blocks of the dynamic RAM 2 are divided and refreshed by dividing and outputting to the blocks, and normally, the refresh signal output means 1a generates one refresh signal within the refresh cycle, and the dynamic RAM 2 Dynamic RA by the standby power supply by collectively refreshing a plurality of memory blocks
The peak current consumption at the time of backing up M2 is suppressed.

According to a second aspect of the present invention, in the first aspect of the invention, the refresh signal distribution means 1b includes a binary counter for counting a plurality of refresh signals generated by the refresh signal output means 1a, and a binary counter. It is configured by a decoder for decoding the output of the counter, and a plurality of memory blocks of the dynamic RAM 2 are divided and refreshed by the output of the decoder.

According to a third aspect of the present invention, in the first aspect of the invention, the refresh signal distributing means 1b is a shift register for generating shift pulses according to a plurality of refresh signals generated by the refresh signal outputting means 1a. A plurality of memory blocks of the dynamic RAM 2 are divided and refreshed by the output of the shift register.

[0012]

When the refresh request signal is input to the refresh signal generating means 1a during backup when the backup signal BKUP is input, the refresh signal generating means 1a generates a plurality of refresh signals within the refresh cycle. The plurality of refresh signals are supplied to the refresh signal distribution means 1b, and the refresh signal distribution means 1b distributes the plurality of refresh signals to the respective memory blocks of the dynamic RAM and outputs the refresh signals. The block is divided into refresh cycles and refreshed.

In the normal control, when the refresh request signal is input to the refresh signal generating means 1a, the refresh signal generating means 1a generates one refresh signal within the refresh cycle. This refresh signal is output to each memory block of the dynamic RAM,
The memory blocks of the dynamic RAM are collectively refreshed.

During backup, the dynamic RAM
Each memory block is refreshed by dividing it, and at the time of normal operation, each memory block of the dynamic RAM is refreshed collectively, so that the peak current consumption of the backup power supply at the time of backup can be suppressed. It is possible to suppress an increase in the occupied time of the memory due to the refreshing.

Further, by using a shift register as the refresh signal distribution means 1b as in the third aspect of the invention, even if the number of memory blocks is increased or decreased, it is possible to easily cope with it by changing the number of stages of the shift register. be able to.

[0016]

EXAMPLE An example in which the number of memory blocks is 4 will be described below. FIG. 2 is a diagram showing a first embodiment of the present invention. In FIG. 2, 21 is a refresh control circuit and 21 is a refresh control circuit.
a is a timing control circuit, 21b is a quaternary binary counter, 21c is a divide-by-4 circuit, 21d is a selector, and 21e.
Is a decoder, 21f-0 to 21f-3 are OR gates, 2
1g-0 to 21g-3 is an AND gate, 21h-0 to 2
1h-3 is a NOR gate, and 22a to 22d are DRAM memory blocks.

In the figure, the timing control circuit 21a
Is means for receiving the refresh request signal "REF request" and outputting the refresh signal RRAS, and its output is given to the AND gates 21g-0 to 21g3. The quaternary binary counter 21b receives the refresh request signal "R
It is a means for counting the "EF request" and returns to zero when the four refresh request signals "REF request" are counted, and the refresh input signal "REF request" to be input next is counted again. The quaternary binary counter 21b is initially cleared by the output of the timing control circuit 21a.

The decoder 21e is means for decoding the output of the quaternary binary counter 21b, and its output is given to the OR gates 21f-0 to 21f-3. The divide-by-4 circuit 21c is a means for dividing the pulse signal of 1/4 cycle of the refresh cycle inputted from a timer (not shown) into 1/4, and the output thereof is given to the selector 21d.

The selector 21d has a backup signal * BK
UP (* BKUP represents a negative signal of the backup signal BKUP and becomes a low level when the DRAM is backed up. In the following description, the * BKUP signal is referred to as a backup signal) and an output pulse signal of a timer not shown. It is a means for selecting and outputting any of the output signals of the divide-by-4 circuit 21c, and a backup signal * B
When KUP is at a high level, that is, in normal time, the output of the divide-by-4 circuit 21c is selected, and when the backup signal is at low level, that is, in backup, the output of a timer (not shown) is selected.

The output of the selector 21d is given to the timing control circuit 21a and the quaternary binary counter 21b. The OR gates 21f-0 to 21f-3 are the decoder 2
1e and a backup signal * BKUP are means for outputting a high level signal when one of them is at a high level, and its output is AND gates 21g-0 to 21g-.
Given to 3.

The refresh signal RRAS output from the timing control circuit 21a is input to the other inputs of the AND gates 21g-0 to 21g-3. And gate 21
The outputs of g-0 to 21g-3 become high level when both input signals thereof become high level. AND gate 21g
The output of -0 to 21g-3 is NOR gate 21h-0 to 21
It is input to h-3 and NOR gates 21h-0 to 21h-3.
The other input of the access timing signal TRAS0
~ TRAS3 is input.

When any one of the inputs of the NOR gates 21h-0 to 21h-3 goes high, its output goes low and its output goes to the memory blocks 22a-22.
given to d. FIG. 3 is a time chart showing the operation of the first embodiment shown in FIG. 2. In FIG. 3, is a refresh request signal, is a backup signal, is a refresh signal output from the timing control circuit 21a, and is -1.
~ -4 are outputs of OR gates 21f-0 to 21f-3,
-1 to -4 are refresh signals output from the NOR gates 21h-0 to 21h-3. Also, in the figure,
“T” indicates a refresh cycle.

Next, the first embodiment of FIG. 2 will be described with reference to FIG. At the time of backup, the backup signal * BKUP is at the low level as shown in FIG. 3, and the selector 21d in FIG. 2 selects the output of the timer (not shown). The timer (not shown) is 1 / th of the refresh cycle T.
It outputs a pulse signal of 4 cycles (see Fig. 3),
This signal is given to the timing control circuit 21a via the selector 21d.

The timing control circuit 21a receives this signal and outputs the refresh signal RRAS shown in FIG. On the other hand, the refresh request signal “REF request” is given to the quaternary binary counter 21b and counted,
The quaternary binary counter 21b returns to zero after counting 4 pulses of the refresh request signal "REF request", and counts the next refresh request signal "REF request" again.

The decoder 21e decodes the output of the quaternary binary counter 21e and outputs OR gates 21f-0 to 2-2.
Give to 1f-3. OR gate 21f-0 to 21f-3
The backup signal * BKUP is applied to the other input end of the OR gates 21f-0 to 21f-3, and the decoder 21e is connected to the output ends of the OR gates 21f-0 to 21f-3.
Is output as it is, and the signals shown in -1 to -4 of FIG. 3 are output.

The outputs of the OR gates 21f-0 to 21f-3 are given to the AND gates 21g-0 to 21g-3, and the refresh signal R output from the timing control circuit 21a.
RAS (see FIG. 3) and AND are taken and applied to NOR gates 21h-0 to 21h-3. NOR Gate 21
h-0 to 21h-3 are AND gates 21g-0 to 21g
-3 output is inverted, and as shown in -1 to -4 of FIG.
The memory block 2 outputs the refresh signals * RAS0 to * RAS3 divided into four within the refresh cycle.
Refresh 2a through 22d.

Next, during normal operation, the backup signal * B
KUP is at a high level as shown in FIG.
The selector 21d selects the output of the divide-by-4 circuit 21c. Therefore, the refresh request signal "REF request"
Occurs once within the refresh cycle T, as shown in FIG. The timing control circuit 21a receives the refresh request signal "REF request" and outputs the refresh signal RRAS as shown in FIG.

On the other hand, the OR gates 21f-0 to 21f of FIG.
The output of f-3 is at a high level as shown at -1 to -4 in FIG. 3 because the backup signal * BKUP is at a high level as shown in FIG. Therefore, the AND gates 21g-0 to 21g-3 generate an output when the refresh signal RRAS is at a high level, and this output is given to the NOR gates 21h-0 to 21h-3.

The NOR gates 21h-0 to 21h-3 invert the outputs of the AND gates 21g-0 to 21g-3, and FIG.
1 within the refresh cycle T as shown in -1 to -4
Refresh signal * RAS0 to * RAS that is batched only once
3 to refresh memory blocks 22a through 22d. As described above, according to this embodiment, at the time of backup, the refresh signals * RAS0 to * R are used.
AS3 is divided into four times and output within the refresh cycle T, and the refresh signals * RAS0 to RAS0
* Since RAS3 is collectively output only once within the refresh cycle T, the peak current consumption of the backup power supply during backup can be suppressed, and the memory occupancy time due to refresh during normal times can be reduced. ..

Basically, since there is little or no memory access at the time of backup, there is no problem even if the DRAM is divided and refreshed to increase the occupied time of the memory as in this embodiment. Absent. FIG. 4 is a diagram showing a second embodiment of the present invention. In FIG.
The same components as those in the first embodiment are designated by the same reference numerals. In this embodiment, the selector 21d is removed from the first embodiment, and the quaternary binary counter is used. The difference is that the input signal to 21b is the refresh signal RRAS output by the timing control circuit 21a, and the rest of the configuration is the same as that of the first embodiment.

FIG. 5 is a time chart showing the operation of this embodiment, and the same signals as those in the time chart of FIG. 3 are assigned the same numbers. Next, referring to FIG. 5, the second of FIG.
The operation of this embodiment will be described. In FIG. 4, a timer (not shown) generates a pulse signal having a 1/4 cycle of the refresh cycle T, and this signal is divided by the divide-by-4 circuit 21c. A refresh request signal "REF request" is added.

During backup, the backup signal * BKUP is at a low level as shown in FIG. 5, and when the timing control circuit 21a receives the refresh request signal "REF request", the refresh signal RR shown in FIG.
Output AS. The refresh signal RRAS is given to the quaternary binary counter 21b and counted.

The decoder 21e decodes the output of the quaternary binary counter 21e and outputs OR gates 21f-0 to 2-2.
Give to 1f-3. OR gate 21f-0 to 21f-3
The backup signal * BKUP is applied to the other input end of the OR gates 21f-0 to 21f-3, and the decoder 21e is connected to the output ends of the OR gates 21f-0 to 21f-3.
Is output as it is, and the signals shown in -1 to -4 of FIG. 5 are output.

The outputs of the OR gates 21f-0 to 21f-3 are given to the AND gates 21g-0 to 21g-3, and the refresh signal R output from the timing control circuit 21a.
RAS (see FIG. 5) and AND are taken and applied to NOR gates 21h-0 to 21h-3. NOR Gate 21
h-0 to 21h-3 are AND gates 21g-0 to 21g
The output of -3 is inverted, and as shown in -1 to -4 of FIG.
The memory block 2 outputs the refresh signals * RAS0 to * RAS3 divided into four within the refresh cycle.
Refresh 2a through 22d.

Next, during normal operation, the backup signal * B
KUP is at a high level as shown in FIG. 5, and the timing control circuit 21a causes the refresh request signal "REF".
In response to the "request", a refresh signal RRAS as shown in FIG. 5 is output. On the other hand, the OR gate 21f in FIG.
The output of -0 to 21f-3 is the backup signal * BKU
Since P is at a high level as shown in of FIG.
It is at a high level as shown in -1 to -4.

Therefore, the AND gates 21g-0 to 21
g-3 generates an output when the refresh signal RRAS is at a high level, and this output is NOR gates 21h-0 to 21h.
given to h-3. NOR gate 21h-0 to 21h-
3 inverts the outputs of the AND gates 21g-0 to 21g-3, and as shown by -1 to -4 in FIG. 5, the refresh signals * RAS0 to RAS0 collectively batched only once within the refresh cycle T.
* RAS3 is generated and the memory block 22a to the memory block 22d are refreshed.

As described above, according to the present embodiment, as in the first embodiment, the refresh signals * RAS0 to * RAS3 are divided into four within the refresh cycle T and output during backup, and Normally, the refresh signals * RAS0 to * RAS3 are set to 1 within the refresh cycle T.
Since the data is output collectively only once, it is possible to suppress the peak current consumption of the backup power supply at the time of backup, and it is possible to suppress the increase in the occupied time of the memory due to the refresh at the normal time.

FIG. 6 is a diagram showing a third embodiment of the present invention. In FIG. 6, the same parts as those in the first embodiment of FIG. 2 are designated by the same reference numerals. Is the first
With respect to the embodiment of FIG.
Have been removed, and the quaternary binary counter 21
b and the decoder 21e instead of the shift register 21j,
The difference is that an AND gate 21k and a NAND gate 21m are provided, and the rest of the configuration is the same as that of the first embodiment.

FIG. 7 shows the shift register 21j shown in FIG.
FIG. 3 is a diagram showing the configuration of the shift register 2 of the present embodiment.
1j is composed of four flip-flops whose outputs are sequentially connected to the next-stage flip-flops as shown in FIG. Then, when the input of the data-in DA is at the high level, QA becomes the high level when the clock input is given from the clock terminal CLK, and thereafter, every time the clock is input, the outputs QA to QD are sequentially set to the high level. Output occurs.

FIG. 8 is a time chart showing the operation of this embodiment. The same signals as those in the time chart of FIG. 3 of the first embodiment are designated by the same reference numerals. The output REFE of the NAND gate 21m of FIG. 6 is shown in place of the backup signal * BKUP of FIG. Also, in the time chart of FIG. 8, only the time chart at the time of backup is shown, and the time chart at the time of normal operation is omitted because it is almost the same as the original time chart of FIG.

The operation of the third embodiment shown in FIG. 6 will be described with reference to FIG. In FIG. 6, a timer (not shown) generates a pulse signal having a 1/4 cycle of the refresh cycle T. This refresh request signal "REF request"
(See FIG. 8) is added to the timing control circuit 21a. Upon backup, the timing control circuit 21a outputs the refresh signal RRAS shown in FIG. 8 when receiving the refresh request signal "REF request".

The refresh signal RRAS is applied to the clock terminal of the shift register 21j. On the other hand, at this time, since the output of the shift register 21j is low level, the output REFE of the NAND gate 21m (see FIG. 8).
Is at a high level, the AND gate 21k is open, and the refresh request signal "REF request" is applied to the data-in terminal of the shift register 21j via the AND gate 21k. Therefore, the shift register 21j
When the refresh signal RRAS is input to the clock terminal of, the output QA of the shift register 21j becomes high level.

Next, when RRAS is applied to the clock terminal of the shift register 21j, the output RE of the NAND gate 21m is output.
FE (see FIG. 8) is at low level, but FIG.
Since the output QA of the shift register 21j is added to the next input terminal DB as shown in FIG.
The output QB of j becomes high level. As described above, the outputs QA to QD of the shift register 21j sequentially become high level each time RRAS is applied to the clock terminal, and this signal is applied to the OR gates 21f-0 to 21f-3.

At the time of backup, since the packup signal * BKUP is at low level, the OR gate 21f
The other input of -0 to 21f-3 is low level, and the OR gates 21f-0 to 21f-3 generate outputs shown in -1 to -3 of FIG. OR gate 21f-0 to 21f-
The output of 3 is given to AND gates 21g-0 to 21g-3, ANDed with the refresh signal RRAS (see FIG. 8) output from the timing control circuit 21a, and given to NOR gates 21h-0 to 21h-3. ..

The NOR gates 21h-0 to 21h-3 invert the outputs of the AND gates 21g-0 to 21g-3, as shown in FIG.
, -1 to -4, refresh signals * RAS0 to * RAS3 divided into four times are output within the refresh cycle to refresh the memory blocks 22a to 22d. Next, during normal operation, the backup signal * B
KUP is at high level, and the timing control circuit 21a
Receives the refresh request signal "REF request"
5, the refresh signal RRAS is output once within the refresh cycle T.

On the other hand, OR gates 21f-0 to 21 of FIG.
The output of f-3 is at high level because the backup signal * BKUP is at high level. Therefore, the AND gates 21g-0 to 21g-3 have the refresh signal RRAS.
Is high level, an output is generated, and this output is given to the NOR gates 21h-0 to 21h-3.

The NOR gates 21h-0 to 21h-3 invert the outputs of the AND gates 21g-0 to 21g-3 and generate the refresh signals * RAS0 to * RAS3 collectively at one time within the refresh cycle T, and the memory. Block 2
2a or memory block 22d is refreshed. As described above, according to the present embodiment, as in the first embodiment, at the time of backup, the refresh signal * RAS
0 to * RAS3 are divided into four times and output within the refresh cycle T, and the refresh signal * RA is normally provided.
Since S0 to * RAS3 are collectively output only once within the refresh cycle T, the peak current consumption of the backup power supply during backup can be suppressed, and
It is possible to suppress an increase in the occupied time of the memory due to the refresh in the normal time.

Further, in this embodiment, since the refresh signal is output by using the shift register, even if the number of memory blocks is increased or decreased, it is possible to easily cope with it by changing the number of stages of the shift register. it can. FIG. 9 is a diagram showing a fourth embodiment of the present invention. In FIG.
The same parts as those in the third embodiment of FIG. 6 are designated by the same reference numerals, and in the present embodiment, compared with the third embodiment,
AND gate 21k and NAND gate 21m are removed,
Instead, a flip-flop 21n and an AND gate 21p
Is provided, and the rest of the configuration is the same as that of the third embodiment.

The flip-flop 21n and the AND gate 21p are provided for controlling the data-in input of the shift register 21j, and the refresh request signal "REF request" becomes high level as described later. Then, the data-in input of the shift register 21j is kept at the high level for a predetermined time. FIG. 10 is a time chart showing the operation of this embodiment. The same signals as those in the time chart of FIG. 8 of the third embodiment are designated by the same reference numerals, and in FIG. Instead of the output REFE of the NAND gate 21m, the output REFE of the flip-flop 21n is shown at.

The shift register 21j shown in FIG.
The signal input to the data-in terminal of is shown. In the time chart of FIG. 10, as in the case of FIG.
Only the time chart at the time of backup is shown,
The normal time chart is omitted because it is almost the same as the original time chart of FIG. Next, the operation of the fourth embodiment of FIG. 9 will be described with reference to FIG.

In FIG. 9, a timer (not shown) generates a pulse signal once every refresh cycle T, and this pulse signal is a refresh request signal "REF request".
(See FIG. 10) As a timing control circuit 21a
Join in. Timing control circuit 21a during backup
When receiving the refresh request signal "REF request", outputs a refresh signal RRAS consisting of four pulses shown in FIG.

The refresh signal RRAS is applied to the clock terminal of the shift register 21j. On the other hand, at this time, the output XQ (inverted output) of the flip-flop 21n
Is high level, the refresh request signal "REF request" is input to the data-in terminal of the shift register 21j through the AND gate 21p, and the shift register 2
The output QA of 1j becomes high level.

Next, when the refresh signal RRAS applied to the clock terminal (inverting input) of the flip-flop 21n becomes low level, the flip-flop 21n is inverted (because the clock input terminal CLK of the flip-flop 21n is an inverting input terminal), The output REFE becomes low level (see FIG. 10). Therefore, AND gate 2
The output of 1p becomes low level (see FIG. 10),
As described in the third embodiment, the outputs QA to QD of the shift register 21j are supplied to the clock terminal RRAS.
Every time is added, the signal sequentially becomes high level, and this signal is added to the OR gates 21f-0 to 21f-3.

At the time of backup, since the backup signal * BKUP is at low level, the OR gate 21f
The other input of −0 to 21f-3 is low level, and the OR gates 21f-0 to 21f-3 are −1 to −3 in FIG.
Produces the output shown in. OR gate 21f-0 to 21f
-3 is applied to AND gates 21g-0 to 21g-3, ANDed with the refresh signal RRAS (see FIG. 10) output from the timing control circuit 21a, and applied to NOR gates 21h-0 to 21h-3. Be done.

The NOR gates 21h-0 to 21h-3 invert the outputs of the AND gates 21g-0 to 21g-3, and FIG.
0 within the refresh period, as shown in -1 to -4
Refresh signals divided into times * RAS0 to * RAS3
To refresh the memory blocks 22a to 22d. Then, the refresh request signal "REF
When "request" becomes low level and is applied to the clear terminal CLK (inverted input) of the flip-flop 21n, the flip-flop 21n is inverted again and its output XQ (inverted output)
Goes high again.

Then, the next refresh request signal "RE
When the "F request" becomes high level, the above operation is repeated. Next, at a normal time, the backup signal * BKUP is at a high level, and the timing control circuit 21a receives the refresh request signal "REF request", and within the refresh cycle T as shown in FIG. 5 of the second embodiment. The refresh signal RRAS is output once.

On the other hand, OR gates 21f-0 to 21 of FIG.
The output of f-3 is at high level because the backup signal * BKUP is at high level. Therefore, the AND gates 21g-0 to 21g-3 have the refresh signal RRAS.
Is high level, an output is generated, and this output is given to the NOR gates 21h-0 to 21h-3.

The NOR gates 21h-0 to 21h-3 invert the outputs of the AND gates 21g-0 to 21g-3, generate the refresh signals * RAS0 to * RAS3 collectively at one time within the refresh cycle T, and execute the memory. Block 2
2a or memory block 22d is refreshed. As described above, according to the present embodiment, as in the first embodiment, at the time of backup, the refresh signal * RAS
0 to * RAS3 are divided into four times and output within the refresh cycle T, and the refresh signal * RA is normally provided.
Since S0 to * RAS3 are collectively output only once within the refresh cycle T, the peak current consumption of the backup power supply during backup can be suppressed, and
It is possible to suppress an increase in the occupied time of the memory due to the refresh in the normal time.

Also in this embodiment, as in the third embodiment, since the refresh signal is output using the shift register, even if the number of memory blocks increases or decreases,
This can be easily handled by changing the number of stages of the shift register.

[0060]

As is clear from the above description,
In the present invention, when the DRAM is backed up by the standby power supply, the refreshing of the memory block of the DRAM is performed in a divided manner, and in the normal state, it is performed collectively.
It is possible to reduce the capacity of the backup power supply that backs up the DRAM without increasing the memory occupation time for refreshing in normal times.

[Brief description of drawings]

FIG. 1 is a principle view of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a time chart of the first embodiment.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a time chart of the second embodiment.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a shift register.

FIG. 8 is a time chart of the second embodiment.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a time chart of the fourth embodiment.

FIG. 11 is a diagram showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 refresh means 1a refresh signal output means 1b refresh signal distribution means 2 dynamic RAM 21 refresh control circuit 21a timing control circuit 21b quaternary binary counter 21c 4 frequency divider circuit 21d selector 21e decoder 21f-0, 21f-3, 21f-3 , 21f-3
OR gate 21g-0, 21g-3 21g-3, 21g-3,
AND gate 21k, 21p
AND gate 21h-0, 21h-3 NOR gate 22a to 22d Memory block 21j Shift register 21m NAND gate 21n Flip-flop

Claims (3)

[Claims] 1. A dynamic RAM (2) comprising a plurality of memory blocks, and refresh means for refreshing the dynamic RAM (2) at a predetermined refresh cycle.
In the dynamic RAM refresh control system including (1), the refresh means (1) refreshes a plurality or one within a refresh cycle according to the presence / absence of a backup signal when a refresh request signal is input. A refresh signal output means (1a) for generating a signal and a refresh signal distribution means (1b) for distributing and outputting a plurality of refresh signals to each memory block of the dynamic RAM (2) are provided. When the dynamic RAM (2) is backed up by the refresh signal output means (1a) generates a plurality of refresh signals within the refresh cycle, the refresh signal distribution means (1b) generates the refresh signal output means (1a). Distributes multiple refresh signals to each memory block of dynamic RAM (2). By outputting, the plurality of memory blocks of the dynamic RAM (2) are divided and refreshed, and normally, the refresh signal output means (1a) generates one refresh signal within the refresh cycle, and the dynamic RAM (2) is generated. A refresh control method for the dynamic RAM, characterized in that the peak current consumption during backup of the dynamic RAM (2) by the standby power supply is suppressed by collectively refreshing the multiple memory blocks of 2). 2. The refresh signal distribution means (1b) comprises a binary counter for counting a plurality of refresh signals generated by the refresh signal output means (1a), and a decoder for decoding the output of the binary counter.
2. A refresh control system for a dynamic RAM according to claim 1, wherein a plurality of memory blocks of the dynamic RAM (2) are divided and refreshed by the output of the decoder. 3. The refresh signal distribution means (1b) comprises a shift register for generating a shift pulse according to a plurality of refresh signals generated by the refresh signal output means (1a), and the dynamic R is provided by the output of the shift register.
2. The dynamic RAM according to claim 1, wherein a plurality of memory blocks of AM (2) are divided and refreshed.
Refresh control method.