JPH0689571A - Dynamic memory device - Google Patents

Abstract

PURPOSE:To reduce a stand-by current (battery backup current) accompanied with the refresh of a dynamic RAM. CONSTITUTION:Distribution of the refresh time of all memory cells in the dynamic RAM is divided into a few numbers of cells having a short refresh time and the greater part of cells having a long refresh time. Then, the greater part of cells are not refreshed instantly by a refresh address signal, and by through, e.g. 3 bit counter 412, these cells are refreshed by prolonging to 3 times of periods of a refresh row address signal. Thus, power at a refreshing time is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory device, and more particularly to a dynamic RAM refresh circuit.

[0002]

2. Description of the Related Art Dynamic RAMs are used not only in general-purpose computers but also in personal computers, word processors, home appliances such as handy type terminal devices and televisions. In such a wide range of applications, dynamic RAM
It is extremely important to reduce the power consumption. This dynamic RAM is suitable for increasing the capacity due to the structure of its memory cell, but since memory information is stored as the amount of charge in a MOS capacitor, the disappearance of information due to leakage current is unavoidable, and it is necessary for recurrent use. Regular refresh cycles are absolutely necessary. This refresh cycle must be performed even in a state without a normal read / write cycle (standby state), and since the refresh cycle itself consumes power as much as a normal read / write cycle, it is necessary to reduce the power consumption of a dynamic RAM. It is a serious obstacle.

One method for reducing the power consumption of the dynamic RAM is to reduce the leak current of the memory cell and extend the cycle of the refresh cycle.
Therefore, conventionally, it is realized in the form of a pseudo SRAM (cell is a dynamic RAM) as shown in FIG.
This limits the function of the substrate bias generator used in a normal dynamic RAM,
The leak current is reduced to extend the cycle of the refresh cycle.

In FIG. 9, writing to the memory 1 is as follows.
The row address input and the column address input are stored in the respective address inverter buffers 2 and 3 by the inverted chip enable clock CE, and the respective decoders 4 and 5 select one word line and one bit line in the memory cell array 1. Then, one cell is selected. Further, by the inverted write enable clock WE, the data input is latched in the data input buffer 6, and this data is given as the data of the above-mentioned selected cell to complete the writing.

In reading, similarly to writing, by selecting a word line and a bit line, the data is given to the bit line, and the data is read through the data bus amplifier 7 and the output buffer 8.

On the other hand, since the cell itself of the pseudo static RAM is the same as the cell of the dynamic RAM, refreshing is necessary. This refresh is
By inputting the inverted refresh clock RFSH, all word address information is generated in the refresh address counter 9 by sequentially counting up, and the word address information selects (reads and rewrites) all word addresses through the row decoder 4. To be achieved. When the inverted refresh clock RFSH is input, the row address input from the outside becomes invalid and only the refresh address input from the refresh address counter 9 becomes valid.

The cycle of the inversion refresh clock RFSH is determined to be a constant value so as to satisfy the memory cell with the shortest refresh interval. For example, in the 1-megabit pseudo-static RAM in this example, since it is determined that all the 512 word lines can be accessed within 8 ms, the inverted refresh clock RFSH must be input every 8 ms ÷ 512 = 16 μs. .

The above refresh method is called pulse refresh, but in this pseudo static RAM, there are other refresh methods. This is R
This is achieved by applying a level of enable (0 V in this memory) in a DC manner, instead of applying a pulse to the inverting terminal of FSH. This is because the internal refresh clock generation circuit 10 automatically refreshes the refresh clock (cell refresh clock) after a certain period of time after the enable level is given to the inverted refresh clock RFSH.
Is a method of generating.

At this time, similarly to the pulse refresh, the row address input from the outside becomes invalid, the refresh address counter 9 is counted up to generate all word addresses, and the refresh operation is performed (cell refresh). The clock cycle of the refresh cycle (cell refresh cycle) in this case is set to be slightly shorter than that of the pulse refresh because external control cannot be performed.

In FIG. 9, in addition to the above configuration,
Input buffer control logic 11, clock generator 12, write control 13, output control 1
4 are provided respectively.

[0011]

In the conventional dynamic RAM (pseudo-static RAM) aiming at low power, a substrate bias is generated in order to reduce a DC-like standby current or a leak current of a merimo cell. I am using it with reduced ability. However, this adversely affects the performance (access time etc.) of the RAM, and there is a problem that performance degradation cannot be avoided.

An object of the present invention is to provide a dynamic memory device capable of extremely reducing a standby current (battery backup current) accompanied by refreshing.

Another object of the present invention is to provide a dynamic memory device in which the refresh cycle of the memory cell is made as long as possible to achieve low power.

[0014]

A dynamic memory device according to the present invention is capable of reading and writing a memory cell selected by a row address signal for row selection and a column address signal for column selection, and A dynamic memory device capable of refreshing a memory cell of a row selected by a refresh row address generated in synchronization with a refresh signal, wherein the refresh row address signal specifies a row belonging to a first group. The first row activates a row designated by the refresh row address signal every time the refresh signal is input.
And the refresh row address signal designates a row belonging to the second group, a row designated by the refresh row address signal is supplied when the refresh signal is applied a plurality of predetermined times. And a second activating means for activating.

In another dynamic memory device according to the present invention, a memory cell selected by a row address signal for row selection and a column address signal for column selection can be read and written and is synchronized with a refresh signal. A refresh type memory device capable of refreshing a memory cell of a row selected by a refresh row address generated by the refreshing row address, the timing generating means generating a timing signal having a cycle of a multiple of the refresh signal; Determining means for determining whether the row address signal designates a row belonging to the first group or a row belonging to the second group; and the refresh row address signal is determined by the determining means as the first row. When it is determined that the row belonging to the group is specified,
Means for activating a row designated by the refresh row address signal at that time in response to a timing signal having the same cycle as the refresh signal; and a row for which the refresh row address signal belongs to the second group by the judging means. Means for activating a row designated by the refresh row address signal at that time in response to a timing signal having a cycle of a multiple of the refresh signal when it is determined to be designated. Characterize.

[0016]

First, the principle of the present invention will be described with reference to FIG. This figure is one example of data showing the distribution of the number of fail cells with respect to the refresh interval of the dynamic RAM. The horizontal axis represents the refresh interval, and the vertical axis represents the number of memory cells in error. As is clear from the figure, when the refresh interval is short, almost no error occurs, and when the refresh interval is sufficiently long, all memory cells fail.

In the middle thereof, after a region in which a very small number of memory cells are in error continues for a while, a large number of memory cells tend to suddenly make an error. This means that the margin of the refresh interval of the original memory cells is a point at which the majority of memory cells make an error, but some manufacturing error causes an area where a small number of memory cells make an error. Probably implied.

A is the point at which a small number of memory cells start error, and B is the point at which the majority of memory cells fail.
Then, in the conventional dynamic RAM, the refresh interval is set so as to satisfy the point A in order to guarantee the information of all the memory cells. On the other hand, the point intended by the present invention is to guarantee the information of all the memory cells by applying a plurality of types of refresh intervals so as to satisfy the points A, B, or the points between the points A and B. Is.

The great advantage of this technique is that most of the refresh intervals are set near the time point B for ensuring the information of the majority of memory cells.
The refresh interval is significantly longer than that of the conventional dynamic RAM (which is set near the point A), so that a remarkable low power can be achieved. Normally, the value of the point A and the value of the point B have a difference of 10 times or more. This is a dynamic type R in the present invention.
AM shows that power consumption can be suppressed to 1/10 or less as compared with the conventional dynamic RAM.

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1A shows the entire structure. This figure is
In order to clarify the difference from the conventional example shown in, some of the duplicated portions are omitted. The main difference lies in the row decoder. FIG. 1 (B) shows the structure of a rectangular portion 41 in the row decoder 4 in FIG. 1 (A). Figure 9
In the conventional dynamic RAM (pseudo-static RAM) in FIG. 1, only the decoder circuit and the word driver in FIG.

However, the dynamic RA according to the present invention
In M, as shown in FIG.
3-bit counter 41 in addition to word driver 413
2 and a circuit of a selector 411 are added. The 3-bit counter 412 has a structure that can be programmed to any one of "through connection", "1-bit counter", "2-bit counter", and "3-bit counter" by some external programming means.

An example of the structure of this programmable 3-bit counter is shown in FIGS. 2 (A) to 2 (D). In the figure, reference numerals 201, 202 and 203 denote 1-bit flip-flops, respectively, which constitute a 3-bit counter by three-stage connection. However, these flip-flops 20
1, 202 and 203 are F / F program terminals 211 and 211
It is designed to be deactivated by laser cutting 12, 213. Furthermore, in order to determine the passage as a counter, the wiring program terminal 221,
There are 222 and 223, which allow programming from conducting to non-conducting by laser cutting.

Now, FIG. 2A shows a state where no programming is performed. At this time, the decoded signal from the left passes through the flip-flops 201, 202, and 203, so that the signal is transmitted to the right word line only after the decoded signal for eight times is given.

Next, FIG. 2B shows a state in which one bit is inactivated. At this time, the decode signal from the left is supplied to the word line on the right for the first time after being given four times. Similarly,
FIG. 2C shows a state where all 3 bits are inactivated. At this time, the decode signal from the left is completely through-connected to the right word line side.

The program of the 3-bit counter is automatically executed in the probing test of the dynamic RAM at the wafer stage. That is, four stages of refresh time are performed for the wafer probing test item. These times are (1) worst refresh time (T0), (2) 2 × t0, (3) 4 × t0.
, (4) 8 × t0. Then, PASS / FAIL information and FAIL word line information of these four tests are recorded.

Program work is (1) PASS,
The word line of FAIL in (2) is P in FIG.
Figure 2 for the word line of FAIL in ASS, (3)
The word lines of PASS in (C) and (3) and FAIL in (4) are performed as shown in FIG. 2 (B), and P in (4).
For the ASS word line, the process shown in FIG. 2A, that is, no programming is performed.

Here, the number of word lines on which the actual program work of FIGS. 2B to 2D is performed is predicted to be about 10 at most, as can be seen from FIG. 8 again. It Most of the remaining word lines (for example, about 500 in a 1-megabit memory) are in a non-programmed state.
The merits of the memory thus programmed are described below.

The dynamic signal of this memory is provided so as to satisfy the worst refresh time t0 (for example, 8 ms). However, the word line for which the refresh operation is actually performed at intervals of 8 ms is only the word line subjected to the program processing in FIG. The word line programmed in FIG. 2C is 8 ms × 2 = 16 ms.
The word line programmed in (B) is 8 ms × 4 = 32
ms, and the non-program word line in FIG. 2 (A) is 8 m
Refresh will be performed at intervals of s × 8 = 64 ms.

As described above, the dynamic RAM has a low power consumption (especially, the low power consumption when the battery is up).
For, it is very effective to extend the refresh time interval. Especially CMOS type dynamic type R
In AM, the refresh interval and the current during battery backup are almost inversely proportional. That is, when 98% (500/512) of the word lines have eight times the refresh time as in the present invention, it is considered that the current at the time of battery backup of the entire memory is almost 1/8. It will not be a problem.

Next, a second embodiment of the present invention will be described with reference to FIG. In the programmable ROM 30 in this figure,
1-bit information is stored for all word addresses, and the output of this ROM is TRUE (D) and COMPL.
It is output separately in EMENT (inverted D).

On the other hand, the counter 31 in this figure is composed of (the number of word address bits) + (3 bits), and its structure is as shown in FIG.
It has a bit (total word number bit) counter 311 and a 3-bit counter 312. Only when the carry output of the 3-bit counter 312 is generated by the AND gate 313, the refresh signal is
It is extracted by 14 and output (corresponding to output b). FIG. 5 is a time chart of this embodiment, and shows an output example for a memory having 3 word address bits (8 word addresses).

The contents written in the programmable ROM 30 correspond to the contents written in the programmable 3-bit counter 412 of each row decoder section of the first embodiment. That is, in the second embodiment, the programmable 3-bit counter 412 of the row decoder section of the first embodiment is gathered in one place for all words and rewritten as a programmable ROM.

Therefore, "1" or "0" is stored in the programmable ROM according to the magnitude of the refresh time of the word line. For example, 8ms or more 8ms x 8
"1" is written to the word line of 64 ms or less, and "0" is written to the word line of 64 ms or more. As described in the first embodiment, from the refresh time distribution (FIG. 8) of the memory cells of the dynamic RAM, "0" is overwhelmingly written in most word addresses, that is, writing is unnecessary.

The present embodiment relates to a dynamic RAM in which a refresh signal and a refresh address signal are externally applied and refreshing is performed.

The operation of this RAM is as follows. In the refresh cycle, at the same time as the refresh signal is input, the refresh address input is applied from the row address input used for reading / writing.
Programmable ROM for refresh address input immediately
30, if the address belongs to a refresh group of 64 ms or less, D is output, and if the address belongs to a refresh group larger than that, D is output.

On the other hand, the refresh signal is given to the counter 31 and outputs the output a or the output b. The selection of either the output a or the output b (which is the refresh signal for the actual RAM) is determined by D and inversion D. That is, for the word line (word address) group of 8 ms or more and 64 ms or less, the refresh signal of the output a, and for the word address group of 64 ms or more, the output b (refreshed at a cycle eight times the output a), the gate circuits 32 to 34. Will be generated from.

As a result, even if a refresh signal from the outside is given so as to satisfy the worst refresh time (for example, 8 ms), in the inside of the RAM, for most word addresses, eight times the cycle ( Eg 8
The refresh operation is performed at (ms × 8 = 64 ms), and a remarkable reduction in power consumption at the time of refresh is expected.

Next, a third embodiment of the present invention is shown in FIG.
In this embodiment, the refresh address counter 35 is set to RA.
This is for a dynamic RAM of the type built in M. In this RAM, a refresh address is generated by an internal refresh address counter 35 in response to an external refresh signal (corresponding to pulse refresh).

The programmable ROM 30 and the counter 31 in this figure are the same as those in FIG. Therefore, the refresh address is only generated internally, and its operation can be considered to be almost the same as that in FIG.

Next, a fourth embodiment of the present invention is shown in FIG.
The present example is for a dynamic RAM of a type without an external refresh signal (which looks like almost a static RAM). The programmable ROM 30 and the counter 31 in this figure are
Again, it is the same as that of FIG.

In this example, since there is no external refresh signal, the signal applied to the counter 31 is automatically generated by the refresh address counter 35 (corresponding to cell refresh) and applied to the counter 31 as a refresh signal. As for the operation, since a refresh control cannot be performed from the outside to the RAM, a busy signal output 36 is provided to indicate whether the read / write is possible or not from the outside. As a result, when this RAM is used, it can be used as an almost normal static RAM and controlled so that the RAM access is stopped only when a busy signal is generated.

Further, as an advantage of this embodiment, since the refresh cycle of most word addresses is eight times, the utilization efficiency of RAM (the ratio of refresh cycles in all accesses) can be expected to be eight times higher. is there. Furthermore, since the power consumption at the time of battery backup is reduced, it can be handled in the same way as a normal static RAM even at the time of battery backup.

[0043]

As described above, according to the present invention, all rows of memory cells are divided into two groups, a group having a short refresh interval and a group having a long refresh interval, and it is determined in advance to which group each row belongs. By keeping
Whenever a row address for refresh specifies a row that belongs to a group, it is automatically determined each time, and if it belongs to a long group, the refresh interval is set to be long. Power can be achieved.

[Brief description of drawings]

1A is a block diagram showing a first embodiment of the present invention, and FIG. 1B is a circuit diagram showing a specific example of a row decoder.

FIG. 2 is a detailed view of a 3-bit counter in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

4 is a detailed view of a counter in the embodiment shown in FIG.

5 is a time chart of the embodiment shown in FIG.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention.

FIG. 8 is one data example showing a distribution of the number of fail cells with respect to a refresh interval of a dynamic RAM.

FIG. 9 is a schematic block diagram of a conventional dynamic memory device.

[Explanation of symbols]

 1 memory cell array 2 row address inverter buffer 3 column address inverter buffer 4 row decoder 5 column decoder / data bus 30 P-ROM 31 counter 32-34 gate 201-203 flip-flop 211-213 F / F program terminal 221-223 wiring program Terminal 311 n-bit counter 312 3-bit counter 313, 314 AND gate 410 decoder circuit 411 selector 412 3-bit counter 413 driver

Claims (4)

[Claims] 1. A refresh row address capable of reading and writing a memory cell selected by a row address signal for row selection and a column address signal for column selection, and by a refresh row address generated in synchronization with a refresh signal. A dynamic memory device capable of refreshing a memory cell of a selected row, wherein when the refresh row address signal specifies a row belonging to a first group, the refresh row is input every time the refresh signal is input. When the refresh row address signal designates a row belonging to the second group, the refresh signal is given a plurality of predetermined times when the refresh row address signal designates a row belonging to the second group. Second activation, which sometimes activates the row designated by the refresh row address signal Dynamic memory device which comprises a stage, a. 2. The first activating means is provided for each row of the memory cells and decodes the refresh row address signal, and the corresponding activating row directly responds to the decoding output. The second activating means is provided corresponding to each row of the memory cells and decodes the refresh row address signal. 2. A counter comprising: a counter having a number of bits each of which is counted and equal to the predetermined number of times; and means for activating a corresponding row in response to each carry output of the counter. Dynamic memory device. 3. A memory read / write operation selected by a row address signal for row selection and a column address signal for column selection is possible, and selected by a refresh row address generated in synchronization with the refresh signal. A dynamic memory device capable of refreshing memory cells in different rows, the timing generating means generating a timing signal having a cycle of a multiple of the refresh signal; and a row in which the refresh row address signal belongs to a first group. Determining means for determining whether to specify a row belonging to the second group, and the determining means for specifying the row belonging to the first group by the refresh row address signal. When judged, in response to a timing signal of the same cycle as the refresh signal, then Means for activating a row designated by the refresh row address signal, and the refresh signal of the refresh signal when the refresh row address signal determines that the refresh row address signal designates a row belonging to the second group. A dynamic memory device comprising: means for activating a row designated by the refresh row address signal at that time in response to a timing signal having a multiple cycle. 4. The determination means receives the refresh row address signal as input, and prestores group information indicating which of the first and second groups the corresponding address corresponds to, respectively. The dynamic memory device according to claim 3, wherein the dynamic memory device is a storage means.