JPH05298141A - Integrated circuit for specified use - Google Patents

Abstract

PURPOSE:To improve visible observation property for the operation of an internal module. CONSTITUTION:This circuit is provided with a first multiplexer 8 to be selected by a test mode signal TEST separately applied an arithmetic result output bus XBUS from a register arithmetic part RALU 6 and the output of the specified module connected to an external output terminal among plural module M1, M2...MN, and second multiplexer 9 to input data from a parameter setting part PREG 3, to input output signals, which are not directly impressed to the outside, from the plural modules M1, M2...MN, to select any one of inputs corresponding to signals from a microprogram control part MCTL 4 and to impress it to a register arithmetic part PREG. Thus, it is not necessary to increase the number of multiplexer switching signal terminals for tests.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application specific integrated circuit (ASIC; Applicat) realizing a testability design method.
ion specific integrated circuit), in detail, the observability of the module at the time of the test of the ASIC adopting the microprogram control method is improved.

[0002]

2. Description of the Related Art Integrated circuits for specific applications (hereinafter referred to as ASICs)
Called)), the circuit configuration becomes large-scale,
In order to ensure high reliability (sufficient failure detection rate) in the case of complication, how to efficiently test a single chip is an important issue. The present invention is particularly directed to an ASIC that employs a microprogram control method, and a general example of such an ASIC is shown in FIG. The ASIC 1 in this figure is a CPU interface unit INF2 that receives a chip select signal CS, a read / write control signal RWC, a host address HA (l bit), etc. for asynchronous access from a host computer (not shown). , Read enable signal from INF2 and output corresponding register value to output port BO
Parameter setting unit PRE which sends the parameter command from the host computer to the corresponding register via the input port BI upon receiving the write enable signal
With G3. This input port BI and output port BO
By exchanging data HD (m bits) with the outside, the ASIC 1 can bidirectionally communicate with a host computer or the like of a higher rank. The transmission buffer BO is controlled by the signal HOE. Furthermore, the micro program control unit MCT
L4 is an address sequencer ADSEQ41 for generating a micro address MICA, a micro address MIC
ROM4 that receives A and outputs microcode INST
2. A pipeline register PPL43 for temporarily holding the microcode INST and a decoder DEC44 are provided. The multiplexer MUX5 selects the value of the specific register in PREG3 under the control of MCTL4 and gives it to the register operation unit RALU6 as data d. The register operation unit RALU6 has data d from the MUX 5, internal registers tr0, tr1, ..., Constant value data.
It has a source selector SOR61 for selecting two data sources of all "0", and an arithmetic unit ALU62 for performing an arithmetic operation on the value selected by the SOR61. Also, the plurality of modules M1, M2, M3, ...
During the operation of C1, it is controlled via the MCTL4, RALU6, and the operation result output bus XBUS. The ASIC 1 of the micro program control system is configured as described above, and the plurality of internal modules M are set by the MCTL 4 according to the instruction from the host computer.
1, M2, ..., MN are controlled and operate. Here, among the plurality of modules M1, M2, ..., MN, the module M1 is assumed to send the data MDO to the outside from the output port GO. Data MDI is externally fetched from the input port GI, and the output port GO is controlled by the signal MOE.

In order to increase the observability of the test operation when testing whether the operation of the modules M1, M2, ..., MN inside the ASIC 1 is normal or abnormal,
A circuit having a configuration as shown in FIG. 5 was adopted. That is, in the example of FIG. 5, the multiplexer MUX7 is provided and the module M1
Output from the module to the outside MD0, output M102 from module M1 to module M2, output M201 from module M2 to module M1, output M202 from module M2 to module M3, output M302 from module M3 to module M2, etc. A signal to be observed is used as its input, one of the inputs is selected by an external test multiplexer switching signal TSEL (r bit), and the signal is output from the output line MDOUT to the outside via the output port GO. is there. Then, the output signal MD can be observed by a display unit, a recording unit, or the like (not shown), and the normal or abnormal operation of the module can be known.

[0004]

However, in the conventional ASIC test system as described above, when the number of modules to be tested increases and the number of outputs increases, the input of the multiplexer 7 increases. In response to this, an external test multiplexer switching signal TSE
The number of terminals for receiving L (r bits) also increases from r bits, and the number of terminals of the entire ASIC is limited, which is not preferable.

The present invention solves such a problem, and an object of the present invention is to improve the observability of the operation of an internal module without increasing the number of terminals in an ASIC adopting a microprogram system.

[0006]

The present invention which achieves such an object corresponds to a host computer by a bidirectional communication means, a parameter setting section for reading / writing parameters or commands, and a micro address generated. A micro program control unit for outputting a micro code in synchronization with a system clock; a register operation unit having an internal register for performing an operation on data given from the parameter setting unit side and outputting the operation result; In an application-specific integrated circuit including a plurality of modules controlled by the program control unit via the register calculation unit, a calculation result output bus from the register calculation unit and an external output terminal of the plurality of modules are connected. Test module that is separately provided with the output of the specific module A first multiplexer selected by a signal, and data input from the parameter setting section and output signals from the plurality of modules which are not directly output to the outside are input by a signal from the microprogram control section. And a second multiplexer for selecting any one of the inputs and giving it to the register arithmetic unit.

[0007]

In the application-specific integrated circuit of the present invention, when the test mode signal is active, the output signal of the desired module is sent to the operation result output bus by the second multiplexer and the register operation unit, and The multiplexer selects this operation result output bus and sends it to the outside.

[0008]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is an example of an ASIC 1 embodying the present invention. In this figure, blocks having the same reference numerals as those of the conventional ASIC 1 shown in FIGS. 4 and 5 have the same functions. The present invention is characterized in that the first multiplexer 8 and the second multiplexer 9 are provided. The first multiplexer 8 is a module M1 for transmitting a signal to the outside.
Output signal MDOUT and one of the operation result output buses XBUS are selectively output by a test mode signal TEST applied from the outside. here,
The operation result output bus XBUS is selected when the test mode signal TEST = "H". The output MD0 of the first multiplexer 8 is output to the outside via the output port G0. The second multiplexer 9 has a value P1 of a specific register in the parameter setting unit PREG3.
, PK and output signals M102, M201, M202, etc. of the plurality of modules M1, M2, ..., MN are selected by the microcode S in the pipeline register PPL43 in the microprogram control unit MCTL4 and registered as data d. It is given to the calculation unit 6.

Next, the AS of the present invention configured as described above
In IC1, microprogram control unit MCTL4
The operation when testing the plurality of modules M1, M2, ..., MN controlled by the register arithmetic unit RALU3 will be described with reference to the time chart of FIG. (1) First, the case where the output M102 of the module M1 is output to the outside will be described. In the n1 cycle, at the rising edge of the system clock CP, the microcode S (M102) for instructing to select the output M102 from the module M1 from the MCTL4 is given to the input S of the second multiplexer 9. As a result, the output M of the second multiplexer 9 becomes the output M.
The data a1 related to 102 is output. Subsequently, in the register operation unit RALU6, the source of the input d and the data "0" is selected by the SOR61, the logical sum operation is performed by the ALU62, and the result is sent to the operation result output bus XBUS.
Therefore, the data a1 of the output M102 is output to the calculation result output bus XBUS. On the other hand, the test mode signal TEST to the first multiplexer 8 is set to "H" at the rising edge of the system clock CP in the n1 cycle, so that the first multiplexer 8 outputs the operation result output bus XBU.
The value of S is selected, and the value of the operation result output bus XBUS appears at its output MDO. Further, since the output enable signal MOE of the output port GO has been set to “H” in advance,
The output MD of the ASIC1 is the data a of the output M102.
It becomes 1. The data a1 relating to the output M102 is strobed at an appropriate strobe timing STB. Subsequently, the same operation is repeated in the N2 cycle and the n3 cycle, and the output MD becomes the data a2 and a3 applied to the output M102 sequentially. (2) Next, output M201 of module M2 to output MD
The case will be described. In the m1 cycle, the module M is input to the input S of the second multiplexer 9 at the rising edge of the system clock CP.
The microcode S (M201) is given which instructs to select the output M201 from 2. As a result, the data b1 corresponding to the output M201 is output from the output d of the second multiplexer 9. Then, the register calculation unit R
Select source of input d and data "0" with ALU6, and AL
A logical sum operation is performed in U62, and the result is output to the operation result output bus XBUS. As a result, the data b1 relating to the output M201 is output to the calculation result output bus XBUS. On the other hand, the first multiplexer 8 is supplied with the test mode signal TEST = “H”, and therefore selects the value of the operation result output bus XBUS, and the output MDO thereof has the value b1 of the operation result output bus XBUS. Is output. Therefore, the output MD of this circuit becomes the data b1 related to the output M201. The data b1 associated with the output M201 is strobed at an appropriate strobe timing STB. Subsequently, the same operation is repeated in the m2 cycle and the m3 cycle, the data b2 and b3 relating to the output M201 are sequentially output to the output MD, and strobed at an appropriate timing STB. Similarly, the data of the modules M3, M4, ...
Output MD.

In the above embodiment, the test mode signal TEST is applied from the outside as the input switching signal of the first multiplexer 8. However, as shown in FIG. Controller MC
The output of the pipeline register PPL43 of TL4 may be given as the multiplexer input switching signal S. With such a configuration, a terminal for receiving the test mode switching signal TEST from the outside is unnecessary.

[0011]

As described above, according to the present invention,
Output signals from a plurality of modules that can be controlled by the micro program control unit and the register arithmetic unit are selectively output to the register arithmetic unit via the second multiplexer without being directly output to the external terminals. And a first multiplexer for switching the operation result output bus from the register operation unit and the output data of the specific module connected to the external output terminals in the plurality of modules by the test mode input signal. Thus, the output signals desired to be observed from the plurality of modules can be output to the outside via the operation result output bus and the output port. Therefore, even if the number of modules to be tested is large, it is not necessary to add an additional multiplexer switching signal terminal for testing from the outside, and the observability of the operation of internal modules can be improved.

[Brief description of drawings]

FIG. 1 is a circuit example of an application specific integrated circuit embodying the present invention.

FIG. 2 is a timing chart showing the operation of the application specific integrated circuit of the present invention.

FIG. 3 is another embodiment of the present invention.

FIG. 4 is a circuit example of a conventional application-specific integrated circuit.

FIG. 5 is a circuit example of a conventional application-specific integrated circuit.

[Explanation of symbols]

 1 ASIC 2 CPU interface unit INF 3 Parameter setting unit PREG 4 Micro program control unit MCTL 41 Address sequencer ADSEQ 42 Memory ROM 43 Pipeline register PPL 44 Decoder 44 5,7 Multiplexer 6 Register operation unit RALU 61 Source selector 62 Operation Part ALU 8 First multiplexer 9 Second multiplexer M1, M2, ..., MN module

Claims (1)

[Claims] 1. A parameter setting unit for reading / writing parameters or commands from a host computer by bidirectional communication means, and a microprogram control for generating a microaddress and outputting a corresponding microcode in synchronization with a system clock. Section, a register operation section having an internal register for performing an operation on the data given from the parameter setting section side and outputting the operation result, and a plurality of units controlled by the microprogram control section via the register operation section. In a specific-purpose integrated circuit including the module, a test mode signal to which an operation result output bus from the register operation unit and an output of a specific module connected to an external output terminal of the plurality of modules are separately provided. The first multiplexer selected by the The register operation is performed by inputting data from the meter setting unit and inputting output signals from the plurality of modules that are not directly output to the outside, and selecting one of the inputs according to a signal from the microprogram control unit. And a second multiplexer provided to the unit.