JP3106442B2 - Application specific integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application specific integrated circuit (ASIC; Applicat) which realizes a design method for testability.
More specifically, the present invention relates to an improvement in a method of generating constant data at the time of testing an ASIC employing a microprogram control method.

[0002]

2. Description of the Related Art Application-specific integrated circuits (hereinafter referred to as ASICs).
) Design, the circuit configuration is large-scale,
When the complexity increases, how to efficiently test a single chip has become an important issue in order to ensure high reliability (sufficient failure detection rate). The present invention is particularly directed to an ASIC employing a microprogram control method. An example of such an ASIC is shown in FIG. The ASIC 10 in this figure is a host computer (not shown)
The CPU receives the chip select signal CS, the read / write control signal RWC, the host address HA (1 bit), etc. for asynchronous access from the CPU interface sections INF2, INF2, and receives the read enable signal from the corresponding register to receive the read enable signal. A parameter register section PREG that sends a value HDO to the output port BO or receives a write enable signal and writes a parameter command HDI from the CPU to the corresponding register via the input port BI.
3 With the input port BI and the output port BO, the ASIC 10 can perform two-way communication with a host computer or the like. Further, the microprogram control unit M
CTL4 includes an address sequencer ADSEQ41 for generating a microaddress MICA, and a microaddress M
RO that receives ICA and outputs microcode INST
M42, a pipeline register PPL43 for temporarily holding the microcode INST, and a decoder DEC44. The multiplexer unit MUX5 selects the value of a specific register in the PREG3.
Upon receiving data d from UX5, internal registers tr0, tr
1. It has an ALU 62 that performs an operation on the value from the source selector SOR61. Further, a plurality of modules M1, M
2,..., MN are in operation of the ASIC 10
It is controlled by MCTL4 and RALU6 via data on bus YBUS. The ASIC 10 of the microprogram control system is configured as described above, and a plurality of internal modules M1, M2,..., MN are controlled and operated by the MCTL 4 according to an instruction from a host computer at a higher level. The data width to be handled is n bits.

In order to test whether the operation of the module inside the ASIC 10 is normal or abnormal,
The following method was used. That is, when a constant ROM 7 is previously set in the ASIC 10 and a test mode is designated, constant data necessary for testing is read from the constant ROM 7 and the RAL is read via the MUX 5.
This is a method of storing data in a register in U6 and testing a target module.

[0004]

However, in the above-mentioned conventional ASIC test system, the ASI
A constant ROM must be provided in C, which hinders downsizing of the circuit. That is, the constant ROM is mainly used only in the test mode, and is not used at all in the normal operation mode (actual use). Also,
If the number of types of constant data increases due to an increase in the number of modules, the capacity of the constant ROM increases, and the scale of the ASIC increases accordingly.

An object of the present invention is to solve such a problem, and an object of the present invention is to realize an ASIC that can efficiently handle constant test data of an ASIC employing a microprogram method.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a parameter register unit for reading / writing a parameter command from a host computer via a bidirectional data bus, and a microaddress. And a micro-program controller for generating a corresponding micro-code in synchronization with a system clock, a multiplexer for selecting a specific register of the parameter register according to the micro-code, and an internal register. And a register operation unit for performing an operation by using an output from the multiplexer unit as one of data sources, and a plurality of modules controlled by the microprogram control unit. Data input from the bus is input to the multiplexer Wherein the multiplexer unit transmits data input from the bidirectional data bus to one of the internal registers of the register operation unit according to an instruction of the microprogram control unit. It is.

[0007]

According to the application specific integrated circuit of the present invention, when the test mode is designated, data transmitted from the outside is selected by the multiplexer section and supplied to the register operation section.
The test is sent to the target module for testing.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is an example of an ASIC 10 embodying the present invention.
In this figure, blocks having the same reference numerals as those of the conventional ASIC 10 shown in FIG. 3 have the same functions. In the present invention, the external data HDI received at the input port BI is supplied to the PREG3 and also to the MUX5. Then, the constant ROM installed in the conventional ASIC 10 is abolished. MUX5 is the P in MCTL4
By the microcode output signal from PL43, PR
The value of a specific register in EG3 or the data HDI from input port BI is selected and given to RALU6 as data d. In the RALU 6, the data d from the MUX 5 is used as one of the data sources and the internal register tr
The ALU 62 performs a logical arithmetic operation together with the values in 0 and tr1.

Next, the AS of the present invention configured as described above will be described.
In the IC 10, a module controlled by the MCTL 4 is set as a test mode, and an operation for generating constant test data required for testing and an operation for giving the constant test data to a specific module are shown in FIG. This will be described with reference to a chart. It is assumed that the bit width n = 16. The test mode is specified, the chip select signal CS from the host computer is “0” (inactive), the read / write control signal RWC is “1”, the host address HA is all “1”, and the enable signal. OE is set to “0” in order to take in data HD from outside (select the input port BI). An external test is performed at a slightly delayed timing due to the rise of the system clock CP in the first cycle.
Data HD = 16h1234 (data "1 in hexadecimal notation
234 "). The constant test data is provided from an external host computer or the like.
X5 selects the currently fetched data HDI based on the microcode signal S from the MCTL4 and sets it as the output d. The RALU 6 selects the source of the input d and data “0”, performs a logical sum operation in the ALU 62, and outputs the result to the bus YBUS. At the rise of the system clock CP in the second cycle, the constant data 16h1234 on the bus YBUS is
The data is stored in the register tr0 in the ALU6. Further, in this second cycle, the contents 16h of the internal register tr0
1234 is read, and data “0” and a source are selected.
The logical sum operation is performed in the LU 62, and the logical sum operation is transmitted to the bus YBUS and written to, for example, the module M1. Module M
1 executes an operation corresponding to the written data, sends the output result to the input / output port MD1, and performs a test operation. External data HD = 16 at a timing slightly delayed from the rise of the system clock CP in the third cycle.
h5678, and similarly input A through MUX5.
It is sent to the LU 62 to perform a logical sum operation, and the bus YBUS
Output to At the rise of the system clock CP in the fourth cycle, the constant data 16h5678 on the bus YBUS is stored in the register tr0. Further, in the second cycle, the contents 16h1 of the internal
234 is read, data “0” is selected as the source, and AL
Perform a logical sum operation in U62 and send it to the bus YBUS,
This time, write to module M2. The module M2 performs an operation corresponding to the written data, sends an output result to the input / output port MD2, and performs a test operation. As described above, an arbitrary constant test data can be stored in a register in the RALU 6 from the outside, and a test operation can be performed by giving the value of the register to an arbitrary module.

[0010]

As described above, according to the present invention,
Constant test data is input from the upper host computer using the input port of the bidirectional data bus, stored in an internal register in the register operation unit and given to the module, so that constant test data is generated inside the ASIC. There is no need to provide a ROM for the ASIC, and the ASIC can be tested efficiently.

[Brief description of the drawings]

FIG. 1 is a circuit example of an application specific integrated circuit embodying the present invention.

FIG. 2 is a timing chart illustrating the operation of the application specific integrated circuit of the present invention.

FIG. 3 is a circuit example of a conventional application-specific integrated circuit.

[Explanation of symbols]

 10 ASIC 2 CPU interface section INF 3 Parameter register section PREG 4 Microprogram control section MCTL 5 Multiplexer section MUX 6 Register operation section RALU M1, M2,..., MN module

Claims (1)

(57) [Claims] 1. A parameter register unit for reading / writing a parameter command from a host computer via a bidirectional data bus, and generating a micro address and synchronizing a corresponding micro code with a system clock. And a multiplexer for selecting a specific register of the parameter register according to the micro code, and an internal register having an output from the multiplexer as one of data sources. A register operation unit for performing an operation and an application-specific integrated circuit including a plurality of modules controlled by the microprogram control unit, wherein data input from the bidirectional data bus is connected to an input of the multiplexer unit; The multiplexer section includes the microprogram. Application specific integrated circuits, characterized in that for transmitting the data inputted from said bidirectional data bus to one of the internal registers of the register arithmetic unit in response to an instruction from the control unit.