JPH0529625A - Method for forming gate oxide film and field effect transistor - Google Patents

Method for forming gate oxide film and field effect transistor

Info

Publication number
JPH0529625A
JPH0529625A JP3201193A JP20119391A JPH0529625A JP H0529625 A JPH0529625 A JP H0529625A JP 3201193 A JP3201193 A JP 3201193A JP 20119391 A JP20119391 A JP 20119391A JP H0529625 A JPH0529625 A JP H0529625A
Authority
JP
Japan
Prior art keywords
gate oxide
oxide film
film
polysilicon
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3201193A
Other languages
Japanese (ja)
Inventor
Yoshio Okamoto
良生 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP3201193A priority Critical patent/JPH0529625A/en
Publication of JPH0529625A publication Critical patent/JPH0529625A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent the formation of a weak spot in the entire gate oxide films by depositing the upper gate oxide film on the lower gate oxide film which is formed by thermal oxidation of the surface side of a polysilicon film that is deposited on a substrate. CONSTITUTION:A polysilicon film 2 is deposited on the upper surface of a substrate 1. Then, the surface side of the polysilicon 2 undergoes thermal oxidation. A semiconductor thin film 3 is formed of the polysilicon film 2 which is not thermally oxidized. A lower gate oxide film 4 comprising silicon oxide formed by thermal oxidation of the upper surface side of the polysilicon is formed on the surface of the semiconductor film 3. Then, an upper gate oxide film 5 comprising silicon oxide is deposited by sputtering method on the surface of the lower gate oxide film 4. Thereafter, the upper gate film 5 is made dense by annealing. In this way, the formation of a weak spot in the entire gate oxide films can be prevented almost perfectly.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はゲート酸化膜の形成方
法および電界効果型トランジスタに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film and a field effect transistor.

【0002】[0002]

【従来の技術】電界効果型トランジスタにおいてゲート
酸化膜を形成する場合、ガラス等からなる基板上に堆積
されたポリシリコン膜の表面側を熱酸化することによ
り、熱酸化されないポリシリコン膜によって半導体薄膜
を形成すると共に、該半導体薄膜の表面に酸化シリコン
からなるゲート酸化膜を形成する方法がある。
2. Description of the Related Art When a gate oxide film is formed in a field effect transistor, the surface side of a polysilicon film deposited on a substrate made of glass or the like is thermally oxidized, so that a polysilicon film which is not thermally oxidized is used to form a semiconductor thin film. And a gate oxide film made of silicon oxide is formed on the surface of the semiconductor thin film.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
このような電界効果型トランジスタにおけるゲート酸化
膜の形成方法では、ポリシリコン膜の表面に結晶粒界に
よる凹凸が形成されている関係から、この凹凸の表面側
を熱酸化してもゲート酸化膜が均一に成長せず、ウィー
クスポットが生じ、このためしきい値電圧が大きくな
り、またゲートリーク電流が大きくなってしまうという
問題があった。この発明の目的は、ゲート酸化膜にウィ
ークスポットが生じるのをほぼ完全に防止することので
きるゲート酸化膜の形成方法および電界効果型トランジ
スタを提供することにある。
However, in the conventional method of forming a gate oxide film in such a field effect transistor, since unevenness due to crystal grain boundaries is formed on the surface of the polysilicon film, this unevenness is generated. There is a problem that the gate oxide film does not grow uniformly even if the surface side of the substrate is thermally oxidized and a weak spot is generated, which increases the threshold voltage and the gate leak current. An object of the present invention is to provide a method for forming a gate oxide film and a field effect transistor capable of almost completely preventing a weak spot from occurring in the gate oxide film.

【0004】[0004]

【課題を解決するための手段】この発明は、基板上に堆
積されたポリシリコン膜の表面側を熱酸化することによ
り、熱酸化されない前記ポリシリコン膜によって半導体
薄膜を形成すると共に、該半導体薄膜の表面に酸化シリ
コンからなる下層ゲート酸化膜を形成し、該下層ゲート
酸化膜の表面に酸化シリコンからなる上層ゲート酸化膜
を堆積するようにしたものである。
According to the present invention, a surface of a polysilicon film deposited on a substrate is thermally oxidized to form a semiconductor thin film by the polysilicon film which is not thermally oxidized, and the semiconductor thin film is also formed. A lower layer gate oxide film made of silicon oxide is formed on the surface of, and an upper layer gate oxide film made of silicon oxide is deposited on the surface of the lower layer gate oxide film.

【0005】[0005]

【作用】この発明によれば、基板上に堆積されたポリシ
リコン膜の表面側を熱酸化してなる下層ゲート酸化膜上
に上層ゲート酸化膜を堆積しているので、下層ゲート酸
化膜と上層ゲート酸化膜とが構造的に互いに独立したも
のとなり、ポリシリコン膜の表面側を熱酸化してなる下
層ゲート酸化膜にポリシリコン膜の表面の結晶粒界に起
因するウィークスポットが生じても、このウィークスポ
ットを上層ゲート酸化膜との界面で終端させることがで
き、したがって全体に亘るゲート酸化膜にウィークスポ
ットが生じるのをほぼ完全に防止することができる。
According to the present invention, since the upper gate oxide film is deposited on the lower gate oxide film formed by thermally oxidizing the surface side of the polysilicon film deposited on the substrate, the lower gate oxide film and the upper layer are formed. The gate oxide film becomes structurally independent from each other, and even if a weak spot due to a crystal grain boundary on the surface of the polysilicon film occurs in the lower gate oxide film formed by thermally oxidizing the surface side of the polysilicon film, This weak spot can be terminated at the interface with the upper gate oxide film, so that the weak spot can be almost completely prevented from being formed on the entire gate oxide film.

【0006】[0006]

【実施例】図1はこの発明の一実施例を適用した電界効
果型トランジスタの要部を示したものである。この電界
効果型トランジスタを製造する場合には、まず、ガラス
等からなる基板1の上面に620℃程度の温度下でLP
CVD法によりポリシリコン膜2を堆積する。次に、ポ
リシリコン膜2の表面側を1000〜1100℃程度の
温度雰囲気中で熱酸化すると、熱酸化されないポリシリ
コン膜2によって半導体薄膜3が形成されると共に、該
半導体薄膜3の表面にポリシリコン膜2の表面側を熱酸
化してなる酸化シリコンからなる下層ゲート酸化膜4が
形成される。この場合、下層ゲート酸化膜4の膜厚は9
00Å程度となるようにする。次に、下層ゲート酸化膜
4の表面にスパッタ法により酸化シリコンからなる上層
ゲート酸化膜5を300Å程度の厚さに堆積する。次
に、アニール処理を行うことにより、上層ゲート酸化膜
5を緻密化する。この状態では、下層ゲート酸化膜4と
上層ゲート酸化膜5とが構造的に互いに独立しているの
で、ポリシリコン膜2の表面側を熱酸化してなる下層ゲ
ート酸化膜4にポリシリコン膜2の表面の結晶粒界に起
因するウィークスポットが生じても、このウィークスポ
ットを上層ゲート酸化膜5との界面で終端させることが
でき、したがって全体に亘るゲート酸化膜にウィークス
ポットが生じるのをほぼ完全に防止することができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the essential parts of a field effect transistor to which an embodiment of the present invention is applied. When manufacturing this field effect transistor, first, LP is formed on the upper surface of the substrate 1 made of glass or the like at a temperature of about 620 ° C.
A polysilicon film 2 is deposited by the CVD method. Next, when the surface side of the polysilicon film 2 is thermally oxidized in an atmosphere at a temperature of about 1000 to 1100 ° C., a semiconductor thin film 3 is formed by the polysilicon film 2 which is not thermally oxidized, and a polysilicon film is formed on the surface of the semiconductor thin film 3. A lower gate oxide film 4 made of silicon oxide is formed by thermally oxidizing the surface side of the silicon film 2. In this case, the thickness of the lower gate oxide film 4 is 9
It should be about 00Å. Next, an upper gate oxide film 5 made of silicon oxide is deposited on the surface of the lower gate oxide film 4 by a sputtering method to a thickness of about 300 Å. Next, the upper gate oxide film 5 is densified by performing an annealing process. In this state, since the lower gate oxide film 4 and the upper gate oxide film 5 are structurally independent from each other, the polysilicon film 2 is formed on the lower gate oxide film 4 formed by thermally oxidizing the surface side of the polysilicon film 2. Even if a weak spot is generated due to a grain boundary on the surface of, the weak spot can be terminated at the interface with the upper gate oxide film 5, so that the weak spot is almost entirely generated in the gate oxide film. Can be completely prevented.

【0007】以下、図示していないが、半導体薄膜3の
チャネル領域に対応する部分の上層ゲート酸化膜5の上
面にポリシリコンからなるゲート電極をパターン形成
し、次いでゲート電極をマスクとしてイオン注入装置に
よりリンイオン等のイオンを注入することにより、ゲー
ト電極の両側における半導体薄膜3に不純物濃度の高い
ソース・ドレイン領域を形成し、次いでソース・ドレイ
ン領域に対応する部分の上層ゲート酸化膜5および下層
ゲート酸化膜4をエッチングしてコンタクトホールを形
成し、次いでコンタクトホールを介してソース・ドレイ
ン領域と接続されるアルミニウムからなるソース・ドレ
イン電極を上層ゲート酸化膜5の上面にパターン形成す
ると、本実施例の電界効果型トランジスタが製造され
る。
Although not shown in the drawings, a gate electrode made of polysilicon is patterned on the upper surface of the upper gate oxide film 5 corresponding to the channel region of the semiconductor thin film 3, and then the ion implantation apparatus is used with the gate electrode as a mask. By implanting ions such as phosphorous ions into the semiconductor thin film 3 on both sides of the gate electrode, the source / drain regions having a high impurity concentration are formed, and then the upper gate oxide film 5 and the lower gate corresponding to the source / drain regions are formed. The oxide film 4 is etched to form a contact hole, and then a source / drain electrode made of aluminum connected to the source / drain region through the contact hole is patterned on the upper surface of the upper gate oxide film 5. Field effect transistor is manufactured.

【0008】ところで、このようにして製造された本実
施例の電界効果型トランジスタ(以下、本実施例品とい
う)と熱酸化のみによる厚さが1200Å程度のゲート
酸化膜を備えた従来の電界効果型トランジスタ(以下、
従来品という)とを用意し、VG(ゲート電圧)−I
D(ドレイン電流)特性およびゲートリーク電流特性に
ついて実験を行ったところ、図2および図3に示すよう
な結果が得られた。すなわち、VG−ID特性について
は、図2に示すように、IDが1nA(1/109A)か
ら10nA(1/108A)に変化するときのVGの立上
り特性が実線で示す本実施例品の場合0.25Vである
のに対し、点線で示す従来品の場合0.6Vであり、本
実施例品の方が立上りが急俊である。したがって、従来
品と比較して、本実施例品のしきい値電圧を小さくする
ことができる。ゲートリーク電流特性については、図3
に示すように、最大許容ゲートリーク電流を10pA
(1/1011A)程度としたとき、実線で示す複数の本
実施例品の場合ゲート電圧を25V程度かけることがで
きるのに対し、点線で示す従来品の場合15V程度しか
かけることができない。したがって、従来品と比較し
て、本実施例品のゲートリーク電流を小さくすることが
できる。
By the way, the field effect transistor of the present embodiment manufactured in this way (hereinafter referred to as the product of this embodiment) and the conventional field effect having a gate oxide film having a thickness of about 1200 Å only by thermal oxidation. Type transistor (hereinafter,
Providing a conventional product called) and, V G (gate voltage) -I
When an experiment was conducted on the D (drain current) characteristic and the gate leakage current characteristic, the results shown in FIGS. 2 and 3 were obtained. That is, for the V G -I D characteristic, as shown in FIG. 2, the rising characteristics of V G when I D changes from 1nA (1/10 9 A) to 10nA (1/10 8 A) solid Is 0.25 V in the case of the product of the present example shown by, whereas it is 0.6 V in the case of the conventional product shown by the dotted line, and the product of the present example has a quicker rise. Therefore, the threshold voltage of the product of this embodiment can be made smaller than that of the conventional product. For the gate leakage current characteristics, see FIG.
The maximum allowable gate leakage current is 10 pA
When it is set to about (1/10 11 A), the gate voltage of about 25 V can be applied in the case of the plurality of products of the present embodiment shown by the solid line, whereas only about 15 V can be applied in the case of the conventional product shown by the dotted line. . Therefore, the gate leakage current of the product of this embodiment can be reduced as compared with the conventional product.

【0009】[0009]

【発明の効果】以上説明したように、この発明によれ
ば、基板上に堆積されたポリシリコン膜の表面側を熱酸
化してなる下層ゲート酸化膜上に上層ゲート酸化膜を堆
積しているので、下層ゲート酸化膜と上層ゲート酸化膜
とが構造的に互いに独立したものとなり、ポリシリコン
膜の表面側を熱酸化してなる下層ゲート酸化膜にポリシ
リコン膜の表面の結晶粒界に起因するウィークスポット
が生じても、このウィークスポットを上層ゲート酸化膜
との界面で終端させることができ、したがって全体に亘
るゲート酸化膜にウィークスポットが生じるのをほぼ完
全に防止することができ、ひいてはしきい値電圧を小さ
くすることができ、またゲートリーク電流を小さくする
ことができる。
As described above, according to the present invention, the upper gate oxide film is deposited on the lower gate oxide film formed by thermally oxidizing the surface side of the polysilicon film deposited on the substrate. Therefore, the lower gate oxide film and the upper gate oxide film are structurally independent from each other, and the lower gate oxide film formed by thermally oxidizing the surface side of the polysilicon film is caused by the grain boundary of the surface of the polysilicon film. Even if a weak spot occurs, the weak spot can be terminated at the interface with the upper gate oxide film, and thus it is possible to almost completely prevent the weak spot from being formed in the entire gate oxide film. The threshold voltage can be reduced and the gate leakage current can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を適用した電界効果型トラ
ンジスタの要部の断面図。
FIG. 1 is a sectional view of a main part of a field effect transistor to which an embodiment of the present invention is applied.

【図2】この電界効果型トランジスタと従来の電界効果
型トランジスタのVG−ID特性を示す図。
FIG. 2 shows the V G -I D characteristic of the field effect transistor and a conventional field effect transistor.

【図3】この電界効果型トランジスタと従来の電界効果
型トランジスタのゲートリーク電流特性を示す図。
FIG. 3 is a diagram showing gate leakage current characteristics of this field effect transistor and a conventional field effect transistor.

【符号の説明】[Explanation of symbols]

1 基板 2 ポリシリコン膜 3 半導体薄膜 4 下層ゲート酸化膜 5 上層ゲート酸化膜 1 substrate 2 Polysilicon film 3 Semiconductor thin film 4 Lower gate oxide film 5 Upper gate oxide film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板上に堆積されたポリシリコン膜の表
面側を熱酸化することにより、熱酸化されない前記ポリ
シリコン膜によって半導体薄膜を形成すると共に、該半
導体薄膜の表面に酸化シリコンからなる下層ゲート酸化
膜を形成し、該下層ゲート酸化膜の表面に酸化シリコン
からなる上層ゲート酸化膜を堆積することを特徴とする
ゲート酸化膜の形成方法。
1. A surface layer of a polysilicon film deposited on a substrate is thermally oxidized to form a semiconductor thin film by the polysilicon film which is not thermally oxidized, and a lower layer made of silicon oxide is formed on the surface of the semiconductor thin film. A method for forming a gate oxide film, which comprises forming a gate oxide film and depositing an upper gate oxide film made of silicon oxide on the surface of the lower gate oxide film.
【請求項2】 前記上層ゲート酸化膜はスパッタ法によ
り堆積することを特徴とする請求項1記載のゲート酸化
膜の形成方法。
2. The method for forming a gate oxide film according to claim 1, wherein the upper gate oxide film is deposited by a sputtering method.
【請求項3】 前記上層ゲート酸化膜を堆積した後アニ
ール処理を行うことを特徴とする請求項1記載のゲート
酸化膜の形成方法。
3. The method for forming a gate oxide film according to claim 1, wherein an annealing process is performed after depositing the upper gate oxide film.
【請求項4】 請求項1記載の方法によって形成された
ゲート酸化膜を備えていることを特徴とする電界効果型
トランジスタ。
4. A field-effect transistor comprising a gate oxide film formed by the method according to claim 1.
JP3201193A 1991-07-17 1991-07-17 Method for forming gate oxide film and field effect transistor Pending JPH0529625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3201193A JPH0529625A (en) 1991-07-17 1991-07-17 Method for forming gate oxide film and field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3201193A JPH0529625A (en) 1991-07-17 1991-07-17 Method for forming gate oxide film and field effect transistor

Publications (1)

Publication Number Publication Date
JPH0529625A true JPH0529625A (en) 1993-02-05

Family

ID=16436891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3201193A Pending JPH0529625A (en) 1991-07-17 1991-07-17 Method for forming gate oxide film and field effect transistor

Country Status (1)

Country Link
JP (1) JPH0529625A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851277B2 (en) 2006-12-05 2010-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851277B2 (en) 2006-12-05 2010-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing same
US8283669B2 (en) 2006-12-05 2012-10-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing same

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