JPH0529522A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0529522A JPH0529522A JP20481591A JP20481591A JPH0529522A JP H0529522 A JPH0529522 A JP H0529522A JP 20481591 A JP20481591 A JP 20481591A JP 20481591 A JP20481591 A JP 20481591A JP H0529522 A JPH0529522 A JP H0529522A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit device
- lead
- socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
- H05K3/308—Adaptations of leads
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、混成集積回路装置の
リードに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead of a hybrid integrated circuit device.
【0002】[0002]
【従来の技術】図2は従来の混成集積回路装置を示すも
ので、図において、1は混成集積回路装置であり、2は
この混成集積回路装置1上に設けられたリードパッド、
3はこのリードパッド2に取付けられた挿入型リードで
ある。2. Description of the Related Art FIG. 2 shows a conventional hybrid integrated circuit device, in which 1 is a hybrid integrated circuit device and 2 is a lead pad provided on the hybrid integrated circuit device 1.
Reference numeral 3 is an insertion type lead attached to the lead pad 2.
【0003】次に動作について説明する。以上のように
リードパッド2に取付けられている挿入型リード3を、
ソケットあるいはスルーホール板に挿入することで、実
動作若しくは機能検査を行う。Next, the operation will be described. The insertion type lead 3 attached to the lead pad 2 as described above is
By inserting into a socket or through-hole plate, actual operation or function inspection is performed.
【0004】[0004]
【発明が解決しようとする課題】従来の混成集積回路装
置の挿入型リードの形状では、被測定物を挿入するソケ
ットの接触抵抗や、そのソケットと外部測定機器との間
に設けられた配線の抵抗分の影響で、電流経路において
は、電圧降下により、測定誤差を生じるという問題点が
あった。In the shape of the insertion type lead of the conventional hybrid integrated circuit device, the contact resistance of the socket into which the object to be measured is inserted and the wiring provided between the socket and the external measuring device are not provided. There is a problem that a measurement error occurs due to a voltage drop in the current path due to the influence of the resistance component.
【0005】この発明は上記のような問題点を解消する
ためになされたもので、電流経路内におけるソケットの
接触抵抗や配線抵抗が起因する電圧降下の影響をなくし
たテスト実施が可能な混成集積回路装置を得ることを目
的とする。The present invention has been made in order to solve the above problems, and it is a hybrid integrated system capable of performing a test without the influence of a voltage drop caused by a contact resistance of a socket or a wiring resistance in a current path. The purpose is to obtain a circuit device.
【0006】[0006]
【課題を解決するための手段】この発明に係る混成集積
回路装置は、ソケットの接触抵抗や配線抵抗による電圧
降下を補正出来る様に、センスラインとフォースライン
のケルビンポイントを出来るだけ被測定物に近づけるた
め、リードの形状を二股とし、それぞれをセンスピン、
フォースピンとしたものである。In the hybrid integrated circuit device according to the present invention, the Kelvin points of the sense line and the force line are set to the object to be measured as much as possible so that the voltage drop due to the contact resistance of the socket and the wiring resistance can be corrected. In order to bring them closer to each other, the shape of the lead is bifurcated, each of which is a sense pin,
It is a four-spin.
【0007】[0007]
【作用】この発明における混成集積回路装置は、リード
の形状を二股とし、それぞれをセンスピン、フォースピ
ンとした事により、電流経路内のソケットの接触抵抗
や、配線抵抗による電圧降下を補正することが出来る。In the hybrid integrated circuit device according to the present invention, the leads are bifurcated, and the leads are the sense pins and the force pins, so that the contact resistance of the socket in the current path and the voltage drop due to the wiring resistance can be corrected. .
【0008】[0008]
【実施例】以下、この発明の一実施例を図について説明
する。図1において、1は混成集積回路装置、2はリー
ドパットであり、このリードパット2には二股の形状と
なった挿入型リード4が取付けられている。そしてこの
二股挿入型リード4のそれぞれをセンスピン、フォース
ピンとし、被測定物上のリードパッド部で、センス、フ
ォーラインがケルビンとなる様な構成となる。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a hybrid integrated circuit device, 2 is a lead pad, and a bifurcated insertion type lead 4 is attached to the lead pad 2. Then, each of the bifurcated insertion type leads 4 is used as a sense pin and a force pin, and a sense pad and a force line are Kelvin in the lead pad portion on the object to be measured.
【0009】これをさらに詳しく説明すると、混成集積
回路装置1上に設けられたリードパッド2には、それぞ
れをセンスピン、フォースピンとした二股形状の二股挿
入型リード4が取付けられている。これは、電流経路内
のソケットの接触抵抗または配線抵抗による電圧降下を
補正できる様に、センスラインとフォースラインのケル
ビンポイントを、被測定物に出来る限り近づけるために
なされたものである。More specifically, the lead pad 2 provided on the hybrid integrated circuit device 1 is provided with a bifurcated bifurcated insertion type lead 4 having a sense pin and a force pin, respectively. This is done in order to bring the Kelvin points of the sense line and the force line as close as possible to the object to be measured so that the voltage drop due to the contact resistance or wiring resistance of the socket in the current path can be corrected.
【0010】[0010]
【発明の効果】以上のようにこの発明によれば、リード
形状を二股とし、それぞれをセンスピン、フォースピン
とする事により、ソケットの接触抵抗や配線抵抗による
電圧降下を補正する事が出来る。As described above, according to the present invention, it is possible to correct the voltage drop due to the contact resistance of the socket and the wiring resistance by making the lead shape bifurcated and forming the sense pin and the force pin, respectively.
【図1】この発明の一実施例による混成集積回路装置の
構成図である。FIG. 1 is a configuration diagram of a hybrid integrated circuit device according to an embodiment of the present invention.
【図2】従来の混成集積回路装置を示す構成図である。FIG. 2 is a configuration diagram showing a conventional hybrid integrated circuit device.
1 混成集積回路装置 2 リードパッド 4 二股状挿入型リード 1 hybrid integrated circuit device 2 lead pad 4 bifurcated insertion type lead
Claims (1)
において、上記リードの形状を2股とし、そのそれぞれ
をセンスピン、フォースピンに設定したことを特徴とす
る混成集積回路装置。Claim: What is claimed is: 1. A hybrid integrated circuit device having an insertion type lead, wherein the shape of the lead is bifurcated, and each of them is set to a sense pin and a force pin. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20481591A JPH0529522A (en) | 1991-07-19 | 1991-07-19 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20481591A JPH0529522A (en) | 1991-07-19 | 1991-07-19 | Hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0529522A true JPH0529522A (en) | 1993-02-05 |
Family
ID=16496840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20481591A Pending JPH0529522A (en) | 1991-07-19 | 1991-07-19 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0529522A (en) |
-
1991
- 1991-07-19 JP JP20481591A patent/JPH0529522A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH08271565A (en) | Method for inspecting connecting state of power supply apparatus and power supply apparatus using method thereof | |
JPH07146327A (en) | Method and apparatus for testing of integrated power device | |
JPH0529522A (en) | Hybrid integrated circuit device | |
JPH0245339B2 (en) | HANDOTAISHUSEKIKAIROSOCHI | |
JPH01129432A (en) | Integrated circuit | |
JP2952641B2 (en) | Test apparatus and test method for integrated circuit device | |
JPH08105935A (en) | Semiconductor integrated circuit inspection device | |
JPH04315062A (en) | Method for measuring resistance value of resistor | |
JPH03185744A (en) | Semiconductor element | |
JPH05251519A (en) | Tester for measuring semiconductor device | |
JPH01263572A (en) | Apparatus for testing semiconductor mounted substrate | |
JPH01210874A (en) | Inspecting method for semiconductor device | |
JPH07113850A (en) | Semiconductor integrated circuit | |
JPS62182677A (en) | Detection of defective insertion of integrated circuit into socket | |
JPH0574897A (en) | Semiconductor device tester | |
JPS6329273A (en) | Burn-in substrate | |
JPH0541419A (en) | Estimation method of test equipment | |
JPS6252948A (en) | Characteristics tester | |
JPH04302453A (en) | Semiconductor tester | |
JPH0480673A (en) | Level hold logic checker | |
JPH0795087B2 (en) | Semiconductor integrated circuit measuring device | |
JP2000133395A (en) | Ic measuring socket | |
JPH0736415B2 (en) | Wafer test equipment | |
JPH0513046U (en) | Semiconductor probe board inspection device | |
JPS6124249A (en) | Master slice system semiconductor integrated circuit device |