JPH0529471A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0529471A
JPH0529471A JP18605091A JP18605091A JPH0529471A JP H0529471 A JPH0529471 A JP H0529471A JP 18605091 A JP18605091 A JP 18605091A JP 18605091 A JP18605091 A JP 18605091A JP H0529471 A JPH0529471 A JP H0529471A
Authority
JP
Japan
Prior art keywords
film
etching
conductor film
contact hole
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18605091A
Other languages
Japanese (ja)
Inventor
Takahiro Maruyama
隆弘 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18605091A priority Critical patent/JPH0529471A/en
Publication of JPH0529471A publication Critical patent/JPH0529471A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve a controllability of an etching for forming a plug by a method wherein gas containing some one of at least F, Cl, Br and I is used as an etching means in the formation process of a buried conductor film. CONSTITUTION:Gas containing some one of at least F, Cl, Br and I is used as an etching means in the formation process of a buried conductor film. In the case an insulator film 2 is an oxide film like an SiO2 film, 0 atoms are eliminated from the SiO2 film by etching. Accordingly, as an etching using gas obtainable by adding a trace amount of O2 of 5% or thereabouts to HBr gas, for example, is reduced at a point of time when a polycrystalline silicon film 4a located at a part other than a contact hole 3 disappears by performing the etching, a possibility that even a plug 4 formed as the buried conductor film in the hole 3 is removed up by the etching as the etching rate is equal as the rate of that performed on the film 4a is dissolved and the control of the etching for forming the plug is facilitated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置の製造方
法に関し、さらに詳しくは、絶縁体膜に開口されたコン
タクトホールを通して上層と下層との各導電体膜の相互
間をプラグと呼ばれる中間導電体膜によって導通接続さ
せる場合、当該中間導電体膜の形成過程において、これ
を部分的にエッチングするためのエッチング方法の改良
に係るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an intermediate conductive layer called a plug between the upper and lower conductive layers through contact holes formed in the insulating layer. The present invention relates to an improvement in an etching method for partially etching the intermediate conductor film in the process of forming the intermediate conductor film when the conductive connection is made by the body film.

【0002】[0002]

【従来の技術】従来から、半導体装置の製造に際して
は、下層導電体膜を形成した後、当該下層導電体膜上を
絶縁体膜(層間絶縁膜)によって覆うと共に、その該当
部分にコンタクトホールを開口させておき、かつ当該コ
ンタクトホール内をプラグと呼ばれる中間導電体膜によ
り埋め込んだ上で、この中間導電体膜(以下,埋め込み
プラグと呼ぶ)を含む絶縁体膜上に上層導電体膜を形成
させ、これによって上層と下層との各導電体膜の相互間
を電気的に導通させるようにした配線形成手段,いわゆ
る多層配線構造の形成手段が採用されている。
2. Description of the Related Art Conventionally, in manufacturing a semiconductor device, after a lower conductor film is formed, the lower conductor film is covered with an insulating film (interlayer insulating film), and a contact hole is formed in the corresponding portion. An opening is made and the inside of the contact hole is filled with an intermediate conductor film called a plug, and then an upper conductor film is formed on an insulator film including this intermediate conductor film (hereinafter referred to as an embedded plug). Thus, a wiring forming means, that is, a so-called multi-layer wiring structure forming means for electrically connecting the upper and lower conductive films to each other is employed.

【0003】図2(a),(b),(c) には、従来から一般的に
行なわれているこの種の多層配線構造の形成手段の概要
を主要な工程順で模式的に示す。
2 (a), (b) and (c) schematically show, in the order of main steps, an outline of means for forming a multi-layer wiring structure of this type which has been conventionally generally performed.

【0004】すなわち、この一般的な多層配線構造の形
成方法においては、適宜,半導体基板上などに下層導電
体膜1を選択的に形成した後、当該下層導電体膜1上を
絶縁体膜2によって覆い、その該当部分,つまり、下層
導電体膜1に対する接続部分を含んだ所要部分にコンタ
クトホール3を開口させた状態において、まず、当該コ
ンタクトホール3内を埋め込み特性のよい導電材料,例
えば、CVD法による多結晶シリコン膜4aによって埋
め込む(同図2(a) 参照)。
That is, in this general method for forming a multilayer wiring structure, after the lower conductor film 1 is selectively formed on a semiconductor substrate or the like, the lower conductor film 1 is covered with the insulator film 2. In a state in which the contact hole 3 is covered with a contact hole 3 in a corresponding portion, that is, a required portion including a connection portion for the lower conductor film 1, the contact hole 3 is first filled with a conductive material having a good filling property, for example, It is filled with a polycrystalline silicon film 4a formed by the CVD method (see FIG. 2 (a)).

【0005】ついで、従来の場合には、前記埋め込まれ
た多結晶シリコン膜4aに対して、プラズマを用いたド
ライエッチング,通常では、例えば、SF6 のようなフッ
素系ガスによるエッチングを行なうことにより、コンタ
クトホール3内にのみ多結晶シリコン膜4aを残すよう
にエッチバックして、中間導電体膜としての埋め込みプ
ラグ4を形成させる(同図2(b) 参照)。
Then, in the conventional case, the buried polycrystalline silicon film 4a is dry-etched by using plasma, usually by a fluorine-based gas such as SF 6 , for example. Etching back is performed so as to leave the polycrystalline silicon film 4a only in the contact hole 3 to form a buried plug 4 as an intermediate conductor film (see FIG. 2 (b)).

【0006】その後、前記コンタクトホール3内の埋め
込みプラグ4を含む絶縁体膜2上にあって、上層導電体
膜5を選択的に形成させ(同図2(c) 参照)、このよう
にしてこれらの上層,下層の各導電体膜5,1の相互間
を埋め込みプラグ4の介在で電気的に導通接続させるこ
とにより、所期通りの多層配線構造を形成させるのであ
る。
After that, the upper conductor film 5 is selectively formed on the insulator film 2 including the buried plug 4 in the contact hole 3 (see FIG. 2 (c)). By electrically connecting the upper and lower conductor films 5 and 1 to each other with the interposition of the embedded plug 4, a desired multilayer wiring structure is formed.

【0007】従って、上記の各工程を経て形成される従
来の多層配線構造では、上層導電体膜5として、例え
ば、スパッタ膜などのように埋め込み特性の悪い導電材
料を用いた場合においても、コンタクトホール3内に予
め埋め込みプラグ4が形成されているために、当該コン
タクトホール3内における導電部分の被覆が良好になさ
れて、接続抵抗が低減され、かつ接続不良などを生ずる
惧れがない。
Therefore, in the conventional multi-layer wiring structure formed through the above steps, even when a conductive material having a poor filling property such as a sputtered film is used as the upper conductor film 5, a contact is formed. Since the buried plug 4 is formed in the hole 3 in advance, the conductive portion in the contact hole 3 is well covered, the connection resistance is reduced, and there is no fear that a connection failure will occur.

【0008】ちなみに、図3には、上記コンタクトホー
ル3内に予め埋め込みプラグ4を形成させずに、当該コ
ンタクトホール3内をスパッタ膜などのように埋め込み
特性の悪い導電材料で直接,埋め込んで、所要の上層導
電体膜5を形成させた場合を示してあるが、同図3から
明らかなように、この場合には、コンタクトホール3内
の内壁部,および底部に薄い膜部分を生じて、接続抵抗
が増加したり、あるいは、断線などの接続不良を生ずる
ことになる。
By the way, in FIG. 3, the contact plugs 3 are not directly formed with the embedded plugs 4 in advance, but the contact holes 3 are directly embedded with a conductive material having a poor embedding property such as a sputtered film. Although the case where the required upper conductor film 5 is formed is shown, as is clear from FIG. 3, in this case, a thin film portion is formed on the inner wall portion and the bottom portion in the contact hole 3, The connection resistance will increase, or a connection failure such as disconnection will occur.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、上記従
来の多層配線形成方法においては、コンタクトホール3
内に埋め込まれた多結晶シリコン膜4aのエッチバック
に際して、SF6 のようなフッ素系ガスを用いた等方性の
強いエッチングを行なっているために、次のような問題
点を生ずることになる。
However, in the above-mentioned conventional method of forming a multi-layer wiring, the contact hole 3 is formed.
In etching back the polycrystalline silicon film 4a embedded in the inside, since strong isotropic etching using a fluorine-based gas such as SF 6 is performed, the following problems occur. .

【0010】すなわち、当該フッ素系ガスによるエッチ
ングにおいては、一般的に、エッチング面積が狭いほど
エッチング速度が大きくなるという特長があるが、この
ために、コンタクトホール以外の部分で被エッチング膜
が除去,消失された場合、そのエッチング速度が増加し
て制御が困難になり、ときにはプラグ相当部分までが完
全に除去されてしまうものであった。
That is, in the etching with the fluorine-based gas, generally, the smaller the etching area is, the higher the etching rate is. However, for this reason, the film to be etched is removed in a portion other than the contact hole. If it is lost, the etching rate increases, making control difficult, and sometimes even the portion corresponding to the plug is completely removed.

【0011】この発明は、このような従来の問題点を解
消するためになされたもので、その目的とするところ
は、被エッチング膜に対するエッチング速度がエッチン
グ面積に依存せず、かつエッチング面積が狭いほど、エ
ッチング速度が遅くなるようにして、エッチング制御を
容易に行ない得るようにした,この種の半導体装置の製
造方法,こゝでは、半導体装置の製造における多層配線
構造の形成方法を提供することである。
The present invention has been made in order to solve such a conventional problem, and an object thereof is that the etching rate for the film to be etched does not depend on the etching area and the etching area is narrow. To provide a method for manufacturing a semiconductor device of this kind, in which the etching speed is slowed down so that etching can be easily controlled, and a method for forming a multilayer wiring structure in the manufacture of a semiconductor device. Is.

【0012】[0012]

【課題を解決するための手段】前記目的を達成するため
に、この発明に係る半導体装置の製造における多層配線
構造の形成方法は、プラグ形成時でのエッチング工程に
あって、絶縁体膜が O原子を含む場合には、少なくとも
F,Cl,Br,Iの何れかを含むガス系のエッチング手段を用
い、また、絶縁体膜が O原子を含むか、もしくは、含ま
ない場合には、少なくとも F,Cl,Br,Iの何れかを含むガ
スに所要量のO2を添加したガス系のエッチング手段を用
いるようにしたものである。
In order to achieve the above object, a method of forming a multi-layer wiring structure in the manufacture of a semiconductor device according to the present invention is characterized in that an insulating film is formed in an etching process during plug formation. If it contains atoms, at least
A gas-based etching means containing any of F, Cl, Br, and I is used, and if the insulator film contains O atoms or does not contain O atoms, at least one of F, Cl, Br, and I is used. A gas-based etching means in which a required amount of O 2 is added to a gas containing such is used.

【0013】すなわち、この発明の第1の発明は、下層
導電体膜上の O原子を含む絶縁体膜にコンタクトホール
を開口させた状態で、まず、前記コンタクトホール内を
含む絶縁体膜上に中間導電体膜を被覆させると共に、少
なくとも当該絶縁体膜上の中間導電体膜のみをエッチン
グ除去して、コンタクトホール内に埋め込み導電体膜を
残し、ついで、前記コンタクトホール内の埋め込み導電
体膜を含む絶縁体膜上に上層導電体膜を形成して、これ
らの上層,下層の各導電体膜の相互を埋め込み導電体膜
によって電気的に導通させるようにした多層配線構造の
形成方法において、前記埋め込み導電体膜の形成過程に
おけるエッチング手段として、少なくとも F,Cl,Br,Iの
何れかを含むガス系を用いることを特徴とする半導体装
置の製造方法である。
That is, according to the first aspect of the present invention, in the state in which a contact hole is opened in an insulating film containing O atoms on a lower conductive film, first, the insulating film including the inside of the contact hole is formed. While covering the intermediate conductor film, at least only the intermediate conductor film on the insulator film is removed by etching to leave the buried conductor film in the contact hole, and then the buried conductor film in the contact hole is removed. In the method of forming a multilayer wiring structure, an upper conductor film is formed on an insulating film including the upper conductor film and the upper conductor film and the lower conductor film are electrically connected by an embedded conductor film. In the method of manufacturing a semiconductor device, a gas system containing at least one of F, Cl, Br, and I is used as an etching means in the process of forming the buried conductor film.

【0014】また、この発明の第2の発明は、下層導電
体膜上の絶縁体膜にコンタクトホールを開口させた状態
で、まず、前記コンタクトホール内を含む絶縁体膜上に
中間導電体膜を被覆させると共に、少なくとも当該絶縁
体膜上の中間導電体膜のみをエッチング除去して、コン
タクトホール内に埋め込み導電体膜を残し、ついで、前
記コンタクトホール内の埋め込み導電体膜を含む絶縁体
膜上に上層導電体膜を形成して、これらの上層,下層の
各導電体膜の相互を埋め込み導電体膜によって電気的に
導通させるようにした多層配線構造の形成方法におい
て、前記埋め込み導電体膜の形成過程におけるエッチン
グ手段として、少なくとも F,Cl,Br,Iの何れかを含むガ
スに所要量のO2を添加したガス系を用いることを特徴と
する半導体装置の製造方法である。
According to a second aspect of the present invention, the contact hole is opened in the insulator film on the lower conductor film, and the intermediate conductor film is first formed on the insulator film including the inside of the contact hole. And at least only the intermediate conductor film on the insulator film is removed by etching to leave the buried conductor film in the contact hole, and then the insulator film including the buried conductor film in the contact hole. A method of forming a multilayer wiring structure, wherein an upper conductor film is formed on the upper conductor film and the upper conductor film and the lower conductor film are electrically connected to each other by the buried conductor film. A method for manufacturing a semiconductor device, characterized in that a gas system in which a required amount of O 2 is added to a gas containing at least one of F, Cl, Br, and I is used as an etching means in the formation process of Is the law.

【0015】[0015]

【作用】従って、この発明の第1の発明では、エッチン
グの進行に伴って酸素原子を含む絶縁体膜が露出される
と、少なくとも F,Cl,Br,Iの何れかを含むエッチングガ
スに、当該露出された絶縁体膜から排出される O原子が
添加されて、中間導電体膜のエッチング速度を低下させ
ることができ、埋め込み導電体膜を制御性よく形成し得
る。
Therefore, in the first aspect of the present invention, when the insulator film containing oxygen atoms is exposed as the etching progresses, the etching gas containing at least one of F, Cl, Br and I O atoms discharged from the exposed insulator film can be added to reduce the etching rate of the intermediate conductor film, and the buried conductor film can be formed with good controllability.

【0016】また、この発明の第2の発明では、エッチ
ング手段に、少なくとも F,Cl,Br,Iの何れかを含むガス
に所要量のO2を添加したガス系を用いており、 O原子を
含む絶縁体膜の場合、当該絶縁体膜が露出された時点
で、排出される O原子がエッチングガス中へさらに添加
されて、中間導電体膜のエッチング速度を低下でき、か
つ O原子を含まない絶縁体膜の場合には、エッチングの
当初から同様に中間導電体膜のエッチング速度が低下さ
れているために、埋め込み導電体膜を制御性よく形成し
得る。
Further, in the second aspect of the present invention, a gas system in which a required amount of O 2 is added to a gas containing at least one of F, Cl, Br and I is used as the etching means. In the case of an insulating film containing, when the insulating film is exposed, the discharged O atom is further added to the etching gas to reduce the etching rate of the intermediate conductor film and to contain the O atom. In the case of a non-insulating film, the embedded conductive film can be formed with good controllability since the etching rate of the intermediate conductive film is reduced from the beginning of etching as well.

【0017】[0017]

【実施例】以下,この発明に係る半導体装置の製造方
法,こゝでは、半導体装置の製造における多層配線構造
の形成方法の実施例につき、図1,および図2を参照し
て詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention, hereunder, an embodiment of a method of forming a multi-layer wiring structure in the manufacture of a semiconductor device will be described in detail with reference to FIGS. .

【0018】この発明の一実施例方法においては、前記
図2(a) 工程後の同(b) 工程におけるエッチングに際し
て、HBr ガスにO2を添加したガス系を用いることで多結
晶シリコン膜4aをエッチバックし、その後、同(c) 工
程を経て、同様に多層配線構造を形成するのである。
In the method of one embodiment of the present invention, the polycrystalline silicon film 4a is formed by using a gas system in which O 2 is added to HBr gas during the etching in the step (b) after the step in FIG. 2 (a). Then, the multilayer wiring structure is similarly formed through the step (c) of etching back.

【0019】図1には、この発明の一実施例方法として
の,HBr ガスにO2を添加したガス系のエッチング手段を
用いた場合の多結晶シリコンにおけるエッチング速度の
O2添加量依存性をグラフによって示してある。
FIG. 1 shows the etching rate in polycrystalline silicon when a gas-based etching means in which O 2 is added to HBr gas is used as a method of one embodiment of the present invention.
The graph shows the dependence of O 2 addition amount.

【0020】すなわち、この図1からも明らかなよう
に、HBr ガスに対してO2を5%以上添加した場合には、そ
のエッチング速度が急激に低下し、10% 以上の添加で
は、エッチングが殆んど進行しないことが判る。
That is, as is apparent from FIG. 1, when O 2 is added to HBr gas in an amount of 5% or more, the etching rate sharply decreases. It turns out that it hardly progresses.

【0021】こゝで、前記図2(b) 工程での絶縁体膜2
が、例えば、SiO2膜のような酸化物膜である場合には、
エッチング中に当該SiO2膜から O原子が排出されること
になる。そして、このために、前記のようにHBr ガスに
5%程度のO2を添加した条件のガス系を用いて多結晶シリ
コン膜4aをエッチバックするときは、エッチングの進
行に伴い、コンタクトホール3以外の部分の多結晶シリ
コン膜4aが除去,消失されて、絶縁体膜2としてのSi
O2膜が露出された時点で、当該SiO2膜から O原子が排出
されるため、結果的に、その後の多結晶シリコン膜4a
に対するエッチング速度が低下される。
Here, the insulator film 2 in the step of FIG. 2 (b) is used.
Is, for example, an oxide film such as a SiO 2 film,
O atoms are discharged from the SiO 2 film during etching. And, for this reason, as described above, HBr gas is added.
When the polycrystalline silicon film 4a is etched back using a gas system to which about 5% O 2 is added, the polycrystalline silicon film 4a other than the contact holes 3 is removed and disappears as the etching progresses. And Si as the insulator film 2
At the time when the O 2 film is exposed, O atoms are ejected from the SiO 2 film, and as a result, the subsequent polycrystalline silicon film 4a is removed.
The etching rate is reduced.

【0022】従って、このようにHBr ガスに5%程度の微
量のO2を添加したガス系を用いたエッチングを行なうこ
とにより、コンタクトホール3以外の部分の多結晶シリ
コン膜4aが消失した時点で、エッチング速度が低下す
るために、従来方法でのように、コンタクトホール3内
での埋め込み導電体膜としてのプラグ4までが、同等の
速度のまゝでエッチング除去されて了う惧れが解消され
て、そのエッチング制御が容易になる。
Therefore, by performing the etching using the gas system in which the trace amount of O 2 is added to the HBr gas as described above, when the polycrystalline silicon film 4a other than the contact hole 3 disappears. Since the etching rate is reduced, there is no fear that the plug 4 as the embedded conductor film in the contact hole 3 is etched and removed at the same speed as in the conventional method. This facilitates the etching control.

【0023】なお、前記実施例方法においては、埋め込
みプラグを形成するためのエッチングガスとして、HBr
ガスにO2を添加したガス系を用いる場合について述べた
が、実質的に、F,Cl,Br,I を含むガスにO2を添加したガ
ス系を用いる場合にも同様な作用,効果が得られる。
In the method of the above embodiment, HBr is used as the etching gas for forming the buried plug.
Although the case where the gas system in which O 2 is added to the gas is used has been described, substantially the same action and effect are obtained when the gas system in which O 2 is added to the gas containing F, Cl, Br, I is used. can get.

【0024】また、前記実施例方法では、プラグを形成
する導電体膜として、これが多結晶シリコン膜である場
合について述べたが、W,Tiなどの金属膜であるとか、あ
るいは、WSix,TiSixなどのような金属のシリコン化合物
であってもよいことは勿論である。
In the method of the above-described embodiment, the case where the conductor film forming the plug is a polycrystalline silicon film has been described. However, it may be a metal film of W, Ti or the like, or WSi x , TiSi. Of course, it may be a metal silicon compound such as x .

【0025】さらに、酸化物系絶縁体膜を有する場合で
のエッチング条件によっては、O2の添加量をより少なく
しても、ないしは、たとえO2を添加しなくても、当該酸
化物系絶縁体膜からの O原子の供給によって所要の作
用,効果が得られる。
Further, depending on the etching conditions in the case of having an oxide-based insulating film, even if the amount of O 2 added is reduced, or even if O 2 is not added, the oxide-based insulating film By supplying O atoms from the body membrane, the required actions and effects can be obtained.

【0026】[0026]

【発明の効果】以上、実施例によって詳述したように、
この発明の第1の発明方法によれば、下層導電体膜上の
O原子を含む絶縁体膜にコンタクトホールを開口させ
て、このコンタクトホール内を含む絶縁体膜上に中間導
電体膜を被覆させ、かつ少なくとも絶縁体膜上の中間導
電体膜のみをエッチング除去して、コンタクトホール内
に埋め込み導電体膜を残し、さらに、コンタクトホール
内の埋め込み導電体膜を含む絶縁体膜上に上層導電体膜
を形成して、これらの上層,下層の各導電体膜の相互を
埋め込み導電体膜によって電気的に導通させるようにし
た多層配線構造の形成方法において、埋め込み導電体膜
の形成過程におけるエッチング手段として、少なくとも
F,Cl,Br,Iの何れかを含むガス系を用いるようにしたか
ら、エッチングの進行に伴い、 O原子を含む絶縁体膜が
露出された時点で、そのエッチングガスに、絶縁体膜か
ら排出される O原子が添加されることになり、この結
果,中間導電体膜のエッチング速度が低下されて、所要
の埋め込み導電体膜を極めて簡単に制御性よく形成し得
る。
As described above in detail with reference to the embodiments,
According to the first invention method of the present invention, on the lower conductor film
A contact hole is opened in the insulator film containing O atoms, the intermediate conductor film is covered on the insulator film including the inside of the contact hole, and at least only the intermediate conductor film on the insulator film is removed by etching. The buried conductor film is left in the contact hole, and an upper conductor film is formed on the insulator film including the buried conductor film in the contact hole. In a method of forming a multi-layer wiring structure in which mutual conduction is made by a buried conductor film, at least as an etching means in the process of forming the buried conductor film,
Since a gas system containing any of F, Cl, Br, and I was used, when the insulator film containing O atoms was exposed as the etching progressed, the insulator film was exposed to the etching gas. The discharged O atoms are added, and as a result, the etching rate of the intermediate conductor film is reduced, and the required buried conductor film can be formed extremely easily and with good controllability.

【0027】また、この発明の第2の発明によれば、前
記の多層配線構造の形成方法において、エッチング手段
に、少なくとも F,Cl,Br,Iの何れかを含むガスに所要量
のO2を添加したガス系を用いているために、O原子を含
む絶縁体膜の場合、この絶縁体膜が露出された時点で、
排出される O原子がエッチングガス中へさらに添加され
て、中間導電体膜のエッチング速度が低下され、かつ O
原子を含まない絶縁体膜の場合には、エッチングの当初
から中間導電体膜のエッチング速度が低下されることに
なって、同様に、所要の埋め込み導電体膜を極めて簡単
に制御性よく形成し得るのである。
Further, according to the second invention of the present invention, in the above-mentioned method for forming a multilayer wiring structure, a gas containing at least any one of F, Cl, Br and I is used as the etching means, and a required amount of O 2 is used. In the case of an insulator film containing O atoms, since a gas system added with is used, when this insulator film is exposed,
The discharged O atoms are further added to the etching gas to reduce the etching rate of the intermediate conductor film, and
In the case of an insulator film that does not contain atoms, the etching rate of the intermediate conductor film is reduced from the beginning of etching, and similarly, the required embedded conductor film can be formed very easily and with good controllability. To get.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例方法によるHBr ガスにO2
添加したガス系のエッチング手段を用いた場合の多結晶
シリコンにおけるエッチング速度のO2添加量依存性を示
すグラフである。
FIG. 1 is a graph showing the dependence of the etching rate of polycrystalline silicon on the amount of added O 2 when a gas-based etching means in which O 2 is added to HBr gas according to an embodiment method of the present invention is used.

【図2】この発明の一実施例方法,および従来方法を含
む一般的な多層配線構造の形成方法の概要を主要な工程
順で模式的に示すそれぞれに断面図である。
2A to 2D are cross-sectional views schematically showing an outline of a general method of forming a multilayer wiring structure including an embodiment method of the present invention and a conventional method in the order of main steps.

【図3】従来方法でのコンタクトホール内をプラグによ
って埋め込まずに形成した多層配線構造の概要構成を模
式的に示す断面図である。
FIG. 3 is a cross-sectional view schematically showing a schematic configuration of a multilayer wiring structure formed by a conventional method without filling a contact hole with a plug.

【符号の説明】[Explanation of symbols]

1 下層導電体膜 2 絶縁体膜 3 コンタクトホール 4a 多結晶シリコン膜 4 埋め込みプラグ(埋め込み中間導電体膜) 5 上層導電体膜 1 Lower conductor film 2 Insulator film 3 contact holes 4a Polycrystalline silicon film 4 Embedded plug (embedded intermediate conductor film) 5 Upper conductor film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 下層導電体膜上の O原子を含む絶縁体膜
にコンタクトホールを開口させた状態で、まず、前記コ
ンタクトホール内を含む絶縁体膜上に中間導電体膜を被
覆させると共に、少なくとも当該絶縁体膜上の中間導電
体膜のみをエッチング除去して、コンタクトホール内に
埋め込み導電体膜を残し、ついで、前記コンタクトホー
ル内の埋め込み導電体膜を含む絶縁体膜上に上層導電体
膜を形成して、これらの上層,下層の各導電体膜の相互
を埋め込み導電体膜により電気的に導通させるようにし
た多層配線構造の形成方法において、 前記埋め込み導電体膜の形成過程におけるエッチング手
段として、少なくともF,Cl,Br,Iの何れかを含むガス系
を用いることを特徴とする半導体装置の製造方法。
1. In a state in which a contact hole is opened in an insulating film containing O atoms on a lower conductive film, first, an intermediate conductive film is coated on the insulating film including the inside of the contact hole, and At least only the intermediate conductor film on the insulator film is removed by etching to leave the buried conductor film in the contact hole, and then the upper conductor on the insulator film including the buried conductor film in the contact hole. In a method of forming a multilayer wiring structure in which a film is formed so that the upper and lower conductor films are electrically connected to each other by a buried conductor film, the etching in the process of forming the buried conductor film is performed. A method of manufacturing a semiconductor device, characterized in that a gas system containing at least one of F, Cl, Br, and I is used as a means.
【請求項2】 下層導電体膜上の絶縁体膜にコンタクト
ホールを開口させた状態で、まず、前記コンタクトホー
ル内を含む絶縁体膜上に中間導電体膜を被覆させると共
に、少なくとも当該絶縁体膜上の中間導電体膜のみをエ
ッチング除去して、コンタクトホール内に埋め込み導電
体膜を残し、ついで、前記コンタクトホール内の埋め込
み導電体膜を含む絶縁体膜上に上層導電体膜を形成し
て、これらの上層,下層の各導電体膜の相互を埋め込み
導電体膜により電気的に導通させるようにした多層配線
構造の形成方法において、 前記埋め込み導電体膜の形成過程におけるエッチング手
段として、少なくともF,Cl,Br,Iの何れかを含むガスに
所要量のO2を添加したガス系を用いることを特徴とする
半導体装置の製造方法。
2. In a state where a contact hole is opened in an insulating film on a lower conductive film, first, an insulating film including the inside of the contact hole is covered with an intermediate conductive film, and at least the insulating film is formed. Only the intermediate conductor film on the film is removed by etching to leave the buried conductor film in the contact hole, and then the upper conductor film is formed on the insulator film including the buried conductor film in the contact hole. In the method of forming a multi-layer wiring structure in which the upper and lower conductor films are electrically connected to each other by the buried conductor film, at least as an etching means in the process of forming the buried conductor film, A method for manufacturing a semiconductor device, which uses a gas system in which a required amount of O 2 is added to a gas containing any one of F, Cl, Br, and I.
JP18605091A 1991-07-25 1991-07-25 Manufacture of semiconductor device Pending JPH0529471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18605091A JPH0529471A (en) 1991-07-25 1991-07-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18605091A JPH0529471A (en) 1991-07-25 1991-07-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0529471A true JPH0529471A (en) 1993-02-05

Family

ID=16181525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18605091A Pending JPH0529471A (en) 1991-07-25 1991-07-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0529471A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130711A (en) * 1993-11-02 1995-05-19 Nec Corp Manufacture of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55111134A (en) * 1979-02-19 1980-08-27 Mitsubishi Electric Corp Method of gas plasma etching
JPS62174920A (en) * 1986-01-29 1987-07-31 Hitachi Ltd Etching method
JPH0289310A (en) * 1988-09-27 1990-03-29 Fujitsu Ltd Etching of silicon layer
JPH03141641A (en) * 1989-10-26 1991-06-17 Sony Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55111134A (en) * 1979-02-19 1980-08-27 Mitsubishi Electric Corp Method of gas plasma etching
JPS62174920A (en) * 1986-01-29 1987-07-31 Hitachi Ltd Etching method
JPH0289310A (en) * 1988-09-27 1990-03-29 Fujitsu Ltd Etching of silicon layer
JPH03141641A (en) * 1989-10-26 1991-06-17 Sony Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130711A (en) * 1993-11-02 1995-05-19 Nec Corp Manufacture of semiconductor device

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