JPH0529319A - Manufacture of thin-film integrated circuit - Google Patents
Manufacture of thin-film integrated circuitInfo
- Publication number
- JPH0529319A JPH0529319A JP18278691A JP18278691A JPH0529319A JP H0529319 A JPH0529319 A JP H0529319A JP 18278691 A JP18278691 A JP 18278691A JP 18278691 A JP18278691 A JP 18278691A JP H0529319 A JPH0529319 A JP H0529319A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sputtering method
- aluminum
- thin
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は薄膜集積回路の製造方法
に関し、特にタンタル膜上に形成する配線およびボンデ
ィングパッド用のアルミニウム膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film integrated circuit, and more particularly to a method for forming an aluminum film for wiring and bonding pads formed on a tantalum film.
【0002】[0002]
【従来の技術】従来の薄膜集積回路の薄膜抵抗素子の形
成方法は、次のように行なわれていた。まずシリコン基
板上に熱酸化によりSiO2 膜を形成し、その上に窒素
ドープタンタル(Ta2 N)膜を形成し、この上部にシ
リコンを含むアルミニウム(Al−Si)膜と純アルミ
ニウム(Al)膜からなる導体膜を直流スパッタ法によ
り順次付着形成する。この導体膜をスパッタリングする
場合、パターン形成時のレジスト密着性や組立時のワイ
ヤーボンディング等の密着性が十分に得られるように、
スパッタ時の温度やスパッタレートを選択してスパッタ
リングすることにより所望の導体膜を得ていた。尚、通
常、導体膜のスパッタは、高周波スパッタ法より膜厚分
布が安定して得られる直流スパッタ法を用い、かつ、ス
パッタ中は、基板温度を一定に保つことが一般的であ
る。2. Description of the Related Art A conventional method of forming a thin film resistance element of a thin film integrated circuit has been performed as follows. First, a SiO 2 film is formed on a silicon substrate by thermal oxidation, a nitrogen-doped tantalum (Ta 2 N) film is formed thereon, and an aluminum (Al—Si) film containing silicon and a pure aluminum (Al) film are formed on the SiO 2 film. A conductive film made of a film is sequentially deposited by the DC sputtering method. When sputtering this conductor film, in order to obtain sufficient adhesiveness such as resist adhesion during pattern formation and wire bonding during assembly,
A desired conductor film was obtained by selecting the temperature during sputtering and the sputtering rate. In general, the conductor film is sputtered by a direct current sputter method, which provides a more stable film thickness distribution than the high frequency sputter method, and the substrate temperature is generally kept constant during the sputter.
【0003】しかる後、Ta2 N膜と導体膜とをパター
ニングし、Ta2 N膜からなる薄膜低抗体と導体膜から
なる配線およびパッドを形成する。次で薄膜抵抗素子の
経時的安定性及び薄膜低抗体とパッドとの密着強度を得
るため、大気中で250〜450℃程度の熱処理を行
う。Thereafter, the Ta 2 N film and the conductor film are patterned to form a thin film low antibody made of the Ta 2 N film and wirings and pads made of the conductor film. Next, in order to obtain stability over time of the thin film resistance element and adhesion strength between the thin film low antibody and the pad, heat treatment is performed at about 250 to 450 ° C. in the atmosphere.
【0004】このように従来の薄膜抵抗素子における配
線およびパッド用の導体膜は、Al−Si膜とAl膜と
の2層構造となっていた。このAl膜は、導体層の最上
部を構成し、ボンディング強度を高めるために設けられ
ている。また、Ta2 N膜上部のAl−Si膜は、Al
−Si膜中のSiとTaによる相互拡散により、Ta2
N膜及びAl−Si膜とAl膜を交互に密着させ、Al
配線におけるボイド,ホイスカ等のエレクトロマイグレ
ーションを防止するために設けられている。As described above, the conductor film for wiring and pad in the conventional thin film resistance element has a two-layer structure of an Al-Si film and an Al film. This Al film constitutes the uppermost part of the conductor layer and is provided to enhance the bonding strength. In addition, the Al-Si film on the Ta 2 N film is
-By mutual diffusion of Si and Ta in the Si film, Ta 2
The N film and the Al-Si film and the Al film are alternately adhered to each other to form an Al film.
It is provided to prevent electromigration such as voids and whiskers in the wiring.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の薄膜抵抗素子等を構成するTa2 N膜上の導体
膜においては、Al−Si膜中のSiとTaとの相互拡
散が、Al−Si膜及びAl膜からなる導体膜形成時に
おける基板温度に依存しやすいため、このときの基板温
度が高くなると、Ta2 N膜へのSiの拡散量が多くな
る。このため、抵抗パターン及び導体パターンを形成す
る際に、Ta2 N膜表面からSiを除去することができ
ないため、外観不良及び特性不良を生ずるという欠点が
ある。However, in the conductor film on the Ta 2 N film constituting the above-mentioned conventional thin film resistance element or the like, the interdiffusion between Si and Ta in the Al-Si film is caused by Al- Since the temperature tends to depend on the substrate temperature at the time of forming the conductor film made of the Si film and the Al film, the amount of Si diffused into the Ta 2 N film increases as the substrate temperature at this time increases. Therefore, when the resistance pattern and the conductor pattern are formed, Si cannot be removed from the surface of the Ta 2 N film, so that there is a drawback that a defective appearance and a defective characteristic occur.
【0006】一方、この問題を回避するため従来は、A
l−Si膜及びAl膜のスパッタリング時の基板温度
を、通常の場合より低温度にしているため、最上部のA
l膜表面が硬くなり、ボンディング強度のばらつきが大
きくなるという問題点があった。On the other hand, in order to avoid this problem, conventionally, A
Since the substrate temperature at the time of sputtering the l-Si film and the Al film is set to a lower temperature than usual, the uppermost A
There is a problem that the surface of the l-film becomes hard and the variation in bonding strength becomes large.
【0007】[0007]
【課題を解決するための手段】本発明の薄膜集積回路の
製造方法は、シリコン基板上に酸化膜を介してタンタル
膜を形成したのち、このタンタル膜上に配線およびボン
ディングパッド用の不純物を含む第1のアルミニウム膜
と不純物を含まない第2のアルミニウム膜とを順次形成
する薄膜集積回路の製造方法において、第1のアルミニ
ウム膜を直流スパッタ法で形成し、第2のアルミニウム
膜を高周波スパッタ法で形成するものである。According to a method of manufacturing a thin film integrated circuit of the present invention, a tantalum film is formed on a silicon substrate via an oxide film, and then impurities for wiring and bonding pads are contained on the tantalum film. In a method of manufacturing a thin film integrated circuit in which a first aluminum film and a second aluminum film containing no impurities are sequentially formed, the first aluminum film is formed by a DC sputtering method, and the second aluminum film is formed by a high frequency sputtering method. It is formed by.
【0008】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図1(a)〜(d)は本発明の第1の実施例を説明
するための半導体チップの断面図であり、本発明を薄膜
抵抗素子の製造方法に適用した場合である。The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, which is a case where the present invention is applied to a method of manufacturing a thin film resistance element.
【0009】まず図1(a)に示すように、シリコン基
板1上に熱酸化法により厚さ約1μmのSiO2 膜2を
形成したのち、窒素ドープタンタル(Ta2 N)膜3を
マグネトロンスパッタ法により形成する。First, as shown in FIG. 1A, a SiO 2 film 2 having a thickness of about 1 μm is formed on a silicon substrate 1, and then a nitrogen-doped tantalum (Ta 2 N) film 3 is magnetron sputtered. It is formed by the method.
【0010】次に図1(b)に示すように、導体膜とし
て1%のシリコンを含むアルミニウム(Al−Si)膜
4を直流(DC)マグネトロンスパッタ法により約0.
8μmの厚さに形成した後、その上部に約1μmの厚さ
に純アルミニウム(Al)膜5を高周波(RF)マグネ
トロンスパッタ法で連続形成する。この導体膜スパッタ
時の基板温度は約100℃とした。Next, as shown in FIG. 1B, an aluminum (Al--Si) film 4 containing 1% of silicon as a conductor film is formed by a direct current (DC) magnetron sputtering method to a thickness of about 0.
After being formed to a thickness of 8 μm, a pure aluminum (Al) film 5 having a thickness of about 1 μm is continuously formed on the upper portion thereof by a radio frequency (RF) magnetron sputtering method. The substrate temperature during the sputtering of the conductor film was about 100 ° C.
【0011】次に図1(c)に示すように、導体膜をパ
ターニングし、最小幅約40μmのAl−Si膜4とA
l膜5とからなるボンディングパットを形成する。次で
図1(d)に示すように、Ta2 N膜3をパターニング
し、最小幅10μmの薄膜抵抗素子を形成する。しかる
後、薄膜抵抗素子の経時安定性を得るため、空気中で4
50℃の熱処理を実施した。Next, as shown in FIG. 1C, the conductor film is patterned to form an Al-Si film 4 and A having a minimum width of about 40 μm.
A bonding pad composed of the I film 5 is formed. Next, as shown in FIG. 1D, the Ta 2 N film 3 is patterned to form a thin film resistance element having a minimum width of 10 μm. Then, in order to obtain stability over time of the thin film resistance element, 4
Heat treatment at 50 ° C. was performed.
【0012】このように第1の実施例においては、Al
−Si膜4及びAl膜5の形成をそれぞれ直流スパッタ
及び高周波スパッタで行うことにより、Al膜のボンデ
ィング強度のばらつきが従来より抑えられ、かつ、低温
度の基板温度によりSi残渣の少ない薄膜抵抗素子が得
られた。As described above, in the first embodiment, Al
-By forming the Si film 4 and the Al film 5 by direct current sputtering and high frequency sputtering, respectively, variation in bonding strength of the Al film can be suppressed more than before, and the thin film resistance element with less Si residue due to the low substrate temperature. was gotten.
【0013】図2(a)〜(d)は本発明の第2の実施
例を説明するための半導体チップの断面図であり、本発
明を薄膜コンデンサ素子の製造方法に適用した場合であ
る。2 (a) to 2 (d) are sectional views of a semiconductor chip for explaining a second embodiment of the present invention, in which the present invention is applied to a method of manufacturing a thin film capacitor element.
【0014】まず図2(a)に示すように、シリコン基
板1上にSiO2 膜2を形成したのち、窒素ドープタン
タル膜より窒素のドープ量が少ないαタンタル(α−T
a)膜13をマグネトロンスパッタ法により形成する。
次に図2(b)に示すように、このα−Ta膜13をパ
ターニングした後、コンデンサとすべき部分のみ0.0
1%クエン酸溶液中で陽極化成を施して、タンタル陽極
酸化(Ta2 O5 )膜16を形成する。First, as shown in FIG. 2A, after a SiO 2 film 2 is formed on a silicon substrate 1, α-tantalum (α-T) having a smaller nitrogen doping amount than a nitrogen-doped tantalum film is formed.
a) The film 13 is formed by the magnetron sputtering method.
Next, as shown in FIG. 2B, after patterning the α-Ta film 13, only the portion to be a capacitor is 0.0
Anodization is performed in a 1% citric acid solution to form a tantalum anodic oxide (Ta 2 O 5 ) film 16.
【0015】次に図1(c)に示すように、第1の実施
例と同様に導体膜としてAl−Si膜14及びAl膜1
5をそれぞれ直流スパッタ法及び高周波スパッタ法にて
連続形成する。次で図2(d)に示すように、これら導
体膜をパターニングし、コンデンサ素子に接続する配線
を形成した。Next, as shown in FIG. 1C, the Al--Si film 14 and the Al film 1 as conductor films are formed as in the first embodiment.
5 are continuously formed by the DC sputtering method and the high frequency sputtering method. Next, as shown in FIG. 2D, these conductor films were patterned to form wirings connected to the capacitor element.
【0016】このように第2の実施例によれば、Si残
渣による絶縁抵抗特性の劣化が防止され、かつ、配線の
密着強度を従来よりも向上させることができた。As described above, according to the second embodiment, it is possible to prevent the deterioration of the insulation resistance characteristic due to the Si residue and to improve the adhesion strength of the wiring as compared with the conventional case.
【0017】尚、上記実施例ではシリコンを含むアルミ
ニウム膜について説明したが、銅を含むアルミニウムの
場合でも同様の効果がある。Although the aluminum film containing silicon has been described in the above embodiment, the same effect can be obtained in the case of aluminum containing copper.
【0018】[0018]
【発明の効果】以上説明したように本発明は、シリコン
酸化膜を介して形成されたタンタル膜上に不純物を含む
第1のアルミニウム膜及び不純物を含まない第2のアル
ミニウム膜を順次付着形成する際、第1のアルミニウム
膜を直流スパッタ法で形成し、第2のアルミニウム膜を
高周波スパッタ法で形成することにより、Si残渣抑制
のために、導体膜のスパッタ時の基板温度を低温度にし
た場合でも最上部の第2のアルミニウム膜の膜表面が軟
らかくなり、ボンディングの密着強度が従来よりも向上
し、ボンディング強度のばらつきが小さくなるという効
果を有する。As described above, according to the present invention, the first aluminum film containing impurities and the second aluminum film containing no impurities are sequentially deposited on the tantalum film formed via the silicon oxide film. At this time, the first aluminum film was formed by the DC sputtering method and the second aluminum film was formed by the high frequency sputtering method, so that the substrate temperature during the sputtering of the conductor film was lowered to suppress the Si residue. Even in such a case, the film surface of the uppermost second aluminum film is softened, the adhesion strength of bonding is improved as compared with the conventional case, and the variation in bonding strength is reduced.
【図1】本発明の第1の実施例を説明するための半導体
チップの断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図2】本発明の第2の実施例を説明するための半導体
チップの断面図。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
1 シリコン基板 2 SiO2 膜 3 Ta2 N膜 4,14 Al−Si膜 5,15 Al膜 13 α−Ta膜 16 Ta2 O5 膜1 Silicon substrate 2 SiO 2 film 3 Ta 2 N film 4, 14 Al-Si film 5, 15 Al film 13 α-Ta film 16 Ta 2 O 5 film
Claims (2)
ル膜を形成したのち、このタンタル膜上に配線およびボ
ンディングパッド用の不純物を含む第1のアルミニウム
膜と不純物を含まない第2のアルミニウム膜とを順次形
成する薄膜集積回路の製造方法において、第1のアルミ
ニウム膜を直流スパッタ法で形成し、第2のアルミニウ
ム膜を高周波スパッタ法で形成することを特徴とする薄
膜集積回路の製造方法。1. A tantalum film is formed on a silicon substrate via an oxide film, and a first aluminum film containing impurities for wiring and a bonding pad and a second aluminum film containing no impurities are formed on the tantalum film. A method of manufacturing a thin film integrated circuit, wherein a first aluminum film is formed by a DC sputtering method and a second aluminum film is formed by a high frequency sputtering method.
iまたはCuを含む請求項1記載の薄膜集積回路の製造
方法。2. The first aluminum film contains S as an impurity.
The method of manufacturing a thin film integrated circuit according to claim 1, wherein the thin film integrated circuit contains i or Cu.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18278691A JPH0529319A (en) | 1991-07-24 | 1991-07-24 | Manufacture of thin-film integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18278691A JPH0529319A (en) | 1991-07-24 | 1991-07-24 | Manufacture of thin-film integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0529319A true JPH0529319A (en) | 1993-02-05 |
Family
ID=16124397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18278691A Pending JPH0529319A (en) | 1991-07-24 | 1991-07-24 | Manufacture of thin-film integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0529319A (en) |
-
1991
- 1991-07-24 JP JP18278691A patent/JPH0529319A/en active Pending
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