JPH0529306A - Method of forming insulating film by plasma cvd - Google Patents

Method of forming insulating film by plasma cvd

Info

Publication number
JPH0529306A
JPH0529306A JP18212691A JP18212691A JPH0529306A JP H0529306 A JPH0529306 A JP H0529306A JP 18212691 A JP18212691 A JP 18212691A JP 18212691 A JP18212691 A JP 18212691A JP H0529306 A JPH0529306 A JP H0529306A
Authority
JP
Japan
Prior art keywords
substrate
processed
film
insulating film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18212691A
Other languages
Japanese (ja)
Other versions
JP3002294B2 (en
Inventor
Kimitake Hitomi
公猛 人見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Microsystems Co Ltd
Asahi Kasei Microdevices Corp
Original Assignee
Asahi Kasei Microsystems Co Ltd
Asahi Kasei Microdevices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Microsystems Co Ltd, Asahi Kasei Microdevices Corp filed Critical Asahi Kasei Microsystems Co Ltd
Priority to JP3182126A priority Critical patent/JP3002294B2/en
Publication of JPH0529306A publication Critical patent/JPH0529306A/en
Application granted granted Critical
Publication of JP3002294B2 publication Critical patent/JP3002294B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To lessen the dispersion between each board and improve the uniformity between faces by specifying the structure of the rear and the margin of the surface of a substrate to be processed when forming an insulating film, using a hot wall type plasma CVD device. CONSTITUTION:A low-resistance regions 12 or 21 is provided at the rear of a substrate 10 or 20 to be processed, and besides the low-resistance region 12 or 21 is turned in, at least, to the vicinity of the surface of the substrate to be processed. The substrate to be processed, which has such structure, is supported with parallel planar electrodes, and plasma is generated to form an insulating film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプラズマCVDによる絶
縁膜の形成方法に関し、更に詳しくは大量バッチ処理が
可能な多層平行平板型プラズマCVD装置、いわゆるホ
ットウォール型PE−CVD装置による絶縁膜の形成方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an insulating film by plasma CVD, and more specifically, it forms an insulating film by a multi-layer parallel plate type plasma CVD apparatus capable of large-scale batch processing, so-called hot wall type PE-CVD apparatus. It is about the method.

【0002】[0002]

【従来の技術】半導体装置のパッシベション膜等を形成
する場合にはプラズマCVDによる膜形成がよく用いら
れている。例えば、窒化シリコン(Si3 4 )を半導
体基板の表面に形成する際には、電極間に半導体基板を
設置し、この電極間に高周波電源を接続すると共にシラ
ン(SiH4 )とアンモニア(NH3 )を導入し、プラ
ズマを発生させ、Si3 4 の絶縁膜を半導体基板の表
面に形成している。
2. Description of the Related Art When forming a passivation film or the like of a semiconductor device, film formation by plasma CVD is often used. For example, when silicon nitride (Si 3 N 4 ) is formed on the surface of a semiconductor substrate, the semiconductor substrate is placed between electrodes, a high frequency power source is connected between the electrodes, and silane (SiH 4 ) and ammonia (NH 3 ) are used. 3 ) is introduced and plasma is generated to form an insulating film of Si 3 N 4 on the surface of the semiconductor substrate.

【0003】このようなプラズマCVD装置で大量バッ
チ処理が可能な装置として多層平行平板型プラズマCV
D装置、いわゆるホットウォール型PE−CVD装置が
ある。これは、図9に示すように石英管1の中に予め半
導体基板2が支持された平板電極3が挿入され、プロセ
スガス、例えばSiH4 、NH3 が石英管1の中に導入
され、平板電極3に高周波電源4からの高周波電力を印
加して、同時にヒータ5で石英管1を加熱する。このよ
うにすると石英間1の中にプラズマが発生し、半導体基
板2の表面にSi3 4 の層が形成される。
A multi-layer parallel plate type plasma CV is used as a device capable of large-scale batch processing by such a plasma CVD device.
There is a D device, a so-called hot wall type PE-CVD device. As shown in FIG. 9, a flat plate electrode 3 on which a semiconductor substrate 2 is previously supported is inserted into a quartz tube 1 and a process gas such as SiH 4 or NH 3 is introduced into the quartz tube 1 to form a flat plate. A high frequency power from a high frequency power source 4 is applied to the electrode 3, and at the same time, the quartz tube 1 is heated by the heater 5. In this way, plasma is generated in the quartz gap 1 and a layer of Si 3 N 4 is formed on the surface of the semiconductor substrate 2.

【0004】平板電極3はカーボンディスクで構成さ
れ、平板電極3への高周波電力の印加は、一対の母線6
及び7にそれぞれ高周波電源4の正負の端子が接続さ
れ、各平板電極3には母線6及び7から交互に接続され
る。従って、隣会う平板電極3間にはそれぞれ高周波電
界が形成され、プラズマを発生することができる。
The plate electrode 3 is composed of a carbon disk, and high frequency power is applied to the plate electrode 3 by applying a pair of bus bars 6 to each other.
And 7 are connected to the positive and negative terminals of the high frequency power source 4, respectively, and the plate electrodes 3 are alternately connected from the busbars 6 and 7. Therefore, a high frequency electric field is formed between the adjacent flat plate electrodes 3, and plasma can be generated.

【0005】[0005]

【発明が解決しようとする課題】このようなホットウォ
ール型PE−CVD装置では、平板電極3の端部と中心
部とで膜厚にばらつきが生じやすく、またプラズマの発
生が一様でないために、隣会う半導体基板間においても
膜厚にばらつきが生じやすいという問題があった。例え
ば、上記Si3 4 をパッシベーション膜として用いる
場合には、厚いと応力が大きくなり、薄いとパッシベー
ション膜としての効果が低下するため、膜厚の均一性、
特に同一バッチ内の基板間の膜厚の均一性を向上させる
ことが重要である。
In such a hot-wall type PE-CVD apparatus, the film thickness is likely to vary between the end portion and the center portion of the plate electrode 3, and the plasma is not generated uniformly. However, there is a problem that the film thickness easily varies between adjacent semiconductor substrates. For example, when the above Si 3 N 4 is used as a passivation film, if the thickness is large, the stress becomes large, and if it is thin, the effect as the passivation film decreases, so that the film thickness uniformity,
In particular, it is important to improve the film thickness uniformity between the substrates in the same batch.

【0006】以上の問題を解決しようとする試みは種々
なされており、例えば特開昭60−202929号公報
や特公昭58−46057号公報には各平板電極間ごと
の電源を独立に制御することにより各平板電極間の電界
強度を一定にしたり、位相を揃えるなどして膜厚の均一
性を向上させていることが示されている。しかしなが
ら、上記装置では端部と中心部とでの膜厚のばらつきを
抑えることができるが、各半導体基板間のばらつきを抑
制するのは十分でない。
Various attempts have been made to solve the above problems. For example, in Japanese Patent Laid-Open No. 60-202929 and Japanese Patent Publication No. 58-46057, it is necessary to independently control the power source for each plate electrode. Show that the uniformity of the film thickness is improved by making the electric field strength between the flat plate electrodes constant or by aligning the phases. However, in the above device, the variation in the film thickness between the end portion and the central portion can be suppressed, but it is not sufficient to suppress the variation between the semiconductor substrates.

【0007】以上の点に鑑み、本発明はプラズマCVD
による絶縁膜の厚さの均一性を向上させる形成方法を提
供することを課題とする。
In view of the above points, the present invention is plasma CVD.
It is an object of the present invention to provide a forming method for improving the uniformity of the thickness of an insulating film by the method.

【0008】[0008]

【課題を解決する為の手段】本発明は、被処理基板を支
持するための複数の平板電極を平行に配列し、配列され
た平板電極を一対の母線に交互に接続し、該一対の母線
に高周波電力を供給して該電極間にプラズマを発生させ
て、前記被処理基板の表面に絶縁膜を形成方法する方法
において、前記電極に支持される前記被処理基板の裏面
に低抵抗領域が設けられ、且つ該低抵抗領域が少なくと
も前記被処理基板の表面周辺に回り込んでいることを特
徴とするものである。低抵抗領域は、1×10-3Ωcm以
下の抵抗が好ましく、例えば多結晶シリコン(Poly
−Si)を半導体基板の裏面及び表面周辺に形成し、リ
ン等をドープして抵抗を低くしてもよいし、半導体基板
自体にリン等をドープして、裏面及び表面周辺の抵抗を
低くしてもよい。半導体基板そのものを1×10-3Ωcm
以下の低抵抗のものを用いることにより裏面及び表面周
辺を低抵抗領域としてもよい。
According to the present invention, a plurality of plate electrodes for supporting a substrate to be processed are arranged in parallel, and the arranged plate electrodes are alternately connected to a pair of bus bars. In the method of forming an insulating film on the surface of the substrate to be processed by supplying high frequency power to the substrate to generate plasma between the electrodes, a low resistance region is formed on the back surface of the substrate to be processed supported by the electrodes. It is characterized in that it is provided and the low resistance region extends around at least the periphery of the surface of the substrate to be processed. The low resistance region preferably has a resistance of 1 × 10 −3 Ωcm or less, such as polycrystalline silicon (Polysilicon).
-Si) may be formed on the back and front surfaces of the semiconductor substrate and doped with phosphorus or the like to lower the resistance, or the semiconductor substrate itself may be doped with phosphorus or the like to lower the resistance on the back and front surfaces. May be. The semiconductor substrate itself is 1 × 10 -3 Ωcm
The back surface and the periphery of the surface may be used as the low resistance region by using the following low resistance materials.

【0009】[0009]

【作用】本発明によれば、各半導体基板間のばらつき、
いわゆる面間均一性を向上することができると共に、1
枚の半導体基板内での膜厚のばらつきを少なくすること
ができる。
According to the present invention, variations among semiconductor substrates,
It is possible to improve the so-called surface-to-surface uniformity and
It is possible to reduce variations in film thickness within a single semiconductor substrate.

【0010】[0010]

【実施例】以下、本発明について図面に基づいて詳細に
説明する。図1(A)及び(B)は、本発明のプラズマ
CVDによる絶縁膜の形成方法に用いられる半導体基板
の前処理を示す断面図で、図1(A)及び(B)のよう
に処理された被処理基板を図9に示すCVD装置の平板
電極3の両面に設置し、Si3 4 膜を形成した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. 1A and 1B are cross-sectional views showing pretreatment of a semiconductor substrate used in the method for forming an insulating film by plasma CVD according to the present invention, which is processed as shown in FIGS. 1A and 1B. The substrates to be processed were placed on both sides of the flat plate electrode 3 of the CVD apparatus shown in FIG. 9 to form a Si 3 N 4 film.

【0011】また、図2(a)乃至(e)は比較例とし
て前処理された半導体基板の断面図である。なお、各実
施例及び比較例の条件は下記のようにした。 プロセスガス SiH4 780〔cc/min 〕 NH3 7〔リットル/min 〕 圧力 2.20〔torr〕 高周波電力 2.1〔kW〕 430〔kHz〕
2A to 2E are sectional views of a preprocessed semiconductor substrate as a comparative example. The conditions of each Example and Comparative Example are as follows. Process gas SiH 4 780 [cc / min] NH 3 7 [l / min] Pressure 2.20 [torr] RF power 2.1 [kW] 430 [kHz]

【0012】[0012]

【実施例1】図1(A)は、Si3 4 膜の形成の前処
理として、半導体基板10の裏面及び表面の周辺に薄い
酸化膜11を形成し、その酸化膜11の上層に低抵抗化
された多結晶シリコン層12を形成したものである。半
導体基板10はN型シリコンで、8〜12Ωcmのものを
用い、熱酸化処理して形成された酸化膜11はおよそ5
00Åの厚さであり、多結晶シリコン層12は3700
Åの厚さに形成されたものにリンをドープして、7.4
×10-4Ωcmとしたものである。
Example 1 FIG. 1A shows that a thin oxide film 11 is formed on the periphery of the back surface and the front surface of a semiconductor substrate 10 as a pretreatment for forming a Si 3 N 4 film, and a low oxide film is formed on the oxide film 11 as a layer. A polycrystalline silicon layer 12 having a resistance is formed. The semiconductor substrate 10 is made of N-type silicon and has a thickness of 8 to 12 Ωcm, and the oxide film 11 formed by thermal oxidation is about 5
It has a thickness of 00Å, and the polycrystalline silicon layer 12 has a thickness of 3700.
Doped with phosphorus to the thickness of Å, 7.4
It is set to × 10 −4 Ωcm.

【0013】このようにして前処理された半導体基板を
用い、Si3 4 膜を形成したときの膜厚を図3に示
す。縦軸はSi3 4 膜の膜厚を示し、横軸は平板電極
に設置された半導体基板の位置番号、すなわち端部から
の位置を示すものである。図に示すように膜厚のばらつ
きが小さく、面間均一性を
FIG. 3 shows the film thickness when a Si 3 N 4 film is formed using the semiconductor substrate thus pretreated. The vertical axis represents the film thickness of the Si 3 N 4 film, and the horizontal axis represents the position number of the semiconductor substrate mounted on the plate electrode, that is, the position from the end. As shown in the figure, there is little variation in film thickness

【0014】[0014]

【数1】 [Equation 1]

【0015】とするとおよそ3.8%であった。なお、
実際のLSI製造プロセスで上記のように前処理するに
は特別の処理を必要とせず、ゲート電極や配線として用
いられる多結晶シリコン層が裏面及び表面周辺に形成さ
れている場合に、その上層に設けられた酸化膜等の絶縁
膜を除去し、ドープされた多結晶層を露出するだけでよ
い。
Then, it was about 3.8%. In addition,
No special treatment is required for the pretreatment in the actual LSI manufacturing process as described above, and when a polycrystalline silicon layer used as a gate electrode or wiring is formed on the back surface and the periphery of the surface, It is only necessary to remove the insulating film such as the provided oxide film and expose the doped polycrystalline layer.

【0016】[0016]

【実施例2】図1(B)は、Si3 4 膜の形成の前処
理として、半導体基板20そのものの裏面及び表面の周
辺に低抵抗領域21を形成したものである。半導体基板
20はN型シリコンで、4〜6Ωcmのものを用い、リン
をドープして、1×10-3Ωcm以下としたものである。
Second Embodiment FIG. 1B shows a low resistance region 21 formed around the back surface and front surface of the semiconductor substrate 20 itself as a pretreatment for the formation of the Si 3 N 4 film. The semiconductor substrate 20 is made of N-type silicon and has a thickness of 4 to 6 Ωcm and is doped with phosphorus to have a density of 1 × 10 −3 Ωcm or less.

【0017】このようにして前処理された半導体基板を
用い、Si3 4 膜を形成したときの膜厚を図4に示
す。図に示すように、この場合も膜厚のばらつきが小さ
く、面間均一性はおよそ3.8%であった。なお、本実
施例では、製品のパターン22が半導体基板20の表面
に設けられており、多結晶シリコンへのリンドープの前
に裏面及び表面周辺の多結晶層や酸化膜層を除去し、半
導体基板20を露出させ、リンをドープさせれば、上記
のような構造になる。
FIG. 4 shows the film thickness when a Si 3 N 4 film is formed using the semiconductor substrate thus pretreated. As shown in the figure, in this case as well, the variation in the film thickness was small, and the in-plane uniformity was about 3.8%. In this embodiment, the product pattern 22 is provided on the front surface of the semiconductor substrate 20, and the polycrystal layer and the oxide film layer on the back surface and around the front surface are removed before phosphorus doping into the polycrystal silicon to remove the semiconductor substrate. When 20 is exposed and phosphorus is doped, the above structure is obtained.

【0018】また、半導体基板20が1×10-3Ωcm以
下であって、裏面及び表面周辺が露出していれば同様の
効果が得られる。
The same effect can be obtained if the semiconductor substrate 20 is 1 × 10 −3 Ωcm or less and the back surface and the periphery of the surface are exposed.

【0019】[0019]

【比較例1】図2(a)は、被処理基板として半導体基
板30を用いてSi3 4 膜を形成した例である。半導
体基板30はN型シリコンで、8〜12Ωcmのものを用
いた。この半導体基板を用い、Si3 4 膜を形成した
ときの膜厚を図5に示す。図に示すように、この場合は
膜厚のばらつきが大きく、面間均一性は7.9%であっ
た。
Comparative Example 1 FIG. 2A shows an example in which a semiconductor substrate 30 is used as a substrate to be processed to form a Si 3 N 4 film. The semiconductor substrate 30 is N-type silicon and has a thickness of 8 to 12 Ωcm. FIG. 5 shows the film thickness when a Si 3 N 4 film was formed using this semiconductor substrate. As shown in the figure, in this case, the variation in the film thickness was large, and the inter-plane uniformity was 7.9%.

【0020】[0020]

【比較例2】図6は、被処理基板として図2(a)、図
2(b)、図2(c)に示す被処理基板を用い、同一石
英管中に挿入してSi3 4 膜を形成したときの膜厚を
示す図である。図2(b)は、被処理基板として2.5
〜3.5ΩcmのN型シリコン基板40を用い、図2
(c)は被処理基板として0.008〜0.018Ωcm
のN型シリコン基板50の表面に4〜6Ωcmのエピタキ
シャル成長層51を形成したものである。
[Comparative Example 2] FIG. 6 shows the case where the substrates to be processed shown in FIGS. 2A, 2B and 2C are used as the substrates to be processed and Si 3 N 4 is inserted into the same quartz tube. It is a figure which shows the film thickness when a film is formed. FIG. 2B shows that the substrate to be processed is 2.5
Using an N-type silicon substrate 40 of ~ 3.5 Ωcm,
(C) is a processed substrate of 0.008 to 0.018 Ωcm
The N-type silicon substrate 50 is formed with an epitaxial growth layer 51 of 4 to 6 Ωcm.

【0021】これらの被処理基板を用い、Si3 4
を形成したときの膜厚は、図2(c)に示した被処理基
板が成長速度が大きいことがわかる。しかし、膜厚のば
らつきは、いずれの被処理基板も大きく、裏面のみに低
抵抗領域を形成しただけでは効果がないことがわかる。
It can be seen that when the Si 3 N 4 film is formed using these substrates to be processed, the substrate to be processed shown in FIG. 2C has a high growth rate. However, it is understood that the variation in the film thickness is large in all the substrates to be processed, and that forming the low resistance region only on the back surface is not effective.

【0022】[0022]

【比較例3】図7は、被処理基板として図2(d)に示
すように9〜12ΩcmのN型シリコン基板60を用い、
その表面に製品のパターン61が形成され、裏面及び表
面周辺が露出したものを使用したときの膜厚を示す図で
ある。同様に膜厚のばらつきは大きい。
Comparative Example 3 In FIG. 7, an N-type silicon substrate 60 of 9 to 12 Ωcm as shown in FIG.
It is a figure which shows the film thickness at the time of using what used the product pattern 61 formed on the surface and exposed the back surface and the surface periphery. Similarly, the variation in film thickness is large.

【0023】[0023]

【比較例4】図8は、被処理基板として図2(e)に示
すように表面に製品のパターンが形成され、裏面は配線
に用いられる多結晶シリコン層や層間絶縁膜等がそのま
ま残されたものを用いた場合のSi3 4 膜を形成した
ときの膜厚を示す図である。図2(e)に示す被処理基
板は、4〜6ΩcmのN型シリコン基板70を用い、その
上層に、ゲート絶縁膜として形成される酸化膜71と、
ゲート電極として形成されるリンドープされた多結晶シ
リコン層72と、層間絶縁膜として形成される酸化膜7
3と、第2のリンドープされた多結晶シリコン層74
と、絶縁膜として形成される酸化膜75とがシリコン基
板70の裏面及び表面周辺に設けられているものであ
る。多結晶シリコン層72及び74の抵抗はおよそ7.
4×10-4Ωcmである。
COMPARATIVE EXAMPLE 4 In FIG. 8, as a substrate to be processed, a product pattern is formed on the front surface as shown in FIG. 2E, and on the rear surface, a polycrystalline silicon layer used for wiring, an interlayer insulating film, etc. are left as they are. it is a diagram showing a film thickness when was an Si 3 N 4 film in the case of using those were. The substrate to be processed shown in FIG. 2E uses an N-type silicon substrate 70 of 4 to 6 Ωcm, and an oxide film 71 formed as a gate insulating film on the upper layer thereof,
Phosphorus-doped polycrystalline silicon layer 72 formed as a gate electrode and oxide film 7 formed as an interlayer insulating film
3 and a second phosphorus-doped polycrystalline silicon layer 74
And an oxide film 75 formed as an insulating film are provided around the back surface and front surface of the silicon substrate 70. The polycrystalline silicon layers 72 and 74 have a resistance of approximately 7.
It is 4 × 10 −4 Ωcm.

【0024】図8に示すように本比較例もばらつきが大
きく、面間均一性はおよそ11.4%もある。なお、本
比較例の酸化膜75と多結晶シリコン層74と酸化膜7
3とを除去すれば図1(A)の被処理基板と同等のもの
となり、従って、上記3層を除去したもので、膜を成長
させれば膜厚のばらつきは小さくなることになる。
As shown in FIG. 8, this comparative example also has a large variation, and the surface-to-plane uniformity is about 11.4%. The oxide film 75, the polycrystalline silicon layer 74, and the oxide film 7 of this comparative example were used.
3 is removed, the substrate becomes equivalent to the substrate to be processed in FIG. 1A. Therefore, if the above three layers are removed and the film is grown, the variation in film thickness will be reduced.

【0025】[0025]

【発明の効果】以上のように、本発明によれば各半導体
基板間のばらつき、いわゆる面間均一性を向上すること
ができると共に、1枚の半導体基板内での膜厚のばらつ
きを少なくすることができる。
As described above, according to the present invention, it is possible to improve the variation between the semiconductor substrates, that is, the so-called face-to-face uniformity, and reduce the variation in the film thickness within one semiconductor substrate. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のプラズマCVDによる絶縁膜の形成方
法に用いられる半導体基板の前処理を示す断面図であ
る。
FIG. 1 is a cross-sectional view showing a pretreatment of a semiconductor substrate used in a method for forming an insulating film by plasma CVD according to the present invention.

【図2】比較例の半導体基板の前処理を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing pretreatment of a semiconductor substrate of a comparative example.

【図3】本発明の実施例1による膜厚を示す図である。FIG. 3 is a diagram showing a film thickness according to Example 1 of the present invention.

【図4】本発明の実施例2による膜厚を示す図である。FIG. 4 is a diagram showing a film thickness according to a second embodiment of the present invention.

【図5】比較例1による膜厚を示す図である。5 is a diagram showing a film thickness according to Comparative Example 1. FIG.

【図6】比較例2による膜厚を示す図である。6 is a diagram showing a film thickness according to Comparative Example 2. FIG.

【図7】比較例3による膜厚を示す図である。7 is a diagram showing a film thickness according to Comparative Example 3. FIG.

【図8】比較例4による膜厚を示す図である。FIG. 8 is a diagram showing a film thickness according to Comparative Example 4.

【図9】ホットウォール型プラズマCVD装置の構成を
示す図である。
FIG. 9 is a diagram showing a configuration of a hot wall type plasma CVD apparatus.

【符号の説明】[Explanation of symbols]

2 被処理基板 3 平板電極 4 高周波電源 6、7 母線 10、20 半導体基板 12、21 低抵抗領域 2 substrate to be processed 3 plate electrode 4 high frequency power supply 6, 7 bus bar 10, 20 semiconductor substrate 12, 21 low resistance region

Claims (1)

【特許請求の範囲】 【請求項1】 被処理基板を支持するための複数の平板
電極を平行に配列し、配列された平板電極を一対の母線
に交互に接続し、該一対の母線に高周波電力を供給して
該電極間にプラズマを発生させて、前記被処理基板の表
面に絶縁膜を形成方法する方法において、前記電極に支
持される前記被処理基板の裏面に低抵抗領域が設けら
れ、且つ該低抵抗領域が少なくとも前記被処理基板の表
面周辺に回り込んでいることを特徴とするプラズマCV
Dによる絶縁膜の形成方法。
Claim: What is claimed is: 1. A plurality of flat plate electrodes for supporting a substrate to be processed are arranged in parallel, the arranged flat plate electrodes are alternately connected to a pair of bus bars, and a high frequency wave is applied to the pair of bus bars. In the method of forming an insulating film on the surface of the substrate to be processed by supplying electric power to generate plasma between the electrodes, a low resistance region is provided on the back surface of the substrate to be processed supported by the electrodes. And the low resistance region wraps around at least the surface periphery of the substrate to be processed.
A method of forming an insulating film by D.
JP3182126A 1991-07-23 1991-07-23 Method of forming insulating film by plasma CVD Expired - Lifetime JP3002294B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3182126A JP3002294B2 (en) 1991-07-23 1991-07-23 Method of forming insulating film by plasma CVD

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182126A JP3002294B2 (en) 1991-07-23 1991-07-23 Method of forming insulating film by plasma CVD

Publications (2)

Publication Number Publication Date
JPH0529306A true JPH0529306A (en) 1993-02-05
JP3002294B2 JP3002294B2 (en) 2000-01-24

Family

ID=16112785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3182126A Expired - Lifetime JP3002294B2 (en) 1991-07-23 1991-07-23 Method of forming insulating film by plasma CVD

Country Status (1)

Country Link
JP (1) JP3002294B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010135835A (en) * 2010-02-17 2010-06-17 Sharp Corp Plasma processing apparatus and semiconductor device manufactured by the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010135835A (en) * 2010-02-17 2010-06-17 Sharp Corp Plasma processing apparatus and semiconductor device manufactured by the same

Also Published As

Publication number Publication date
JP3002294B2 (en) 2000-01-24

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