JPH05291513A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor substrate with which the breakdown strength deterioration can be avoided and which has a required mechanical strength in order to cope with the diameter increase of a wafer required from the finer structure and productivity improvement of a semiconductor device and to provide a Bi-CMOS semiconductor device which can maintain the electrical characteristics of both a bipolar transistor and a field effect transistor. CONSTITUTION:An epitaxial layer 200 is formed on a silicon wafer 100 produced by a CZ method. A silicon wafer 300 produced by an FZ method is bonded to the epitaxial layer 200. An n-p-n bipolar transistor 250 is formed in the epitaxial layer 200. An n-type channel MOS transistor 350 and a p-type channel MOS transistor 360 are formed in the silicon wafer 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a semiconductor substrate, for example, a substrate obtained by directly bonding two silicon wafers, and a method of manufacturing the same, and more specifically, to two types of semiconductor devices having different oxygen concentrations. The present invention relates to a so-called Bi-CMOS type semiconductor device in which a bipolar transistor and a field effect transistor are formed using a semiconductor substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art At present, when manufacturing a semiconductor device, a silicon wafer is often used as a semiconductor substrate. The silicon wafer manufacturing method is roughly divided into the CZ method (Cz method).
ochralski method), FZ method (flo
ating zone method), MCZ method (m
agricultural-field-applied Czo
chralski method). The characteristics of each of the silicon wafers obtained by these three manufacturing methods are shown below.

(I) CZ silicon wafer Oxygen concentration: 1.0 to 1.8 × 10 ¹⁸ / cm ³ High mechanical strength.

(Ii) MCZ silicon wafer Oxygen concentration: 2-8 × 10 ¹⁷ / cm ³ Medium mechanical strength.

(Iii) FZ silicon wafer Oxygen concentration: <1 × 10 ¹⁶ / cm ³ Mechanical strength is weak.

Among the above three types of silicon wafers, most of the semiconductor substrates of large scale integrated circuit devices (LSI) are silicon wafers manufactured by the CZ method at present. In particular, when the diameter of the silicon wafer becomes 8 inches or more, in order to prevent the wafer from being damaged in the manufacturing process, the silicon wafer manufactured by the CZ method has to be used because of its strength.

When a wafer is manufactured by the CZ method, a quartz crucible is generally used. Therefore, oxygen is supplied from the quartz crucible to the silicon single crystal being produced, and a silicon wafer having a high oxygen concentration of 1.0 to 1.8 × 10 ¹⁸ / cm ³ is produced. However, the high concentration of oxygen increases the mechanical strength of the wafer itself. Therefore, the CZ wafer can be used as a wafer having a large diameter for improving productivity.

However, the oxygen concentration of the CZ silicon wafer is as high as 1.0 to 1.8 × 10 ¹⁸ / cm ³ . Therefore, when a silicon oxide film is formed on a CZ silicon wafer, the silicon oxide film has many defects. Thus, for example, when a silicon oxide film is used as a gate oxide film of a field effect transistor, there is a problem that the breakdown voltage of the gate oxide film deteriorates with the miniaturization of the semiconductor device formed on the silicon wafer. ..

Further, according to the FZ method, a silicon wafer having a low oxygen concentration can be manufactured. However,
The mechanical strength of FZ silicon wafer is weaker than that of CZ silicon wafer due to its low oxygen concentration. for that reason,
The FZ silicon wafer has a problem that the silicon wafer is easily damaged by a plurality of treatments or handlings involving heat history. On the other hand, due to the low oxygen concentration, a high-quality silicon oxide film with few defects is formed by FZ
It can be formed on a silicon wafer.

Therefore, as disclosed in Japanese Patent Laid-Open No. 2-46770, a semiconductor device having an SOI structure using a substrate in which an FZ silicon wafer having a low oxygen concentration is bonded onto a CZ silicon wafer having a high oxygen concentration is disclosed. Proposed. According to this semiconductor device, the characteristics of the gate oxide film can be improved by forming the silicon oxide film on the FZ silicon wafer having a low oxygen concentration even if miniaturization progresses. Further, the CZ silicon wafer can obtain high mechanical strength, and can cope with an increase in the diameter of the wafer for improving productivity.

A method for manufacturing a semiconductor device substrate in which two silicon wafers are directly bonded to each other is disclosed in, for example, Japanese Unexamined Patent Publication No. 2-183510.

[0012]

As described above, when a MOS semiconductor device including a field effect transistor is formed by using an FZ silicon wafer bonded on a CZ silicon wafer as a substrate, the breakdown voltage of the gate oxide film is improved. As a result, it is possible to obtain a semiconductor device in which electrical characteristics are not deteriorated even when miniaturization progresses. However, when a so-called Bi-CMOS type semiconductor device in which a bipolar transistor and a field effect transistor are formed on one substrate is formed on the above-mentioned bonded FZ silicon wafer, the following problems occur. Below, Bi-CM
While explaining the method of manufacturing the OS type semiconductor device in the order of steps,
Let's examine the problem.

FIGS. 22 to 33 show a FZ silicon wafer bonded on a CZ silicon wafer and a Bi-CM.
FIG. 6 is a partial cross-sectional view showing, in sequence, the manufacturing process for forming the OS type semiconductor device.

First, a silicon wafer is manufactured by using the CZ method. Further, a silicon wafer is manufactured by using the FZ method. The surface of each silicon wafer is cleaned to be highly cleaned and subjected to a hydrophilic treatment. The surfaces of the CZ silicon wafer and the FZ silicon wafer thus treated are mechanically bonded to each other. Then 500-1
The heat treatment at a temperature of 000 ° C. causes a dehydration condensation reaction between the bonded surfaces of the CZ silicon wafer and the FZ silicon wafer. By controlling the heat treatment, the bonding between the CZ silicon wafer and the FZ silicon wafer is strengthened. In this way, as shown in FIG. 22, a silicon substrate in which the p-type FZ silicon wafer 300a is bonded onto the p-type CZ silicon wafer 100 is manufactured.

Next, referring to FIG. 23, the p-type and n-type are formed at a dose of about 10 ¹⁵ to 10 ¹⁶ / cm ² by using the ion implantation method.
Type impurity ions are respectively generated in the FZ silicon wafer 30.
It is introduced into a predetermined area of 0a. Then 700-11
By performing heat treatment at a temperature of 00 ° C., n ⁺ buried diffusion layers 371 and 374 and p ⁺ buried diffusion layers 372 and 373 are formed.
Is formed.

Referring to FIG. 24, FZ silicon wafer 3
N ^- epitaxial layer 400 650 on the surface of 00a
It is formed with a thickness of 2 to 10 μm at a temperature of ˜1100 ° C.

As shown in FIG. 25, n-type and p-type impurities are ion-implanted into predetermined regions of n ^- epitaxial layer 400 at a dose of about 10 ¹² to 10 ¹³ / cm ² , respectively. After that, a lamp annealing process is performed at a temperature of 600 to 1000 ° C., whereby the n-type well region 4
01, 403, 405 and p-type well regions 402, 404
And are formed. In this way, a well region is formed as a CMOS transistor formation region.

As shown in FIG. 26, the p-type well region 40 is formed.
2, p-type impurities are ion-implanted at a dose of about 10 ¹² to 10 ¹⁴ / cm ² . After that, 600 ~ 1000 ℃
By performing the lamp annealing treatment at the temperature of
⁺ Region 402, p ⁻ region 406, and p ⁺ buried diffusion layer 372
To form a p-type isolation region.

Referring to FIG. 27, isolation oxide films 407, 408 and 409 are formed so as to isolate a predetermined element formation region of n ⁻ epitaxial layer 400. At this time,
N regions 410, 411, 413 and p region 412 are formed.

Referring to FIG. 28, an n-type impurity is ion-implanted into a partial region of n-region 410 at a dose amount of about 10 ¹⁴ to 10 ¹⁷ / cm ² . After that, 600 ~ 1000 ℃
By performing the lamp annealing treatment at the temperature of
^{+ A} collector wall 414 is formed.

As shown in FIG. 29, a gate oxide film 415 is formed in p region 412 and a gate oxide film 416 is formed in n region 413. Gate electrodes 417 and 41 having a polycide structure are formed on the gate oxide films 415 and 416, respectively.
8 is formed. Using each gate electrode 417 or 418 as a mask, n-type and p-type impurities are
Ion implantation is performed with a dose amount of about 0 ¹⁵ to 10 ¹⁶ / cm ² . Then, a lamp annealing process is performed at a temperature of 600 to 1000 ° C. to form an n-type source / drain region 419 and a p-type source / drain region 420. In this way, the n-channel MOS transistor 4
50 and p channel MOS transistor 460 are formed.

As shown in FIG. 30, p-type impurities are ion-implanted into the n region 410 at a dose amount of 10 ¹³ to 10 ¹⁵ / cm ² . Then, a lamp anneal process is performed at a temperature of 600 to 1000 ° C. to form p ⁺ base region 421.

As shown in FIG. 31, p⁺Base region 42
N-type impurities in 10 ¹⁵-10¹⁶/ Cm²
Ions are implanted with a dose of about the same. Then 600 ~
Lamp annealing should be performed at a temperature of 1000 ° C
By n⁺Emitter region 422 is formed.

In this way, the npn bipolar transistor 470 is formed. As shown in FIG. 32, an interlayer insulating film 423 made of an oxide film is formed on the entire surface of the FZ silicon wafer 300a so as to cover the bipolar transistor 470, the n-channel MOS transistor 450 and the p-channel MOS transistor 460.

Finally, as shown in FIG. 33, the interlayer insulating film 4
A contact hole is opened at 23. Aluminum wiring layers 424, 425, 4 are formed so as to contact the surfaces of the collector region, the emitter region, the base region, the source region and the drain region through the contact holes, respectively.
26, 427, 428, 429, 430 are formed.
As described above, Bi-C is applied to the FZ silicon wafer 300a bonded on the CZ silicon wafer 100.
A MOS semiconductor device is formed.

In the manufacturing process described above, the epitaxial layer 400 is formed on the FZ silicon wafer 300a to form the bipolar transistor. At this time, a slip line is generated on the silicon wafer. Figure 3
4 is a plan view showing slip lines generated when an epitaxial layer is formed on the FZ silicon wafer 300a. FIG. 34A shows a silicon wafer (10
The slip line generated on the (0) plane is shown. FIG. 34B shows the slip line generated on the (111) plane of the silicon wafer. Reference numeral 380 indicates an orientation flat. Referring to (A), FZ silicon wafer 30
It can be seen that the slip line 501 is generated around 0a. Further, referring to (B), it can be seen that the slip lines 502 are formed at a predetermined angle in the peripheral portion of the FZ silicon wafer 300a. Such a slip line is considered to be a set of dislocations as one of the lattice defects of the crystal.

FIG. 35 is an enlarged sectional view of the bipolar transistor formed in the epitaxial layer including the slip line as described above. Referring to this figure, p ⁺ base region 421 is formed in n ⁻ epitaxial layer 400. The p ⁺ base region 421 has an n ⁺ emitter region 42.
2 is formed. A depletion layer 431 is formed between the p ⁺ base region 421 and the n ⁺ emitter region 422. In this case, the slip line 500 exists so as to extend from the p ⁺ base region 421 to the n ⁺ emitter region 422. In this way, the slip line 5 is attached to the pn junction.
If 00 is present, a leak current is likely to occur. As a result, the electrical characteristics of the bipolar transistor deteriorate, and the transistor malfunctions. Therefore, B
A defective i-CMOS type semiconductor device will be generated. That is, the peripheral portion of the FZ silicon wafer 300a where the slip line 501 or 502 is generated (FIG. 34).
A defective Bi-CMOS type semiconductor device is generated. Therefore, the peripheral portion of the silicon wafer in which the defective product is generated is cut off. This causes a reduction in the manufacturing yield of Bi-CMOS type semiconductor devices.

Therefore, the object of the present invention is to cope with the increase in the diameter of the wafer accompanying the improvement in productivity, to prevent the breakdown voltage of the oxide film from being deteriorated due to the miniaturization of the element, and
It is an object of the present invention to provide a Bi-CMOS type semiconductor device capable of improving the characteristics of an S transistor and also improving the electrical characteristics of a bipolar transistor, and a method for manufacturing the same.

[0029]

A semiconductor device according to one aspect of the present invention includes a first semiconductor substrate, a semiconductor layer, a second semiconductor substrate, a bipolar transistor,
And a field effect transistor. The first semiconductor substrate has a main surface and contains oxygen at a first concentration. The semiconductor layer is epitaxially grown on the main surface of the first semiconductor substrate. The second semiconductor substrate is bonded onto the semiconductor layer and contains oxygen at a second concentration lower than the first concentration. The bipolar transistor is formed in the semiconductor layer. The field effect transistor is formed on the second semiconductor substrate.

According to the method of manufacturing a semiconductor device according to another aspect of the present invention, the semiconductor layer is formed by epitaxial growth on the main surface of the first semiconductor substrate containing oxygen at the first concentration. It is formed. A bipolar transistor is formed on this semiconductor layer. A second semiconductor substrate containing oxygen at a second concentration lower than the first concentration is bonded onto the semiconductor layer. A field effect transistor is formed on this second semiconductor substrate.

[0031]

In the semiconductor device of the present invention, the first semiconductor substrate containing oxygen at a relatively high concentration is used as one substrate. A semiconductor layer is formed by epitaxially growing on the first semiconductor substrate.
Therefore, no slip line is generated in this semiconductor layer. Moreover, since the first semiconductor substrate contains relatively high oxygen, its mechanical strength is high.
As a result, it is possible to cope with an increase in the diameter of the silicon wafer due to the improvement in productivity.

A field effect transistor is formed on the second semiconductor substrate having a relatively low oxygen concentration. As a result, the breakdown voltage of the oxide film formed on the surface of the second semiconductor substrate does not deteriorate with miniaturization. Therefore, the electrical characteristics of the field effect transistor can be maintained even if the element is miniaturized.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a Bi-C according to an embodiment of the present invention.
It is a fragmentary sectional view showing a MOS type semiconductor device. Referring to FIG. 1, n ⁺ is formed on the surface of a p-type CZ silicon wafer 100.
Buried diffusion layers 101, 104 and p ⁺ buried diffusion layers 102, 1
03 is formed. An n ⁻ epitaxial layer 200 is formed on the CZ silicon wafer 100. n ^-
The epitaxial layer 200 includes an n ⁺ collector wall layer 2
01 and n ⁻ regions 204 are formed. n ^- region 20
4 has ap ⁺ base region 207 formed therein. An n ⁺ emitter region 208 is formed in the p ⁺ base region 207. In this way, the npn bipolar transistor 250 is formed in the n ⁻ epitaxial layer 200. Further, p ⁺ isolation regions 202 and 203 are formed in the n ⁻ epitaxial layer 200. This gives n ⁻
Regions 204, 205, 206 are electrically isolated. An n-type FZ silicon wafer 300 is bonded onto the n ⁻ epitaxial layer 200.

On the FZ silicon wafer 300, p ⁺ isolation regions 305, n ⁺ regions 306, p ⁺ regions 307 and n ⁻ regions 308 are formed. An n channel MOS transistor 350 is formed in p ⁺ region 307. A p-channel MOS transistor 360 is formed in n ⁻ region 308. n-channel MOS transistor 350
Is a pair of n-type source / drain regions 315, and a gate oxide film 311 and a gate electrode 31 formed between them.
Including 3. The p-channel MOS transistor 360 is
It includes a pair of p-type source / drain regions 316, and a gate oxide film 312 and a gate electrode 314 formed between them.

Isolation oxide films 309 and 310 are formed on the surface of the FZ silicon wafer 300 in order to isolate the bipolar transistor 250, the n-channel MOS transistor 350, and the p-channel MOS transistor 360 from each other. Bipolar transistor 250 and MOS
An interlayer insulating film 324 is formed on the FZ silicon wafer 300 so as to cover the transistors 350 and 360. Contact holes are formed in the interlayer insulating film 324 so as to expose the surfaces of the collector region, the emitter region, the base region, and the source / drain regions. Aluminum wiring layers 325 and 32 are formed so as to contact the respective regions through the respective contact holes.
6, 327, 328, 329, 330, 331 are formed. Note that the npn bipolar transistor 250
N ⁺ collector wall layer 201, p ⁺ base region 20
7, n ⁺ emitter regions 208 and aluminum wiring layers 325, 327, 326 are plug electrodes 321, 323, 322 formed on the FZ silicon wafer 300.
Are connected through each.

A method of manufacturing the Bi-CMOS type semiconductor device configured as described above will be described. 2 to 18
3A to 3D are partial cross-sectional views sequentially showing manufacturing steps of the Bi-CMOS type semiconductor device shown in FIG.

First, referring to FIG. 2, p-type and n-type impurities are ion-implanted into predetermined regions of p-type CZ silicon wafer 100 at a dose of 10 ¹⁵ to 10 ¹⁶ / cm ² , respectively. Then, heat treatment is performed at a temperature of 700 to 1100 ° C. to form n ⁺ buried diffusion layers 101 and 104 and p ⁺ buried diffusion layers 102 and 103.

As shown in FIG. 3, a CZ silicon wafer 1
N ^- epitaxial layer 200 over 001
It is formed with a thickness of 2 to 10 μm at a temperature of 00 ° C. At this time, the oxygen concentration of the CZ silicon wafer 100 is 1.0 to
Since it is a relatively high value of about 1.8 × 10 ¹⁸ / cm ³ , slip lines do not occur in the epitaxial layer 200 even when epitaxial growth is performed on the CZ silicon wafer 100.

Referring to FIG. 4, n ^- epitaxial layer 2
N-type impurities in a predetermined region of 00 of 10 ¹⁴ to 10 ¹⁷ / c
Ions are implanted with a dose amount of about m ² . Then 60
By performing the lamp annealing treatment at a temperature of 0 to 1000 ° C., the n ⁺ collector wall layer 201 is formed.

As shown in FIG. 5, the p ⁺ buried diffusion layer 10 is formed.
N ⁻ epitaxial layer 20 on each of 2, 103
P-type impurities are ion-implanted into the 0 region at a dose of about 10 ¹² to 10 ¹⁴ / cm ² . Then 600-10
By performing the lamp annealing treatment at a temperature of 00 ° C., the p ⁺ isolation regions 202 and 203 are formed. As a result, the n ⁻ regions 204, 205 and 206 are formed so as to be electrically isolated from each other.

As shown in FIG. 6, n^-Part of region 204
There are 10 p-type impurities in the region.¹³-10 ¹⁵/ Cm²Degree of
Ion implantation is performed. Then 600-1000
By performing the lamp annealing treatment at a temperature of ℃,
p⁺A base region 207 is formed.

As shown in FIG. 7, the p ⁺ base region 207 is formed.
N-type impurities are ion-implanted into a partial region of the substrate at a dose of about 10 ¹⁵ to 10 ¹⁶ / cm ² . Then 600-1
By performing a lamp annealing process at a temperature of 000 ° C., n ⁺ emitter region 208 is formed. In this way, the npn bipolar transistor 250 is formed.

Next, the FZ method is used to manufacture a silicon wafer having a relatively low oxygen concentration, for example, a concentration of less than about 1 × 10 ¹⁶ / cm ³ . The surface of the CZ silicon wafer 100 on which the bipolar transistor 250 is formed, to be precise, the surface of the epitaxial layer 200 and the surface of the FZ silicon wafer are cleaned and made hydrophilic. The CZ silicon wafer 100 and the FZ silicon wafer thus processed are mechanically bonded to each other. After that, heat treatment is performed at a temperature of 500 to 1000 ° C., so that a dehydration condensation reaction occurs on the bonding surface of the CZ silicon wafer 100 and the FZ silicon wafer.

A schematic diagram of this dehydration condensation reaction is shown in FIG. Referring to FIG. 21A, the surface of the epitaxial layer 200 formed on the CZ silicon wafer 100 and the surface of the FZ silicon wafer 300 are bonded by hydrogen bonding. A dehydration condensation reaction occurs at the interface between the epitaxial layer 200 and the FZ silicon wafer 300 thus bonded. As a result, water is released as shown in FIG.
00 and the FZ silicon wafer 300 are bonded together with oxygen interposed.

Thereafter, by controlling the heat treatment, 2
The bonding surface of two silicon wafers is strengthened.
The cross section of the semiconductor substrate thus obtained is shown in FIG. An n-type FZ silicon wafer 300 is bonded onto the n ⁻ epitaxial layer 200.

Referring to FIG. 9, FZ silicon wafer 30
By mechanically polishing 0, the thickness of the FZ silicon wafer 300 is reduced to about 10 μm. Then FZ
The surface of the silicon wafer 300 is mirror-polished.

As shown in FIG. 10, FZ silicon wafer 3
P-type and n-type impurities in the predetermined area of 00 are 10
Ions are implanted with a dose amount of about ¹² to 10 ¹³ / cm ² . After that, a lamp annealing process is performed at a temperature of 600 to 1000 ° C., so that the p ⁺ well region 301,
303 and n ⁺ well regions 302 and 304 are formed.

As shown in FIG. 11, the p ⁺ well region 30 is formed.
1,303 is ion-implanted with p-type impurities at a dose of about 10 ¹² to 10 ¹⁴ / cm ² . Then 600-1
By performing the lamp annealing treatment at a temperature of 000 ° C., a p ⁺ isolation region is formed on the FZ silicon wafer 300.

As shown in FIG. 12, isolation oxide films 309 and 310 are formed in predetermined regions of the FZ silicon wafer 300. In this way, p ⁺ isolation region 305, n ⁺ region 306, p ⁺ region 307 and n ⁻ region 308 are formed.

Referring to FIG. 13, p ⁺ region 307 and n ^{− are shown.}
An oxide film is formed in each of the regions 308 by heat treatment at 900 to 1150 ° C., and patterned to form gate oxide films 311 and 312 with a film thickness of 50 to 300 Å. A gate electrode 313 having a polycide structure is formed on each of the gate oxide films 311 and 312.
314 is formed. The gate electrodes 313 and 314 may be formed of other materials such as polycrystalline silicon.

As shown in FIG. 14, using the gate electrodes 313 and 314 as masks, n-type and p-type impurities are ion-implanted at a dose of about 10 ¹⁵ to 10 ¹⁶ / cm ² . Then, a lamp annealing process is performed at a temperature of 600 to 1000 ° C. to form an n-type source / drain region 315 and a p-type source / drain region 316. In this way, the n channel M
OS transistor 350 and p-channel MOS transistor 360 are formed.

As shown in FIG. 15, a photoresist film 317 is formed on the entire surface of the FZ silicon wafer 300. Photoresist film 3 by photolithography technology
17 is selectively removed. As a result, patterning is performed to expose the surface of each region of the bipolar transistor 250 formed in the epitaxial layer 200 on the CZ silicon wafer 100.

As shown in FIG. 16, the FZ silicon wafer 300 is etched using the photoresist film 317 patterned as described above as a mask.
In the case of wet etching, an alkaline solution such as KOH is used, and in the case of dry etching, NF ₃ gas or the like is used. In the case of wet etching using a KOH solution, the etching rate is 0.2-3 μm / mi.
n. It is a degree. As a result, the n ⁺ collector wall layer 201, the n ⁺ emitter region 208, and the p ⁺ base region 20 are formed.
Contact holes 318, 319, and 320 are formed in the FZ silicon wafer 300 so as to expose the respective surfaces of 7. Although not shown, the contact hole 3
An insulating film is formed on the sidewalls of 18, 319 and 320.

As shown in FIG. 17, a conductive layer of tungsten or the like is formed on the entire surface by the CVD method. afterwards,
The conductive layer is contact hole 31 by etching back.
It is made to remain only in the area of 8,319,320. As a result, the plug electrodes 321, 322, 323 are formed.

As shown in FIG. 18, an interlayer insulating film 324 is formed on the entire surface of the FZ silicon wafer 300.

Finally, as shown in FIG. 1, the plug electrode 32
Contact holes are formed in the interlayer insulating film 324 so as to expose respective surfaces of 1, 322 and 323. Further, contact holes are formed in the interlayer insulating film 324 so as to expose the respective surfaces of the n-type source / drain regions 315 and the p-type source / drain regions 316. Aluminum or tungsten wiring layers 325, 326, 32 so as to contact the respective regions through the respective contact holes.
7,328,329,330,331 are formed. In this way, the Bi-CMOS type semiconductor device of the present invention is formed.

Further, in the above embodiment, the thickness of the FZ silicon wafer 300 is set to about 10 μm by mechanically polishing the FZ silicon wafer 300. By doing so, the FZ silicon wafer 30 for forming the contact hole in the step shown in FIG.
The etching time of 0 can be shortened. However, after the FZ silicon wafer 300 is bonded to the CZ silicon wafer 100, in order to reduce the thickness of the FZ silicon wafer 300, a grinder (removing the thickness of about 200 μm) and polishing (removing the thickness of about 30 μm) are used. Two steps are required.

Currently, a standard wafer has a thickness of 5
The size of inch and 6 inch is 625 ± 15 μm, and that of 8 inch is 725 ± 15 μm. The FZ silicon wafer 300 may be used with this thickness as it is.
In that case, the mechanical polishing step becomes unnecessary. However, the etching time of the FZ silicon wafer 300 for forming the contact hole in the process shown in FIG. 16 becomes long. For example, HF / HNO ₃ / CH ₃ C
In the case of chemical etching using OOH or KOH as an etching solution, the etching rate is 20 to 30 μm / mi.
n. _{(HF / HNO 3 / CH 3} COOH), 0.2~3
μm / min. (KOH). When the thickness of the FZ silicon wafer 300 is 625 μm, the etching time is 30 min. More than a degree. Considering the above points, F
The thickness of the Z silicon wafer is selected in the range of 10 to 750 μm. The minimum thickness of the FZ silicon wafer is 10μ.
The reason for setting m is that the active region and the isolation region of the MOS transistor are taken into consideration.

[0059] Further, in the above embodiment, n as shown in FIG. 8 ^- but directly FZ silicon wafer 300 on the epitaxial layer 200 is formed, n as shown in FIG. 19 ^-
Thickness 1000-2000 on the epitaxial layer 200
After forming the oxide film 209 of Å, the FZ silicon wafer 300 may be bonded thereon as shown in FIG. By thus interposing an oxide film on the bonding surface between the CZ silicon wafer and the FZ silicon wafer, the oxide film serves as an etching stopper of the FZ silicon wafer 300 for forming a contact hole in the process shown in FIG. .. Therefore, the in-plane uniformity of the FZ silicon wafer is improved, and overetching on the CZ silicon wafer side is prevented. The cross section of the Bi-CMOS type semiconductor device when the oxide film 209 is formed is shown in FIG.

In the above embodiment, the CMOS region including the n-channel MOS transistor 350 and the p-channel MOS transistor 360 is shown.
Flash memory including transistors (collective erase type E
EPROM), EPROM, SRAM, DRAM, etc.
It may be formed in the MOS region.

[0061]

As described above, according to the present invention, since the bipolar transistor is formed in the semiconductor layer epitaxially grown on the first semiconductor substrate having a relatively high oxygen concentration, a slip line is formed in the semiconductor layer. And the electrical characteristics of the bipolar transistor are not deteriorated. Further, since the field effect transistor is formed on the second semiconductor substrate having a relatively low oxygen concentration, defects such as deterioration of breakdown voltage of the gate oxide film can be suppressed even if miniaturization progresses. As a result, it is possible to obtain a Bi-CMOS type semiconductor device capable of obtaining excellent electric characteristics in both the field effect transistor and the bipolar transistor.

[Brief description of drawings]

FIG. 1 is a partial sectional view showing a Bi-CMOS type semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a first step of a method of manufacturing the Bi-CMOS type semiconductor device shown in FIG.

FIG. 3 is a partial cross-sectional view showing a second step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

FIG. 4 is a partial cross-sectional view showing a third step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

5 is a partial cross-sectional view showing a fourth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

6 is a partial cross sectional view showing a fifth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

7 is a partial cross sectional view showing a sixth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

8 is a partial cross sectional view showing a seventh step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

9 is a partial cross-sectional view showing an eighth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

10 is a partial cross sectional view showing a ninth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

11 is a partial cross sectional view showing a tenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

12 is a partial cross sectional view showing an eleventh step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

13 is a partial cross sectional view showing a twelfth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

14 is a partial cross sectional view showing a thirteenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1. FIG.

FIG. 15 is a partial cross sectional view showing a fourteenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1.

16 is a partial cross sectional view showing a fifteenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG.

FIG. 17 is a partial cross sectional view showing a sixteenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1.

FIG. 18 is a partial cross sectional view showing a seventeenth step of the method for manufacturing the Bi-CMOS type semiconductor device shown in FIG. 1.

FIG. 19 is a partial cross-sectional view showing a step in another manufacturing method of the Bi-CMOS type semiconductor device.

FIG. 20: B manufactured according to the process shown in FIG.
It is a fragmentary sectional view showing an i-CMOS type semiconductor device.

21 (a) and 21 (b) are schematic diagrams (a) and (b) showing a dehydration condensation reaction performed in a step of bonding a CZ silicon wafer and an FZ silicon wafer.

FIG. 22 is a partial cross-sectional view showing a first step of a method for manufacturing a conventional Bi-CMOS type semiconductor device.

FIG. 23 is a partial cross-sectional view showing a second step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 24 is a partial cross-sectional view showing a third step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 25 is a partial cross-sectional view showing a fourth step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 26 is a partial cross-sectional view showing a fifth step of the method for manufacturing the conventional Bi-CMOS type semiconductor device.

FIG. 27 is a partial cross-sectional view showing a sixth step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 28 is a partial cross-sectional view showing a seventh step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 29 is a partial cross-sectional view showing an eighth step of the method for manufacturing the conventional Bi-CMOS type semiconductor device.

FIG. 30 is a partial cross-sectional view showing a ninth step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 31 is a partial cross-sectional view showing a tenth step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

FIG. 32 is a partial cross-sectional view showing the eleventh step of the method for manufacturing the conventional Bi-CMOS type semiconductor device.

FIG. 33 is a partial cross-sectional view showing a twelfth step of the conventional method for manufacturing a Bi-CMOS type semiconductor device.

34A and 34B are schematic views (A) and (B) showing slip lines generated when silicon is epitaxially grown on an FZ silicon wafer.

FIG. 35 is an enlarged partial cross-sectional view showing a bipolar transistor formed in an epitaxial layer in which a slip line has occurred.

[Explanation of symbols]

100 CZ silicon wafer 200 n ^- Epitaxial layer 250 npn bipolar transistor 300 FZ silicon wafer 350 n-channel MOS transistor 360 p-channel MOS transistor

Claims (2)

[Claims] 1. A first semiconductor substrate having a main surface and containing oxygen at a first concentration, a semiconductor layer epitaxially grown on the main surface of the first semiconductor substrate, and the semiconductor layer. A second semiconductor substrate which is bonded onto the semiconductor substrate and contains oxygen at a second concentration lower than the first concentration; a bipolar transistor formed on the semiconductor layer; and a second semiconductor substrate formed on the second semiconductor substrate. And a field effect transistor. 2. A step of forming a semiconductor layer by epitaxial growth on a main surface of a first semiconductor substrate containing oxygen at a first concentration; a step of forming a bipolar transistor in the semiconductor layer; Bonding a second semiconductor substrate containing oxygen at a second concentration lower than the first concentration onto the semiconductor layer; and forming a field effect transistor on the second semiconductor substrate. A method for manufacturing a semiconductor device, comprising: