JPH05291390A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which does not reduce the area of an element region in an element activation region by forming an isolation well in the semiconductor device having an SOI structure in which each element activation region to be a semiconductor chip is isolated into first and second element regions. CONSTITUTION:A semiconductor layer 14 for forming an element on an insulating layer 12 is formed and divided into a plurality of activation element regions 18 from a scribe line region 16, and each activation element region 18 is isolated into first and second element regions 20, 22. An isolation well 28 to which impurities are attached is formed in the isolation region of the semiconductor layer 14 between the first and second element regions 20, 22 and crosses the activation element region 18 to reach the scribe line region 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI structure semiconductor device, and more particularly to a semiconductor device in which each element active region serving as a semiconductor chip is separated into a first element region and a second element region.

[0002]

2. Description of the Related Art As a type of semiconductor device, a semiconductor device in which a digital element region and an analog element region are mixedly mounted on a single semiconductor chip is known. In such a semiconductor chip, noise between the digital element region and the analog element region may affect each other due to noise such as substrate potential variation, which causes malfunction. In this case, the digital element need only have both high-level and low-level signals, so the effect of minute potential fluctuations is small, whereas
The analog element is also greatly affected by fluctuations in the minute potential.
Therefore, in order to block the influence of an external signal on the analog element, a separation well for separating the analog element region is formed inside the semiconductor chip.

A conventional semiconductor device having isolation wells is shown in FIG. 4A is a plan view and FIG. 4B is XX ′.
It is a line sectional view. As shown in FIG. 4B, a silicon oxide film 61 is formed on a silicon substrate 60, and a silicon layer 62 for forming an element is formed on the silicon oxide film 61 to form an SOI structure. As shown in FIG. 4A, the silicon layer 62 is divided into a plurality of semiconductor chip regions 64 by scribe line regions 63. Each semiconductor chip area 64 is separated into an analog element area 65 on the left side in the figure and a digital element area 66 on the right side in the figure. A plurality of pads 67 are formed in the analog element region 65, and a plurality of pads 68 are formed in the digital element region 66.

Isolation well 69 is formed so as to surround analog element region 65 and reach silicon oxide film 61. In the isolation well 69, as shown in FIG. 4B, impurity ions are added to the silicon layer 62 in the silicon oxide film 6.
Formed by ion implantation to reach 1,
The analog element region 65 is electrically cut off from the outside.

[0005]

As described above, the conventional SO
In the semiconductor device having the I structure, since the isolation well 69 has a pattern surrounding the analog element region 65, the area of the element region in the semiconductor chip region is reduced by the width of the isolation well 69. .. Further, in order to input and output the signal of the analog element region 65, it is necessary to wire-bond the input / output signal pad 67 across the separation well 69, which causes a problem that the bonding wire becomes long.

An object of the present invention is to provide a semiconductor device in which the signal line for input / output signals can be shortened without reducing the area of the element region in the semiconductor chip region by forming the isolation well. Especially.

[0007]

A semiconductor layer for forming an element is divided into a plurality of semiconductor chip areas by a scribe line area, and each semiconductor chip area is divided into a first element area and a second element area. In a semiconductor device having a region, an impurity is added to the semiconductor layer between the first element region and the second element region to separate the first element region and the second element region. A semiconductor device is characterized in that an isolation well is formed, and the isolation well reaches the scribe line region across the semiconductor chip region.

[0008]

According to the present invention, an impurity is added to the semiconductor layer between the first element region and the second element region in the semiconductor chip region to separate the first element region and the second element region. Since the isolation well is formed and the isolation well reaches the scribe line region across the semiconductor chip region, the area occupied by the isolation well in the semiconductor chip region can be reduced and the area of the element region can be increased.
It is possible to shorten the signal line for input / output signals to / from the element region.

[0009]

1 shows a semiconductor device according to a first embodiment of the present invention. 1A is a plan view, and FIG. 1B is XX ′.
It is a line sectional view. As shown in FIG. 1B, a silicon oxide film 12 is formed on a silicon substrate 10, and a silicon layer 14 for forming an element is formed on the silicon oxide film 12. As shown in FIG. 1A, the silicon layer 14 is divided into a plurality of semiconductor chip regions 18 by a scribe line region 16 having a width of about 150 μm. Each semiconductor chip region 18 is divided into an analog element region 20 on the left side in the figure and a digital element region 22 on the right side in the figure. A plurality of pads 24 are formed in the analog element region 20, and a plurality of pads 26 are formed in the digital element region 22.

In this embodiment, the analog element region 2 on the left side is
A separation well 28 having a width of about 6 μm is provided to separate 0 and the digital element region 22 on the right side. The isolation well 28 is formed by ion-implanting impurities into the silicon layer 14. The isolation well 28 of this embodiment crosses the semiconductor chip region 18 and intersects the front and rear scribe line regions 16 at a right angle.

As described above, according to the present embodiment, each semiconductor chip region is crossed by only one isolation well, so that the analog element region is effectively reduced without reducing the effective element region area. The digital element areas can be effectively separated. Also, since the pads in the analog element area can be arranged near the scribe line area,
Signal input / output can be performed with a short bonding wire.

A semiconductor device according to the second embodiment of the present invention is shown in FIG. 2A is a plan view and FIG. 2B is X-.
It is a X'line sectional view. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description. The present embodiment is characterized in that when the impurity is ion-implanted to form the isolation well 28, the impurity is also ion-implanted into the scribe line region 16 around the semiconductor chip region 18 at the same time. As a result, an impurity region similar to the isolation well 28 is formed around each semiconductor chip region 18, and the semiconductor chip regions 18 are electrically isolated from each other.

According to the present embodiment, as in the first embodiment, the isolation well 28 is formed so as to intersect the scribe line region 16, and the same operational effect as the first embodiment is provided. In this embodiment, there is an advantage that it is particularly effective at the time of inspection such as an energization test. That is, in the energization test, the semiconductor chip area 18
The probe is brought into contact with the pads 24 and 26 of the semiconductor chip region 18. However, since each semiconductor chip region 18 is electrically cut off by the impurity region of the scribe line region 16, noise during the test affects the semiconductor chip regions 18 to each other. There is nothing to do. Therefore, the energization test can be accurately performed.

Further, the width of the scribe line region 16 is larger than the cutting grade blade width for cutting as a semiconductor chip, and the scribe line region 16 remains around each semiconductor chip region 18 even if it is divided into each semiconductor chip region 18. To do. Therefore, the semiconductor chip regions 18 are formed by the scribe line regions 16 in which impurities are ion-implanted.
Since it is surrounded by, it is possible to prevent external noise from affecting each element from the substrate and prevent malfunction of the entire semiconductor chip.

A semiconductor device according to the third embodiment of the present invention is shown in FIG. 3A is a plan view and FIG. 3B is X-.
It is a X'line sectional view. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description. In this embodiment, impurities are ion-implanted also in the scribe line region 16 to form an impurity region similar to the isolation well 28, and at the intersection of the isolation well 28 with the scribe line region 16, that is, in the semiconductor of the isolation well 28. Both end portions of the chip region 18 are wider than the other portions, and the separation well 28 and the scribe line region 16 are continuous via the wide portion 30.

In general, since the mechanical strength of the ion-implanted portion is lowered, both ends of the separation well 28 are apt to be chipped when the semiconductor chip is cut, and the chipping may cause the separation well 28 to be partially cut. is there. In this embodiment, since the wide portions 30 are provided at both end portions of the separation well 28, even if the semiconductor chip is cut into chips, the separation well 28 can be prevented from being partially cut.
As a result, the analog element area 20 and the digital element area 2
2 can be separated more reliably.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the present invention can be applied to a semiconductor device that needs to electrically cut off a specific element region from another element region regardless of whether it is a digital element or an analog element.

[0018]

As described above, according to the present invention, the first element region and the second element region are separated in the semiconductor layer between the first element region and the second element region of the semiconductor chip region. Therefore, an isolation well to which an impurity is added is formed, and the isolation well crosses the semiconductor chip region and reaches the scribe line region. Therefore, the area occupied by the isolation well in the semiconductor chip region decreases and the area of the element region increases. In addition, the signal line for input / output signals to / from the element region can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

 10 ... Silicon substrate 12 ... Silicon oxide film 14 ... Silicon layer 16 ... Scribe line area 18 ... Semiconductor chip area 20 ... Analog element area 22 ... Digital element area 24 ... Pad 26 ... Pad 28 ... Separation well 30 ... Wide part 60 ... Silicon Substrate 61 ... Silicon oxide film 62 ... Silicon layer 63 ... Scribing line area 64 ... Semiconductor chip area 65 ... Analog element area 66 ... Digital element area 67 ... Pad 68 ... Pad 69 ... Separation well

Claims (4)

[Claims] 1. A semiconductor device in which a semiconductor layer for forming a device is divided into a plurality of semiconductor chip regions by a scribe line region, and each semiconductor chip region has a first device region and a second device region, In the semiconductor layer between the first element region and the second element region, an isolation well doped with an impurity for isolating the first element region and the second element region is formed, A semiconductor device, wherein a well reaches the scribe line region across the semiconductor chip region. 2. The semiconductor device according to claim 1, wherein an impurity region to which impurities are added is formed in the scribe line region so as to surround the semiconductor chip region. 3. The semiconductor device according to claim 1, wherein the semiconductor layer is formed on an insulating layer, and the isolation well and the impurity region reach the insulating layer. 4. The semiconductor device according to claim 1, wherein the first element region is an analog element region, and the second element region is a digital element region. Semiconductor device.