JPH05291270A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the structure of elements and facilitate their manufacturing method by forming a metal layer in such a fashion that the metal layer may face the bottom of an embed layer connected to the bottom of a collector region. CONSTITUTION:There is formed a transistor layer which comprises an element isolated epitaxial layer 2 on a first conductivity type board 1. There are formed a first conductivity type base region 8B, a second conductivity type emitter region 8E, a collector region 8C and a second conductivity type embedded layer 4 connected to the bottom of the collector region 8C on the surface of this transistor. In this semiconductor device as described above, a metal layer 5 is formed in such a fashion that it may face the bottom of the embedded layer 4. This construction allows the bottom of the collector region 8C to be connected to the embedded layer which faces the metal layer 5, which reduces collector parasitic resistance to virtually zero. Therefore, signal switch over time is minimized while the circuit is operated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar transistor.

[0002]

2. Description of the Related Art As shown in FIG. 4, in the structure of a conventional bipolar transistor, an n-type diffusion layer 40 and a p-type diffusion layer 70 are formed on a P-type substrate 10, and further on these diffusion layers 40, 70. In addition, the epitaxial layer 20 isolated by the silicon oxide film 30a forms a transistor region. In this transistor region, the base region 80B, the emitter region 80E and the n-type diffusion layer 40 are formed.
A collector region 80C connected to is formed, and a base electrode 90B, an emitter electrode 90E and a collector electrode 90C are formed respectively.

[0003]

By the way, bipolar
In order to operate the transistor at high speed, the collector
It is necessary to reduce the product of raw resistance and base parasitic capacitance. this
Uses self-aligned technology to reduce base parasitic capacitance
The parasitic base area is being reduced by
Has reached the limit, while the collector parasitic resistance
N to reduce ⁺Even if the buried layer concentration is increased,
A new problem of autodoping during axial growth has occurred
We cannot expect a wide decrease in resistance.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which can operate at a high speed without complicating its element structure and whose manufacturing method is easy.

[0005]

In order to achieve the above object, the semiconductor device of the present invention is such that a transistor region formed of an element-separated epitaxial layer is formed on a first conductivity type substrate, and the transistor region is formed. A first conductivity type base region, a second conductivity type emitter region and a collector region on the surface layer of the second conductivity type, and a second region connected to the lower surface of the collector region.
In a semiconductor device having a conductive type buried layer, a metal layer is formed in contact with the lower surface of the buried layer.

[0006]

The metal layer in contact with the lower surface of the buried layer is connected to the collector region and the collector parasitic resistance becomes almost zero. Therefore, the signal switching time becomes short and the circuit operation becomes fast.

[0007]

1 is a schematic sectional view of an embodiment of the present invention.
The SiO ₂ film 3a is formed on the support substrate S via the insulating film 6.
To form the epitaxial layer 2 with element isolation,
A transistor region is formed. In the transistor region, a base region 8B and an emitter region 8E are formed on its surface layer. Further, n ⁺ is a collector region 8C reaching the buried layer 4 is formed, further on its n ⁺ buried layer 4 below, the metal layer 5 the buried contact with the n ⁺ buried layer 4 lower surface is formed. A base electrode 9B, an emitter electrode 9E and a collector electrode 9C are formed from the base region 8B, the emitter region 8E and the collector region 8C, respectively.

In this structure, the collector region 8C for drawing out the collector electrode 9C is connected to the n ⁺ buried layer 4 whose lower surface is in contact with the layer made of metal. Therefore, the collector parasitic resistance becomes almost zero. This has a high cutoff frequency and can shorten the signal switching time. As a result, in the embodiment of the present invention, the speed is increased about twice as fast as the conventional example.

FIG. 2 is a schematic cross-sectional view showing the manufacturing method of the embodiment of the present invention having the above-described structure over time. First, the n ⁺ buried layer 4 and the p ⁺ diffusion layer 7 are formed on the P-type silicon substrate 1.
Then, the n ⁻ epitaxial layer 2 is formed on the substrate [FIG. 2 (a)].

Next, using a well-known technique, the epitaxial layer 2 is element-isolated by the SiO ₂ film 3a serving as an isolation oxide film, and a transistor region is formed on the n ⁺ buried layer 4. [FIG. 2 (b)].

Next, a SiO ₂ film 3b is formed on the entire surface of the wafer, and base patterning, base diffusion, emitter patterning, emitter diffusion and collector patterning, and collector diffusion are performed using a known technique to form a base. A region 8B, an emitter region 8E and a collector region 8C are formed. Then, aluminum is applied to form the base electrode 9
B, the emitter electrode 9E, and the collector electrode 9C are formed.
In this way, first, the NPN transistor is formed on the P-type silicon substrate 1 [FIG. 2 (c)].

[0012] Next, add adhesive to the surface of the wafer.
The insulating substrate 7 is applied, and the supporting substrate is provided through the adhesive 7.
The silicon substrate 8 to be the above is bonded [FIG. 3 (a)]. Continued
Of the silicon substrate 1 on which the NPN transistor is formed.
From the back side, the silicon substrate 1 is selected using selective polishing.
Removed by polishing, and separated oxide film 3a from the surface of the silicon substrate
The thin film structure is left up to the surface position [FIG. 3 (b)].

Then, a metal is deposited on the back surface of the obtained substrate by a sputtering method, and NP is formed by photoetching.
A buried metal layer 5 is formed so as to cover the n ⁺ buried layer 4 region of the N transistor while leaving the metal. After that, an insulating film 6 serving as an adhesive is deposited on the embedded metal layer 5 and the polished back surface of the substrate, and the supporting substrate S is bonded onto the insulating film 6. Then, first, the silicon substrate 8 attached to the surface of the wafer is removed, and further the insulating film 7 on the bonding pad is removed to complete the semiconductor device of the embodiment of the present invention (FIG. 1).

[0014]

As described above, according to the semiconductor device of the present invention, the structure in contact with the lower surface of the collector region and the layer made of metal is formed. The parasitic collector resistance can be reduced.
As a result, high frequency and high speed can be realized.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating an embodiment of the present invention over time.

FIG. 3 is a schematic sectional view illustrating an embodiment of the present invention over time.

FIG. 4 is a schematic cross-sectional view showing a conventional example.

[Explanation of symbols]

1 ... P type silicon substrate 2 ... Epitaxial layer 3a, 3b ... Silicon oxide film 4 ... N ⁺ buried layer 5 ... Embedded metal layer 6, 7 ... Insulating film S, 8 ... Support substrate

Claims (1)

[Claims] 1. A transistor region comprising an element-separated epitaxial layer is formed on a first conductivity type substrate,
A semiconductor in which a first-conductivity-type base region, a second-conductivity-type emitter region and a collector region, and a second-conductivity-type buried layer connected to the lower surface of the collector region are formed in a surface layer of the transistor region. The semiconductor device is characterized in that a metal layer is formed in contact with the lower surface of the buried layer.