JP2010123986A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which elements 3 separated longitudinally and laterally by insulating members 2a in element, well, and circuit units, the semiconductor device having a high isolation breakdown voltage and being manufactured inexpensively without using an SOI substrate, and to provide a method of manufacturing the same. <P>SOLUTION: A semiconductor substrate 1 where the separation grooves 2 in which insulating members 2a are buried and the elements 3 are formed is made thin until bottoms of the insulating members 2a project from the side of a reverse surface 1b, and then the reverse surface 1b and a support 6 are joined together through an insulating layer 4. Consequently, projecting portions of the insulating members 2a are buried in the insulating layer 4, and adjacent regions of the semiconductor substrate 1 are electrically insulated by the separation grooves 2 and insulating layer 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a structure in which electrical isolation is performed in element units, well units, and circuit units in a chip, and a method for manufacturing the same.

  FIG. 5 is an explanatory diagram regarding a separation groove in a conventional SOI (Silicon On Insulator) wafer. FIG. 5A shows an SOI structure wafer J3 in which a single crystal silicon layer J2 is formed on a silicon oxide film J1 which is an insulating film. Then, as shown in FIG. 5B, a separation groove J4 reaching the silicon oxide film J1 embedded in the wafer J3 is formed from the surface of the single crystal silicon layer J2, and the inside of the separation groove J4 is formed inside the silicon oxide. If the insulating member J5 is buried, the adjacent region can be electrically insulated and separated by the separation groove J4 and the silicon oxide film J1 embedded in the wafer J3. Thereby, for example, if the CMOS is insulated and separated in units of wells, malfunction due to latch-up can be prevented. Further, even when different circuits made of MOS, bipolar, DMOS, etc. are integrated into a single chip to form a system, each circuit can be insulated and separated, so that a highly reliable system LSI can be manufactured.

  The separation groove J4 is generally formed by dry etching. However, since the variation in the thickness of the SOI layer J2 in the wafer J3 is large, all the grooves reach the silicon oxide film J1 over the entire surface of the wafer J3. In some cases, excessive etching must be performed. Therefore, as shown in FIG. 5C, in the thin region of the SOI layer J2, the bottom of the isolation groove J4 is etched laterally along the silicon oxide film J1, and the width of the bottom of the isolation groove J4 increases. Occurs. When the insulating member J5 is embedded in this state, as shown in FIG. 5D, the insulating material at the bottom of the separation groove J4 becomes thin, or a cavity J6 that is not embedded remains. In addition, since the constriction occurs in the shape of the separation groove J4 and the electric field concentrates there, there is also a problem that the separation breakdown voltage is reduced.

  In addition, as a method for manufacturing an SOI substrate (wafer), there are a SIMOX method in which oxygen ions are implanted, a wafer bonding method in which two wafers are bonded together through a silicon oxide film, and both methods are high in manufacturing cost. The SOI substrate is more expensive than a normal silicon wafer (bulk wafer). Therefore, there is a problem that the price of the element completion chip using the SOI substrate is also increased.

  In view of the above problems, the present invention has a high isolation breakdown voltage in a semiconductor device in which an element, a well, and an element having a structure in which vertical and horizontal directions are separated by an insulating member in a circuit unit, and further uses an SOI substrate. An object of the present invention is to provide a semiconductor device that can be manufactured at low cost and a manufacturing method thereof.

  To achieve the above object, according to the first aspect of the present invention, the element (3) formed on the surface (1a) side of the semiconductor substrate (1) is partitioned by the separation groove (2), and the semiconductor substrate (1) The back surface (1b) side of the semiconductor device is bonded to the support (6) through the insulating layer (4), and the insulating member (2a) embedded in the separation groove (2) is the back surface (1b). The protruding portion is characterized in that the protruding portion is embedded in the insulating layer (4).

  Thereby, since insulation isolation is performed by embedding the insulating member (2a) in the protruding separation groove (2) in the insulating layer (4), the thickness change of the insulating member (2a) in the separation groove (2) In addition, it is possible to have a configuration in which there is no constriction in the shape of the cavity and the separation groove (2). Therefore, a semiconductor device with high isolation breakdown voltage can be provided.

The invention according to claim 2 is characterized in that, in the invention according to claim 1, a metal (9) is provided between the semiconductor substrate (1) and the insulating layer (4).
Thereby, the semiconductor device using the metal (9) as a low resistance layer on the upper surface of the insulating layer (4) in the semiconductor substrate (1) can be provided.

  In the invention according to claim 3, the element (3) formed on the surface (1a) side of the semiconductor substrate (1) is partitioned by the separation groove (2) reaching the inside of the semiconductor substrate (1), and the separation groove ( 2) Preparing a semiconductor substrate (1) that is embedded with an insulating member (2a) and thinning the semiconductor substrate (1) until the bottom of the insulating member (2a) protrudes from the back surface (1b) side of the semiconductor substrate (1). And the back surface (1b) is joined to the support (6) through the insulating layer (4), and the protruding insulating member (2a) is embedded in the insulating layer (4). It has the 2nd process.

  According to this manufacturing method, since the insulating separation is performed by embedding the insulating member (2a) in the protruding separation groove (2) in the insulating layer (4), the insulating member (2a) in the separation groove (2) is provided. It is possible to have a configuration in which there is no constriction in the shape of the separation groove (2). Therefore, it is possible to provide a method for manufacturing a semiconductor device with high isolation breakdown voltage. Further, since it is not necessary to use an expensive SOI substrate, manufacturing cost can be reduced.

  As in the invention described in claim 4, as the insulating layer (4) of the invention described in claim 3, a silicon oxide film, a silicon nitride film, or a liquid insulating film formed by chemical vapor deposition is used. A film formed by solidifying after applying a material or a film including a non-conductive adhesive film can be used.

  As in the invention described in claim 5, as the support body (6) of the invention described in claim 3 or 4, any one of a mounting substrate, a silicon wafer, a glass substrate, a ceramic substrate, and a metal substrate is used. Can be used.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. It is a schematic sectional drawing of the semiconductor device of 2nd Embodiment. It is a schematic sectional drawing of the semiconductor device of 3rd Embodiment. It is a schematic sectional drawing of the semiconductor device of 4th Embodiment. It is a schematic sectional drawing regarding the insulation isolation | separation of the semiconductor device by the conventional SOI wafer.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the semiconductor device of this embodiment in the order of manufacturing steps. As shown in FIG. 1D, the semiconductor device according to the present embodiment has an SOI structure, and adjacent regions in the semiconductor substrate 1 are electrically connected to each other by the separation groove 2 formed in the semiconductor substrate (bulk wafer) 1. It has an isolated structure. The configuration will be described below.

  An element 3 and a separation groove 2 are formed on the semiconductor substrate 1, and the element 3 is formed on the surface 1 a side of the semiconductor substrate 1. Here, as the semiconductor substrate 1, a silicon wafer or a silicon carbide wafer can be used. The isolation trench 2 can be formed in element units, CMOS well units, or circuit units, and divides these regions. Further, as the element 3, for example, a CMOS, a bipolar transistor, a power transistor, or the like can be formed.

  Further, the size of the isolation trench 2 can be, for example, a width of 2 μm and a depth of 20 μm. The depth is determined by the element structure and must be deeper than the active region of the element 3. An insulating member 2a is embedded in the isolation groove 2. In this embodiment, the side wall and the bottom of the isolation groove 2 are covered with a silicon oxide film, and the inside thereof is embedded with polycrystalline silicon. Further, the insulating member 2a in the separation groove 2 protrudes from the semiconductor substrate 1 on the back surface 1b of the semiconductor substrate 1, and the protruding dimension is preferably 0.1 to 2 μm, for example.

  An insulating layer 4 is formed on the back surface 1 b of the semiconductor substrate 1. Specifically, the protruding portion of the insulating member 2 a in the separation groove 2 is embedded in the insulating layer 4. The surface on which the insulating layer 4 is formed is bonded to the support 6 via an adhesive 5.

  Here, as the insulating layer 4, for example, a silicon oxide film formed by chemical vapor deposition, a silicon nitride film, a film formed by solidifying after applying a liquid insulating material, A conductive adhesive film or the like can be used. As the support 6, a mounting substrate such as a printed wiring board, a silicon wafer, a glass substrate, a ceramic substrate, a metal substrate, or the like can be used. Further, as the adhesive 5, it is preferable to use an adhesive that has little distortion and can absorb stress, and is preferably non-conductive.

  Next, a method for manufacturing a semiconductor device having such a configuration will be described with reference to the example shown in FIG. First, a semiconductor substrate (bulk wafer) 1 is prepared, and as shown in FIG. 1A, a separation groove 2 that reaches the inside of the semiconductor substrate 1 is formed by dry etching. Then, after a silicon oxide film is formed on the side walls and bottom of the isolation trench 2 by thermal oxidation, the inside of the silicon oxide film is buried with polycrystalline silicon. Thereafter, the element 3 is formed.

  Next, as shown in FIG. 1B, the supporting substrate 8 is bonded to the surface 1a of the semiconductor substrate 1 on which the element (device) 3 and the separation groove 2 are formed using an adhesive 7. . This is to prevent damage to the semiconductor substrate 1 in the steps described later. Here, as the supporting substrate 8, for example, a silicon wafer, a glass substrate, a ceramic substrate, a metal substrate, a tape member, or the like can be used.

  Next, as shown in FIG. 1C, the thickness of the semiconductor substrate 1 is reduced until the bottom of the separation groove 2 protrudes from the back surface 1b side of the semiconductor substrate 1 (hereinafter referred to as “thinning”). In the thinning method, first, the separation groove 2 is thinned to just before the separation groove 2 is exposed by grinding, and then the separation groove 2 is projected by chemical mechanical polishing. This chemical mechanical polishing is further polished after the separation groove 2 is exposed under the polishing conditions with a high selectivity between the oxide film and silicon, so that the insulating member 2a in which the separation groove 2 is embedded becomes the back surface of the semiconductor substrate 1. Finish in a shape that protrudes beyond 1b (first step). Here, as the abrasive, for example, an organic alkali solution mixed with colloidal silica can be used, and as the abrasive cloth, a polyester nonwoven fabric can be used.

  Next, as shown in FIG. 1D, the insulating layer 4 is formed on the back surface 1b of the thinned semiconductor substrate 1, and then bonded to the support 6 with the adhesive 5 (second step). Here, if the support body 6 is a printed circuit board, it may be bonded after being cut into chips. Moreover, if the support body 6 is a silicon wafer, a glass substrate, a metal substrate, etc., it may be cut into chips and then joined to the support body 6, or after the semiconductor substrate 1 and the support body 6 are joined in the wafer state. It may be cut into chips and then mounted on a printed circuit board or the like.

  The support substrate 8 is peeled off after the support 6 and the semiconductor substrate 1 are joined. The method can be peeled off by irradiating with ultraviolet rays using, for example, an adhesive 7 whose adhesiveness decreases when irradiating the supporting substrate 8 and the semiconductor substrate 1 with ultraviolet rays. At that time, as the supporting substrate 8, it is necessary to use a member that transmits ultraviolet rays, and for example, a glass substrate can be used.

  Through the above steps, the element 3 formed on the semiconductor substrate 1 is separated by the insulating layer 4 made of a silicon oxide film or the like, and a semiconductor device having an SOI structure is completed.

  By the way, according to the present embodiment, the insulating member 2a embedded in the separation groove 2 is formed in a shape that bites into the insulating layer 4 interposed between the semiconductor substrate 1 and the support 6. The insulating member 2a in the separation groove 2 is not changed in thickness, hollow, and the shape of the separation groove 2 is not constricted. Accordingly, it is possible to provide a semiconductor device having a structure separated with high isolation breakdown voltage in element units, CMOS well units, or circuit units, and a method for manufacturing the same. In addition, since the SOI structure is formed by using an inexpensive bulk wafer instead of an expensive SOI substrate, a semiconductor device with a low manufacturing cost and a manufacturing method thereof can be provided.

  Note that the separation groove 2 may be filled with only silicon oxide by CVD (Chemical Vapor Deposition). Moreover, you may form the shape which the isolation | separation groove | channel 2 protruded by the etching with high selection ratio instead of grinding | polishing. Further, if the adhesive 5 used for bonding the insulating layer 4 formed on the back surface 1b of the semiconductor substrate 1 and the support 6 is non-conductive, the insulating layer 4 is not necessarily required.

(Second Embodiment)
FIG. 2 is a schematic cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 2B showing a semiconductor device completed using the invention of the present embodiment, the structure is a metal between the back surface 1b of the semiconductor substrate 1 and the insulating layer 4 as compared with the first embodiment. 9 is different. Therefore, hereinafter, this difference will be mainly described in the manufacturing method.

  First, the steps up to the first step of the first embodiment are performed in the same manner as shown in FIGS. Next, as shown in FIG. 2A, Al (aluminum), Cu (copper), W (tungsten), and the like on the back surface 1b of the thinned semiconductor substrate 1 by a method such as vapor deposition, sputtering, and CVD. A metal 9 such as Ti (titanium) is formed. Next, the metal 9 on the insulating member 2a of the separation groove 2 is removed by polishing. This is performed by selective polishing using the silicon oxide at the bottom of the separation groove 2 as a stopper and removing the metal 9 thereon. Then, as shown in FIG. 2B, the second step of the first embodiment is performed. Through the above steps, an SOI structure semiconductor device in which the metal 9 is interposed between the back surface 1b of the semiconductor substrate 1 and the insulating layer 4 is completed.

  By the way, according to the present embodiment, the same effects as those of the first embodiment can be exhibited. Furthermore, the metal 9 having a low resistance value can be easily provided on the lower surface of the element 3 (on the insulating layer 4 formed on the support 6), and the performance of the bipolar element can be improved.

  This point will be described in detail below. The characteristics of the bipolar element are improved by forming a low resistance layer (low resistance layer) on the lower surface of the SOI layer (upper surface of the silicon oxide layer). However, if this low resistance layer is to be formed from a metal (Al, W, etc.), the metal is melted or the metal atoms are converted into silicon by a high-temperature heat treatment (for example, about 1170 ° C.) during the subsequent device formation. Or diffuse inside. Therefore, it is difficult to manufacture a device (element) on a wafer having a structure in which metal is embedded in an SOI substrate.

  In addition, in order to form such a low resistance layer on an SOI substrate on which an element is formed in advance, a high concentration diffusion layer is formed by thermal diffusion. At this time, Al of the element already formed is formed. Such a metal wiring is adversely affected by being melted or cut by heat. However, as in this embodiment, if the low resistance layer is formed of the metal 9 and insulated after the element 3 is formed on the semiconductor substrate 1, the low resistance layer can be appropriately formed on the substrate having the SOI structure. The performance of the bipolar element can be improved.

  The contents not described such as specific examples of each member are the same as those in the first embodiment.

(Third embodiment)
FIG. 3 is a schematic cross-sectional view showing the semiconductor device of this embodiment in the order of the manufacturing process. As shown in FIG. 3D, the configuration of the semiconductor device of this embodiment is the same as that of the first embodiment, but the method of thinning in the first step is different. Hereinafter, in the manufacturing method, portions different from the first embodiment will be mainly described.

  First, as shown in FIG. 3A, hydrogen ions are implanted into a semiconductor substrate (bulk wafer) 1 in which the element 3 and the isolation groove 2 are formed. Hydrogen ions are implanted from the surface 1a side of the semiconductor substrate 1 as indicated by an arrow A in FIG. By this ion implantation, an ion-implanted layer (hereinafter referred to as a mud layer) 10 in which hydrogen and crystal defects are segregated at a high density is formed. The depth of the mud layer 10 from the surface 1a is determined by the acceleration voltage for ion implantation. In addition, the depth of the mud layer 10 must be deeper than the depth of the separation groove 2.

  Next, as shown in FIG. 3B, the semiconductor substrate 1 is peeled off by the mud layer 10 by performing heat treatment (about 700 ° C.) after being bonded to the supporting substrate 8. Regarding the separation by this hydrogen ion implantation, reference can be made to the invention described in JP-A-5-211128. After peeling, as in the first embodiment, the peeling surface is polished or etched to project the separation groove 2 (first step). Thereafter, the second step is performed in the same manner as in the first embodiment, and a semiconductor device having the same configuration as in the first embodiment is completed.

  By the way, according to the present embodiment, the same effects as those of the first embodiment can be exhibited. In addition, the back surface 1b of the semiconductor substrate 1 can be collectively reduced to the same thickness. The contents not described such as specific examples of each member are the same as those in the first embodiment.

  Further, by applying the second embodiment to this embodiment, after the first step, metal is formed on the back surface 1b of the semiconductor substrate 1 to remove the metal on the insulating member 2a of the separation groove 2, and then You may perform a 2nd process.

(Fourth embodiment)
FIG. 4 is a schematic cross-sectional view of the semiconductor device of this embodiment. In the semiconductor device of the first embodiment, the insulating layer 4 is provided on the entire back surface 1b of the semiconductor substrate 1, whereas the semiconductor device of this embodiment is different in that the insulating layer 4 is partially provided. Hereinafter, differences from the first embodiment will be mainly described. As shown in FIG. 4B, the insulating layer 4 is provided in a part of the region between the semiconductor substrate 1 and the support 6 with the region partitioned by the separation groove 2 as a unit. The insulating layer 4 is not provided in this region. In some regions, the insulating member 2 a protruding from the separation groove 2 is embedded in the insulating layer 4.

  Next, the manufacturing method will be described. First, the steps up to the first step of the first embodiment are performed in the same manner as shown in FIGS. Thereafter, a film made of an insulating material for forming the insulating layer 4 is formed on the entire back surface 1b.

  Next, as shown in FIG. 4A, current is passed in the vertical direction, that is, the film made of an insulating material in the region of the element 3 that is electrically connected to the support 6 is peeled off to insulate the opening 11. Layer 4 is formed. As a peeling method, a resist material is applied as a mask at the time of peeling, patterning is performed, and a film made of an insulating material can be removed by dry etching or wet etching. The alignment key at the time of patterning may be formed in the scribe region or the like in the formation process of the separation groove 2.

  Subsequently, as shown in FIG. 4B, the surface of the semiconductor substrate 1 on which the insulating layer 4 is formed and the support 6 are joined using the conductive adhesive 5 (second step). Thereby, the conductive adhesive 5 is filled in the opening 11 of the insulating layer 4. As the support 6, a silicon wafer doped with a dopant impurity at a high concentration can be used, and the resistivity is desirably 0.01 Ωcm or less. In addition, as the conductive adhesive 5, for example, solder or a resin containing a metal filler can be used. As described above, a semiconductor device that partially secures conduction with the support 6 is completed.

  By the way, according to the present embodiment, the same effects as those of the first embodiment can be exhibited. Further, the element 3 in the region where the insulating layer 4 is not provided, that is, the region where the opening 11 is formed, can be electrically connected to the support 6, and the region where the insulating layer 4 is provided has the element 3 having the SOI structure. Can be formed. That is, it is possible to provide a semiconductor device having a structure in which a region that is electrically insulated and separated and a region that is electrically connected to the support 6 are mixed, and a method for manufacturing the semiconductor device. If such a structure is to be formed when an SOI substrate is used, a complicated process such as filling the silicon single crystal after removing the insulating layer 4 by etching is required. According to the form, such a structure can be easily formed.

  In this example, the support 6 is bonded after the insulating layer 4 is formed on the semiconductor substrate 1. However, the insulating layer 4 is formed on the support 6 and the support 6 is connected to the semiconductor substrate 1. You may align and join. Further, as the support 6, a mounting board such as a printed wiring board or a metal board can be used. In addition, contents not described such as specific examples of other members are the same as those in the first embodiment.

  Further, the second embodiment is applied to the present embodiment, and after the first step, a metal is formed on the back surface 1b of the semiconductor substrate 1 to remove the metal on the separation groove 2, and then the second step. May be performed. Further, the third embodiment may be applied to the present embodiment, and the thinning in the first step may be performed using hydrogen ion implantation.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Front surface 1b Back surface 2 Separation groove 2a Insulating member 3 Element 4 Insulating layer 6 Support body 8 Supporting substrate 9 Metal 10 Ion implantation layer 11 Opening

Claims (5)

The element (3) formed on the front surface (1a) side of the semiconductor substrate (1) is partitioned by the separation groove (2), and on the back surface (1b) side of the semiconductor substrate (1) via the insulating layer (4). A semiconductor device joined to a support (6),
The insulating member (2a) embedded in the separation groove (2) protrudes from the back surface (1b), and the protruding portion has a shape embedded in the insulating layer (4). A featured semiconductor device.   2. The semiconductor device according to claim 1, wherein a metal (9) is provided between the semiconductor substrate (1) and the insulating layer (4). An element (3) formed on the surface (1a) side of the semiconductor substrate (1) is partitioned by a separation groove (2) reaching the inside of the semiconductor substrate (1), and the inside of the separation groove (2) is an insulating member. A step of preparing a buried one in (2a);
A first step of thinning the semiconductor substrate (1) until the bottom of the insulating member (2a) protrudes from the back surface (1b) side of the semiconductor substrate (1);
A second step in which the back surface (1b) is joined to the support (6) through an insulating layer (4), and the protruding insulating member (2a) is embedded in the insulating layer (4); A method for manufacturing a semiconductor device, comprising:   The insulating layer (4) is a silicon oxide film formed by chemical vapor deposition, a silicon nitride film, a film formed by solidifying after applying a liquid insulating material, or a non-conductive film The method for manufacturing a semiconductor device according to claim 3, further comprising an adhesive film.   The manufacturing method according to claim 3 or 4, wherein the support (6) is any one of a mounting substrate, a silicon wafer, a glass substrate, a ceramic substrate, and a metal substrate.

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