JPH05284152A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To constitute a stable phase locked loop circuit with a loop filter by selecting and reading the information every time information speed and conversion ratio are changed and controlling the information by using a D/A converter. CONSTITUTION:The phase locked loop circuit 13 outputs a clock synchronized with the sample clock 11 of the formula, a speed converting clock signal S15 being f1.alpha/beta, and a speed converting data retiming clock signal S6. A frequency divider 13 receives the clock S15, and outputs a phase comparing signal S10 which is frequency-divided to be the frequency of f1/beta. On the other hand, a block pulse generator 14 receives a clock S5 to be frequency-divided and outputs a phase comparing signal S16 being f1/beta. A phase comparator 6 receives the signals S16 and S10 and outputs a signal S7. A voltage control filter 9 for removing the higher harmonic of the signal S7 receives the information speed and coding ratio information S17 from the outside at a data storage circuit 10 and outputs data S18. A D/A converter 11 receives the S18 and outputs an analog voltage to the filter 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit used in a speed conversion circuit in a digital transmission system.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a phase synchronization circuit used in a circuit system having a speed conversion circuit and a latch circuit at its output section has a phase synchronization circuit 23 and a phase synchronization circuit 23 used in a speed conversion section 21. It is composed of a frequency divider 106 and a phase synchronization circuit 24 used in the latch unit 22. The phase synchronization circuit 23 is composed of a VCO 113, a frequency divider 109, a phase comparator 108 and a loop filter group 112 in order to synchronize the phase with the clock S5 of the input data signal S1. The oscillation signal S9 is frequency-divided by the frequency divider 106 and supplies a desired frequency to the speed converter 21. On the other hand, the phase synchronization circuit 24 includes a VCO 116, a frequency divider 110, and a phase comparator 10.
7 and a loop filter group 115, and supplies to the latch circuit 5 an oscillation signal that is in phase with the frequency-divided signal S106 output from the frequency divider 106 in the preceding stage. In addition, the frequency divider 11
0 outputs a plurality of frequency division signals when a plurality of speed conversion frequencies are required and is supplied to the latch circuit 5.

Here, as shown in FIG. 3, the loop filter groups 112 and 115 are switched by a plurality of switches 111A and 111B provided for input and output signals S108 and S109 in order to correspond to a plurality of frequency conversion frequencies. Loop filter 112-1 to 112-N. This loop filter 112-1 ~
The switching of 112-N is controlled by an external control signal S119.

[0004]

The speed conversion circuit using the conventional phase locked loop circuit is selected by selecting an overhead added to an arbitrary information speed at a rate of several percent of the information speed or by adding an error correction code. The transmission rate is many times higher than the original information rate. Also, the clock frequency used in the speed conversion circuit becomes very large depending on the selection of the overhead and the addition rate of the correction code.
Normally, the band of the loop filter is set to a few tenths to a few hundredths of the phase comparison frequency, so the loop loop is changed according to the change of the phase comparison frequency every time the information rate and the conversion ratio change. Since it is necessary to optimize the band of the filter, there is a drawback that various loop filters must be used. Further, there is a drawback that another group of phase synchronization circuits must be provided in order to establish synchronization with the latch clock.

[0005]

SUMMARY OF THE INVENTION The phase locked loop circuit of the present invention is adapted to input an arbitrary information speed conversion input data signal f1H.
In a phase synchronization circuit used for a speed conversion circuit and a latch circuit for speed conversion to an arbitrary conversion ratio β / α synchronized with z, a clock signal (β /
alpha) - f1 Hz and sample number 2 ^N of the sample clock ^{2 (N-1) · f1} · R / 2 · α / β ( although, N is the corresponding number of samples = 2 ^N a positive integer, R represents BPSK In order to obtain R = 2 in modulation, R = 1 in QPSK modulation (A.
The voltage controlled oscillator 8 which oscillates at the center frequency of S · α) · f1 / βHz (A and S are frequency division ratios which will be described later) and the oscillation frequency of 2 · 2 ^(N−1) · f1 · R / 2 · 1 / A frequency divider 7 that can be set to α / β frequency division, 1 / S frequency divider 7 that can be set to a sampling clock of 2 ^N samples, and f1 / β phase 1 / α that can be set to the comparison frequency
A frequency divider 13 for dividing, a block pulse generator 14 capable of setting a division ratio 1 / β according to conversion comparison β / α, a phase comparator 6, and a band of a loop filter converted by a control voltage. And a voltage control filter 9 that can be used.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Figure 1
In, the speed conversion input data signal (f1 bit / S)
S1 is retimed by the speed conversion input clock (f1 Hz) S5 in the retiming circuit 1 and input to the speed conversion circuit 2 with the conversion ratio β / α. Speed conversion circuit 2
Then, f1 · (α
The speed is converted by the speed conversion clock signal S15 of / β) Hz, and is input to the shift register 4 after retiming by the retiming circuit 3. In the shift register 4, the data signal S is sent to the latch circuit 5 which is converted from serial to parallel.
12 is output. In the latch circuit 5, the data signal S12
The sample clock signal S11 and the latch clock S
It latches at 14, and outputs a latch circuit output data signal S13.

On the other hand, the voltage controlled oscillator 8 which oscillates at the center frequency of (A.S..alpha.). F1 / .beta.Hz having the coefficients of the frequency division ratios A and S described later outputs the voltage controlled oscillator output S9 and outputs 1 The frequency is divided by the frequency divider 12 which divides the frequency by / A. further,
(S · α) · f1 / βHz latch clock S14
Is input to the frequency divider 7 and the latch circuit 5 for 1 / S frequency division. Sample clock S11, (1) to become ^{2 0 · f1 · R / 2α} · β, 2 1 · f1 · R / 2 · α · β, ...... 2 (N-1) · f 1 · R / 2 · α · β (1) where ^N corresponds to S = number of samples = 2 ^N and R is BP
R = 2 and R = 1 in SK modulation and QPSK modulation, respectively.

The phase synchronization circuit 13 is a sample of the equation (1).
A clock synchronized with the clock S11, the speed conversion clock signal S15 having f1 · (α / β) Hz, and the clock signal S6 synchronized with the speed conversion data retiming clock signal S6 is output. In response to the speed conversion clock S15, the frequency divider 13 divides the frequency to f1 / βHz and outputs it as the phase comparison signal S10. On the other hand, the block pulse generator 14 receives the speed conversion input clock S5, divides it, and outputs a phase comparison signal S16 of f1 / βHz. The phase comparator 6 receives the phase comparison signal S16 and the phase comparison signal S10, compares them in phase, and outputs a phase comparator output signal S7. The voltage control filter 9 for removing the harmonic component of the phase comparator signal S7 receives the information speed and the information of the code density from the outside in the ROM of the data storage circuit 10 as an address, and receives the data selected from the address. Output as S18. The D / A converter 11 receives S18, performs D / A conversion, and outputs the analog voltage to the voltage control filter 9, whereby the D / A converter 11 is controlled by an optimum filter and is in phase synchronization.

[0009]

As described above, in the phase locked loop circuit of the present invention, whenever the information speed and the conversion ratio change arbitrarily, the voltage control filter corresponding to the change of the phase comparison frequency by the information, and the filter A data storage circuit that stores the control voltage and its information is selectively read out and controlled by using a D / A converter, so that one loop filter can stabilize phase synchronization over various information speeds and conversion ratios. A circuit can be configured. In addition, by providing a frequency divider that divides the output of the voltage controlled oscillator to the latch clock and a frequency divider dedicated to sampling, the speed conversion clock and sampling clock can be extracted, and another phase synchronization like the conventional one can be performed. There is an effect that a circuit is unnecessary and the circuit scale can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a conventional phase locked loop circuit.

FIG. 3 is a block diagram of a conventional loop filter group of essential parts.

[Explanation of symbols]

 1,3 retiming circuit 2 speed conversion circuit 4 shift register 5 latch circuit 6 phase comparator 7, 12, 13 frequency divider 8 voltage controlled oscillator 9 voltage control filter 10 data storage circuit 11 digital / analog conversion circuit 13 phase synchronization circuit 14 block pulse generator

Claims (2)

[Claims] 1. A phase synchronization circuit used for a speed conversion circuit and a latch circuit for speed conversion into an arbitrary conversion ratio β / α synchronized with an input arbitrary information speed conversion input data signal f1 Hz, which is used for the speed conversion circuit. Clock signal (β / α) · f1 Hz and 2 ^N samples
Clock 2 ^(N-1) , f1, R / 2, α / β (however, N
Is a positive integer and corresponds to the sample number = 2 ^N , and R is BPSK
A voltage control oscillator 8 that oscillates at a center frequency of (A · S · α) · f1 / βHz (A and S are frequency division ratios described later) for obtaining R = 2 in modulation and R = 1 in QPSK modulation. , A frequency divider 7 that divides this oscillation frequency by 1 / A that can be set to 2/2 ^(N-1) · f1 · R / 2 · α / β and a sampling clock with 2 ^N samples 1 / S frequency divider 7 that can be set, 1 / α frequency divider 13 that can be set to a phase comparison frequency of f1 / β, and a division ratio of 1 according to conversion comparison β / α Block pulse generator 1 that can be set to / β
4, a phase comparator 6, and a voltage control filter 9 capable of converting the band of the loop filter with a control voltage. 2. A ROM in which a control system of the voltage control filter stores data of a control voltage corresponding to an information rate and a conversion ratio from the outside, and a D / A conversion of the output of the ROM as a control voltage. 2. The phase locked loop circuit according to claim 1, further comprising an A converter, the band of which is controlled by this control voltage.