JP2556032B2 - Binary-Transversal Filter - Google Patents

Description

DETAILED DESCRIPTION [Overview] A binary transversal filter that shapes a distorted waveform of received data “1/0” in the time domain, and particularly a shift register that outputs serial input data in parallel for waveform shaping,
A PLL that generates and outputs a sampling frequency Nf ₀ to the shift register based on the input clock f ₀ , an address counter that divides the output Nf ₀ and outputs an n-parallel address, and an output of the shift register A ROM that stores a fixed number of waveform shaping data in advance and reads it by n parallel addresses of the output of the address counter, and D / A converts the output data to remove the harmonics Nf ₀ generated during the conversion. Then, in the binary transversal filter consisting of a smoothing filter for smoothing and outputting the signal, the sampling multiple N is switched by 2 ^{1 in} binary number every time the transmission rate of the input data exceeds 2 times. By making the sampling frequencies in the change range equal, the position of the harmonics generated at the output of the D / A converter is always fixed.
Only the type of smoothing filter is required, eliminating the need for replacement.

[Industrial applications]

The present invention relates to a binary transversal filter that shapes a distorted waveform of received input data “1/0” in the time domain, and in particular, a shift register that outputs serial input data in parallel for waveform shaping, and a clock of input data. A PLL that uses f ₀ as a reference input and outputs N (= 2 ⁿ ) times NF ₀ as the sampling frequency of the input data, and an address counter that divides the output Nf ₀ of the PLL and outputs n parallel addresses. And a ROM for writing and storing the waveform shaping data of the parallel output of the shift register in advance and reading the n parallel output of the address counter as an address, and the output data read from the ROM is D / A converted and output through a smoothing filter. Binary transversal filter BT configured as
It is about the improvement of F.

In order to obtain the data shaped into the correct waveform as the desired analog output from the received data with the binary waveform distortion displayed as "0" and "1", first the data that has undergone the waveform distortion is input. It is supplied to a binary transversal filter to obtain waveform-shaped data, and then the digital output data D is converted into an analog signal A by request.
The harmonic generated in the output at the time of this D / A conversion is removed by a high-frequency cutoff filter and the smoothed desired analog signal is output, but in this case, the smoothing filter for harmonic removal is It is desirable that the same smoothing filter is fixedly used even if the transmission rate of the input data changes more than twice.

[Conventional technology]

Conventional binary transversal filter (BT
An example of the structure of (F) is shown in the block circuit diagram of FIG. 4, and the necessity of smoothing is shown in the explanatory diagram of FIG.

In FIG. 4, 1 is a phase locked loop PLL circuit, 2 is an address counter, 3 is a shift register, 4 is a read-only storage device ROM, 5 is a digital-analog converter D / A converter, and 6 is a low-pass filter. It is a smoothing filter with a high frequency cutoff.

Conventionally, in the PLL circuit 1, the input clock of the frequency f ₀ sent together with the serially received data is used as the reference input of the PLL, and the rate f ₀ of the input data is N (= 2 ⁿ ) times as large. A clock of frequency Nf ₀ is created, and an output clock of the frequency Nf ₀ is used as a sampling signal for input data to be waveform-shaped. Normally, N of the sampling frequency Nf ₀ must be a value larger than 2, but this N value has been fixed in the past. Here, as an example, FIG. 4 per case of N = 4 = 2 ^2, will be described with reference to FIG. 5. The address counter 2 divides the sampling frequency Nf ₀ of the output of the PLL circuit 1 (2 bits when N = 4 = 2 ² ) and matches one of the output signals with the clock f ₀ of the input data. The signal is given as the shift clock of the serial-parallel conversion shift register 3. The input of the shift register 3 is binary serial data.

A certain number of parallel outputs of the shift register 3 and n parallel outputs of the address counter are input to the ROM 4 of the read-only storage device as a read code. Corresponding to this code, the ROM 4 reads the stored data of the result obtained by multiplying n coefficients for waveform shaping and the addition thereof in advance, and converts it into an analog signal by the D / A converter 5. The harmonics Nf ₀ of the output signal generated during the conversion are cut off by the smoothing filter 6 that cuts through the high band and cuts off in the high band, and the required smoothed output signal is obtained. The output of the D / A converter 5 at this time is the fifth
As shown in the explanatory diagram of the drawing, since unnecessary high-frequency components are included in addition to the necessary shaped signal data, the smoothing filter 6 blocks the higher harmonic components. The problem at this time is that the BTF is a synchronous type that operates in synchronization with the input clock when the speed (clock) of the received input data changes, so the circuit configuration up to the D / A converter 5 is changed. Although not necessary, the smoothing filter 6 after that must be replaced with another filter having a different frequency characteristic.

FIG. 5 (a) is a D / A conversion in the case where the frequency of the input clock of the conventional BTF of FIG. 4 is f ₀ and the division ratio N of the peripheral force frequency Nf ₀ of PLL1 is N = 4. 3 shows the spectral characteristics of the output of the container 5. The horizontal axis represents the frequency with the frequency f ₀ of the input clock as a unit, and the vertical axis represents the output level of the harmonic component of the output signal data. Harmonic components are generated around frequencies of 4f ₀ , 8f ₀ , 12f ₀ ···, and in order to remove these harmonic components, there is a low-pass and high-frequency cutoff frequency characteristic as shown in the figure. It is necessary to have a smoothing filter 6.

In the case of FIG. 5 (b), where the transmission speed f ₀ of the input data of the BTF changes to the higher side, which is 2f ₀ , which is twice f ₀ in the case of FIG. 5 (a), N = 4 Is fixed and does not change, so that the spectrum characteristic of the output of the D / A converter 5 changes from the position of 4f ₀ to the position of 8f ₀ of the center of the first harmonic, as shown in FIG.
In this case, although not all shown, the harmonic components are 8f ₀ and 16f _0.
・ ・ And appears every 8f ₀ . In order to block this harmonic, the output has a flat frequency characteristic up to 2f _{0 in} (b) of the figure, which is different from the case of (a) in the figure, and the output drops at 2f ₀ or above. Therefore, the smoothing filter 6 having a frequency characteristic that cuts off most of the harmonics of the frequency 8f ₀ must be used.

[Problems to be solved by the invention]

As described above, the conventional BTF requires another smoothing filter 6 having different frequency characteristics of high-frequency cutoff and low-frequency cutoff every time the transmission speed (clock) of the input data changes, and the input data transmission There was a problem that the smoothing filter 6 had to be replaced each time the speed changed. Further, the analog smoothing filter 6 composed of analog elements has a drawback that the configuration is not simple.

The purpose of the present invention is to transmit the input data (clock).
Changes, and the change range is 2 of the input data clock.
Even if it becomes more than twice, it is necessary to use a smoothing filter with the same frequency characteristic, and to realize a BTF of digital processing that does not require replacement of the smoothing filter each time.

[Means for solving problems]

The basic configuration of the BTF of the present invention (the principle configuration diagram of FIG. 1) for achieving the above object is configured based on the general description given below.

Consider a case where the input data clock fluctuates between f _{0 and} 2f ₀ . At this time, the maximum output frequency of the PLL is set to 16f ₀ . Further, the sampling process for shaping the waveform of the input data requires at least twice the clock of the input data clock, so sampling is performed at 4 times the input clock.
Do more than double.

When the input data clock is f _{0 to} 2f ₀ , the sampling frequency is 8f _{0 to} 16f ₀ . Therefore, the frequency division ratio N of the PLL output Nf ₀ with respect to the input clock f ₀ is 8 = 2 ³ . In this case, the number of parallel output signals of the address counter is three,
The output of the selector is one of them. The three output signals of the address counter are shown in a time chart chart as shown in FIG. The output of the selector in this case is one of the output signals of the address counter (f ₀ ~
2f ₀ ) is selected. Next, when the input data clock is 2f _{0 to} 4f ₀ , the sampling frequency is 8f _{0 to} 16f ₀ . At this time, the frequency division ratio N of the PLL is 4
= 2 ² The number of parallel output signals of the address counter is three, which is the same as that of FIG. 6 (a) as shown in FIG. 6 (b), but the output of the selector is one of them (2f). _{0 ~4f 0)} is selected.

Regarding the smoothing filter, in the case where the input data clock in the above example is f _{0 to} 2f ₀ , since the sampling frequency is 8f _{0 to} 16f ₀ , the harmonics of 8f ₀ or more of the output of the D / A converter are It must be able to be cut and pass flat up to the signal 2f ₀ .

When the input data clock in the above example is 2f _{0 to} 4f ₀ , the sampling frequency is 8f _{0 to} 16f ₀ , so the harmonics above 8f ₀ of the D / A converter output can be cut and the signal 4f ₀
Must be flat and passable.

Therefore, when using the circuit of such BTF, if the input data clock is changed between f ₀ ~4f ₀ is made cut 8f ₀ or more outputs of the D / A converter, flat to 4f ₀ It suffices if there is only one type of smoothing filter that can pass.

The above description is generally expressed as the table shown in FIG.

Generally, in the phase locked loop circuit (11) that outputs the output frequency Nf ₀ of N times (= 2 ⁿ times, n is an integer) with the clock frequency f ₀ of the input data as the reference input, at the speed of the input data. A certain clock frequency f is from the reference value f ₀ to 2
^When changing up to ^n-2 f ₀ , the change is up to 2 times each 01,02
If the frequency is within the range of n-3, the frequency division ratios N are 2 ^n-1 and 2 ^{n-2, respectively.}
... 2 ² and is constant, each time more than its 2-fold change range,
The external switch 17, since N is switched 2 ^one by one binary number, the sampling frequency Nf ₀ is ^{_{2 n-1 f 0 ~2 n}} f 0 becomes an output frequency of the phase-locked loop circuit (11), the table As shown in the sampling frequency column of FIG. 7, it is always constant. Therefore, the harmonic component generated as the output signal of the D / A conversion (15) appears at the same position. Therefore, the smoothing filter corresponding to the change of the input data transmission rate from f ₀ to 2 ^n-2 f ₀ has a frequency of 2 ^n-2.
flat to f _0, would be the if there is a filter one of the frequency characteristic of cutting the 2 ^n-1 f ₀ or more.

Note that n connections between the address counter 12 (frequency divider) and the selector 18 and the shift register 13 from the selector 18 are connected.
One output line to is as shown in FIG. 8 of the accompanying drawings.

Based on the above description, the basic configuration of the BTF of the present invention is
As shown in the principle configuration diagram of FIG. 1, a phase-locked loop circuit that generates and outputs a sampling frequency Nf ₀ that is N times as large as 2 ⁿ times with a clock frequency f ₀ of received data of serial input as a reference input ( 11) and the received input data “1 /
A read-only storage device (14) in which shaping data of 0 "distortion waveform is stored in advance and read out, and the sampling frequency Nf ₀ is input from the phase-locked loop circuit and divided to output n parallel output signals. An address counter (12) to be supplied to the nuclear read-only storage device (14) and a certain fixed number of the input data are serially stored using one of n parallel output signals of the address counter as a clock signal. A shift register (13) for supplying outputs read in parallel to the read-only storage device (14), and the shift register (13)
A selector (1 that selects one clock signal to be supplied to the address counter (12) from the n output signals of the address counter (12).
8) and the speed (f) of the input data is the reference input (f ₀ , 2f
₀ ...) and the range of double change (f ₀ <f ≤ 2f ₀ , 2f ₀ <f ≤ 4f
_The phase-locked loop circuit (1
At the same time as switching the frequency division ratio N of 1), the selector (18)
An external switch (17) for driving a clock signal to change the clock signal supplied to the shift register register (13) by the address counter (12) and the digital data D output from the read-only storage device (14) to an analog signal A. A digital-analog converter circuit (15) for conversion and a smoothing filter (16) that cuts off the harmonic component (Nf ₀ ) generated during D / A conversion and passes a reduced analog signal are received. Each time the change of the speed (f) of the input data exceeds the double change range from the reference input, the multiple (N) of the multiple of the speed at which the input data is sampled is switched, and in each double change range. By making the sampling frequencies equal, the D / A converter (1
The configuration is such that the position of the harmonic Nf ₀ generated at the output of 5) is always constant.

[Action]

According to the configuration of the BTF of the present invention, the clock frequency f ₀ of the received input data is used as the reference input, and N times (= 2 ⁿ times, n
In the phase-locked loop circuit (11) that outputs the output frequency NF ₀ of the integer), when the clock frequency f, which is the speed of the received data, changes from the reference value f ₀ to 2 ^n-2 f ₀ ,
If the change is within each change range up to 2 times, the frequency division ratio N is constant, and each time the change range exceeds 2 times, N is switched by the external switch 17 by 2 ^{1 in} binary number. Therefore, the sampling frequency Nf _0, which is the output frequency of the phase-locked loop circuit (11), is 2 ^n-1 f ₀ to 2 ⁿ f ₀ ,
It is always constant as shown in the column of sampling frequency in the general theory table (FIG. 7). Therefore, the harmonic component generated as the output signal of the D / A conversion (15) appears at the same position. Therefore, the smoothing filter corresponding to the change of the input data transmission rate from f ₀ to 2 ^n-2 f ₀ has a frequency of 2 ^n-2.
flat to f _0, would be the if there is one type that 2 ^n-1 f ₀ or more can be cut.

〔Example〕

FIG. 2 is a block circuit diagram showing the configuration of the BTF of the embodiment of the present invention, in which the same circuits 11 to 16 as the circuits 1 to 6 of the conventional example shown in FIG. The selector 18 is added. The external switch 17 can change the frequency dividing ratio N of the frequency dividing circuit 114 in the phase locked loop circuit 11 by its operation, and the change of the input clock exceeds the double range from each reference value. Sometimes it can be switched. Here, the frequency division ratio N is a binary number N =
Since it is expressed as 2 ⁿ (where n is an integer), the transmission rate of the input data (the frequency of the input clock) has the same change range up to twice that rate.

Voltage-controlled oscillator 113 of phase locked loop circuit 11
Is the output frequency thereof, and the oscillation frequency can be changed in the range from the maximum value which is the sampling frequency of the input data to the frequency of half thereof. In FIGS. 3A to 3C, the selection of the frequency division ratio N values of 8, 4 and 4 when the input clock is changed to three types of f ₀ , 2f ₀ and 1.1f ₀ and the digital Each spectrum characteristic of the output of the analog conversion circuit 15 is shown. Further, FIG. 3 (d) shows a characteristic diagram of the same commonly usable smoothing filter 16 in the case of the double changes f _{0 to} 2f ₀ of the input clocks (a) and (b).

In the explanation example described as the basis of the BTF of the present invention in the section [Means for Solving Problems], the case where the division ratio N is 8 when the input data clock is f _{0 to} 2f ₀ , The output signal of the address counter 12 and the selector 18 when the input data clock is 2f _{0 to} 4f ₀ and the division ratio N is 4.
The selection outputs of the above are already shown in FIGS. 6 (a) and 6 (b).

Now, consider the case where the frequency of the input clock, which is the transmission rate of the input data, changes in the range of f _{0 to} 2f ₀ .

In phase locked loop circuit 11, external switch 17
Thus, the frequency dividing ratio N of the frequency dividing circuit 114 is first set to 2 (= 2 ¹ ) and adjusted so that the output of the voltage controlled oscillator 113 becomes the maximum frequency 2f ₀ at the time of the input data clock f ₀ . Next, the frequency division ratio N (= 2 ⁿ ) is set to N = 8, for example, and the frequencies 8f _{0 to} 16f ₀ are set.
The output clock of is output to the address counter 12. Further, the output of the phase locked loop circuit 11 is input by the address counter 12 which is a frequency divider so that the shift clock for operating the shift register 13 for converting serial input data into parallel data can be received from the address counter 12. , A plurality of four clocks are generated in parallel, and the address counter 12 is controlled by the selector 18 controlled by the external switch 17.
One of the four parallel clocks of the output of 1 is selected according to the phase of the input data and is supplied to the shift register 13.

In (a) of FIG. 3, the data transmission rate (input clock) of the input data is f ₀ , and the sampling is performed at a frequency of 8f _0.
It is the spectral characteristic of the output of the D / A converter 15 when the above is performed. The division ratio in this case is N = 8. In this case,
Unwanted harmonics occur at the positions of 8f ₀ , 16f ₀ ....

In FIG. 3B, the data transmission rate (input clock) of the input data is 2f ₀ , and the sampling is
3 is a spectrum characteristic of an output of the D / A converter 15 when the same frequency 8f ₀ is used. The frequency division ratio in this case is N = 4. In this case, unnecessary harmonics occur at the positions of 8f ₀ , 16f ₀ ... However, the generated bandwidth is expanded.

FIG. 3 (c) shows the spectrum characteristic of the output of the D / A converter 15 when the data transmission rate (input clock) of the input data is 1.1f ₀ and the sampling is performed at the frequency 4.4f _0. Is. The frequency division ratio in this case is N = the same as in (b).
It is 4. In this case, the positions of unnecessary harmonics are 4.4f ₀ , 8.8f
₀ , which is closer to the frequency of the fundamental wave than in the cases of (a) and (b), or the frequency characteristic (2f _{0 in} FIG. 3D).
Can be removed by a smoothing filter that has a flat characteristic up to 4f ₀ ).

Further,此the smoothing filter is effective if the data rate of the input data (input clock) is changed by _{f 0 ~2f 0, 2f 0 ~4f} 0 and twice the range, there is a change in transmission rate But there is no need to replace it. This means that the clock of input data in the explanation example described as the basis of the BTF of the present invention in the section of [Means for solving problems] described above is
The output signal of the address counter 12 and the selective output of the selector 18 when the frequency division ratio N is 8 when f _{0 to} 2f ₀ and when the frequency division ratio N is 4 when the input data clock is 2f _{0 to} 4f ₀ Has already been shown in FIGS. 6 (a) and (b), and has been described in detail.

〔The invention's effect〕

As described above, according to the present invention, even if the transmission rate of the input data changes, the frequency division ratio N is switched by 2 every time the change range of double is exceeded, so that the sampling frequency of the input data is kept constant. ROM output D <A
It is no longer necessary to replace the smoothing filter for preventing harmonics of the converted output each time, and the production and operation effects are extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the BTF of the present invention. FIG. 2 is a block circuit diagram of the BTF of one embodiment of the present invention. FIG. 3 is a block diagram of the digital-analog converter circuit of the embodiment of FIG. Output spectrum characteristic diagram and smoothing filter characteristic diagram FIG. 4 is a BTF block circuit diagram of the conventional example. FIG. 5 is an output spectrum characteristic diagram of the digital-analog conversion circuit of the conventional example of FIG. FIG. 7 is an explanatory view of the operation of an example which is the basis of the BTF of the present invention. FIG. 7 is a table showing items of general operation of the BTF of the present invention. FIG. It is an output connection diagram. In the figure, 1 and 11 are phase locked loop circuits (PLL circuits) 2, 12 are address counters, 3 and 13 are shift registers, 4 and 14 are read-only memory devices (ROM) 5, and 15 are digital / analog conversion circuits ( D / A converter) 6 and 16 are smoothing filters, 17 is an external switch, 18 is a selector, 111 is a phase detection circuit, 112 is a loop filter, and 113 is a voltage controlled oscillator (VCO).

Claims (1)

(57) [Claims] 1. A phase-locked loop circuit (11) for generating and outputting a N times sampling frequency Nf ₀ signal equal to 2 ⁿ times that of a serial input frequency f ₀ received data clock as a reference input. A read-only storage device (14) for storing and reading the distortion waveform shaping data of the received input data "1/0" in advance and the sampling frequency Nf ₀ signal from the phase-locked loop circuit are input and frequency-divided to n. An address counter (12) that supplies parallel output signals as an address to the nuclear read-only storage device (14), and n of the address counter.
A shift register (13) for storing a certain number of the input data in series using one of the parallel output signals as a clock signal and supplying the outputs read in parallel to the read-only storage device (14); 1 to supply to the shift register (13)
A selector (18) for selecting one clock signal from the n output signals of the address counter (12), and the selector (18) each time the speed (f) of the input data exceeds a change range of twice the reference input value. At the same time as switching the frequency division ratio N of the phase-locked loop circuit (11), the selector (18) is driven and the address counter (12) shifts to the shift register register (1
An external switch (17) for changing the clock signal supplied to 3), a digital-analog conversion circuit (15) for converting the digital data D output from the read-only storage device (14) into an analog signal A, and Equipped with a smoothing filter (16) that blocks the harmonic component (Nf ₀ ) generated during D / A conversion and passes a reduced analog signal, the change in the speed of the received input data is in the range of twice that of the reference input. Switching of multiples (N) of how many times the input data is sampled each time the value exceeds, by making the sampling frequency equal in each double change range, the output of the D / A converter (15) A binary transversal filter characterized in that the position of the generated harmonic (Nf ₀ ) is always constant.