JPH05284021A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To speedily obtain the state of holding frequency dividing ratio data corresponding to a first frequency dividing part, which frequency divides the oscillated output signals of a voltage controlled oscillator (VCO), and a second frequency dividing part to frequency divide the oscillated output signals of a reference oscillator while this device is composed by utilizing a PLL. CONSTITUTION:This device is provided with a memory 17 to store the frequency dividing ratio data to be supplied to a data latch part 15, which holds the frequency dividing ratio data to decide the frequency dividing ratio of a frequency dividing part 13 while being attached to the frequency dividing part 13 for frequency dividing the oscillated output signals of a VCO 11, and a data latch part 16 to hold the frequency dividing ratio data for deciding the frequency dividing ratio of a frequency diving part 14 while being attached to the frequency dividing part 14 to frequency divide the oscillated output signals of a reference oscillator 12, and control unit 18 to transmit address designating data for selectively designating the addresses of the memory 17 storing plural frequency dividing ratio data to the memory 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to phase locked
The present invention relates to a frequency synthesizer that generates a signal that switches and changes frequencies while being stabilized by a loop.

[0002]

2. Description of the Related Art A phase locked loop (PLL) is used as a device capable of stably generating a signal that selectively takes a plurality of frequencies set at predetermined frequency intervals. Frequency synthesizers are known. Such a frequency synthesizer is used, for example, as a local oscillating unit that constitutes a mixer unit in the front end of the heterodyne receiver.

A frequency synthesizer using a PLL is
Although various concrete configurations have already been proposed,
In a typical example, a voltage-controlled oscillator that changes an oscillation output signal frequency according to a supplied control voltage and a reference oscillator that stably generates an oscillation output signal of a constant frequency are provided. A first frequency division output signal obtained by frequency division of the output signal with a predetermined frequency division ratio in the first frequency division section, and an oscillation output signal of the reference oscillator by the second frequency division section in the predetermined frequency division section. The second frequency-divided output signal obtained by frequency division is set to have the same frequency, and the first frequency-divided output signal and the second frequency-divided output signal are cross-phase-compared to each other. A control voltage signal based on the comparison output signal is formed, supplied to the voltage controlled oscillator to control the oscillation output signal frequency, and the oscillation output signal of the voltage controlled oscillator is used as the output signal. In such a frequency synthesizer, it has been proposed to digitally set the frequency division ratio in each of the first and second frequency division units. In such a case, the first and second frequency division units are used. Each of the divisions is accompanied by a shift register, and in the shift register, the division ratio data of a predetermined number of bits that determines the division ratio in the first or second division portion is held, and the held division By supplying the ratio data to each of the first and second frequency dividing units, the frequency dividing ratio in each of the first and second frequency dividing units is set.

The frequency of the output signal is switched, that is,
When the frequency of the oscillation output signal of the voltage controlled oscillator is switched, the frequency division ratio in the first frequency division unit is switched, and therefore, the frequency is held in the shift register attached to each of the first frequency division units. The division ratio data is replaced.

When the frequency of the output signal of the frequency synthesizer using such a PLL is switched, the frequency synthesizer goes from the steady operating state before the frequency switching to the steady state after the frequency switching through the transient state related to the frequency switching. It will shift to the operating state. At that time, in order to make the transitional state period short and to shift to the steady operation state after the frequency switching quickly, in the transitional state period, the frequency division ratio in each of the first and second frequency division parts is increased. The first frequency-divided output signal from the first frequency divider and the second frequency-divided from the second frequency divider are set to be larger than the normal operating state after frequency switching and mutual phase comparison is performed. It is known that the respective frequencies of the output signals are increased compared to the steady operating state after the frequency switching. For example, the frequency division ratio of each of the first and second frequency dividers in the transient state period is the first in the steady operation state after frequency switching.
And the frequency division ratio of each of the second frequency division parts,
As a result, the respective frequencies of the first frequency division output signal from the first frequency division unit and the second frequency division output signal from the second frequency division unit in the transient state period are the steady operation after frequency switching. In the state, the frequency of each of the first frequency-divided output signal from the first frequency-divided portion and the second frequency-divided output signal from the second frequency-divided portion is doubled. Then, when the stable operation after the frequency switching is performed under the transient state related to the frequency switching, the frequency division ratio in each of the first and second frequency division units is reduced, and for example, 1 / The frequency of each of the first frequency-divided output signal from the first frequency-dividing unit and the second frequency-divided output signal from the second frequency-dividing unit is, for example, ½.
To a steady operating state after frequency switching.

Therefore, when the frequency of the output signal of the frequency synthesizer using the PLL is switched as described above, the frequency division ratio in each of the first and second frequency division sections is once increased, The respective frequencies of the first divided output signal from the first divider and the second divided output signal from the second divider are increased, and then the frequencies of the first and second dividers are increased. The frequency division ratio in each of them is reduced, and the respective frequencies of the first frequency division output signal from the first frequency division section and the second frequency division output signal from the second frequency division section are reduced.
Therefore, in the shift register associated with each of the first and second frequency division units, the frequency division ratio data is replaced to temporarily increase the frequency division ratio in each of the first and second frequency division units. Then, the division ratio data is replaced twice with the replacement of the division ratio data for reducing the division ratio in each of the first and second frequency division sections thereafter.

[0007]

The frequency division ratio data used in the frequency synthesizer using the PLL as described above is a binary code having a predetermined number of bits, for example, 14 bits to 19 bits. It The frequency division ratio data is supplied to the shift registers associated with the first and second frequency division units, for example, by the control unit sequentially transmitting the frequency division ratio data bit by bit from the least significant bit. The serial method is adopted in which these are sequentially loaded into the shift register, and when the most significant bit is loaded into the shift register, the latch relating to the division ratio data loaded into the shift register by the strobe pulse sent from the control unit. Then, the shift register holds the frequency division ratio data fetched therein.

Therefore, when the division ratio data is taken and held in each of the shift register attached to the first frequency division unit and the shift register attached to the second frequency division unit, for example, From the control unit, see FIG.
As shown in, the period Ts from time t1 to time t2
In, the bit-by-bit transmission of the frequency division ratio data DS to the shift register associated with the first frequency division unit is performed,
In the period Tr from time t3 to time t4 that follows, the frequency division ratio data DR is sent out bit by bit to the shift register associated with the second frequency division unit.
At this time, the periods Ts and Tr are relatively long,
For example, sending 1 bit in the division ratio data DS or the division ratio data DR usually takes about 3 μsec. Therefore, the division ratio data DS and DR having 14 bits to 19 bits are respectively sent. Each of the periods Ts and Tr to be performed is about 42 μsec to 57 μsec.

In particular, as described above, when the frequency of the output signal is switched in the frequency synthesizer using the PLL, the first and second shift registers associated with the first and second frequency dividers respectively. Of the dividing ratio data for temporarily increasing the dividing ratio in each of the frequency dividing parts, and the dividing ratio data for reducing the dividing ratio in each of the first and second dividing parts thereafter. In the case where the division ratio data is replaced twice with the above replacement, the division ratio data having a 14-bit to 19-bit configuration is supplied twice to the shift register. It will be. Therefore, when switching the frequency of the output signal, it takes a relatively long time to transmit the frequency division ratio data from the control unit and to capture the frequency division ratio data transmitted by the shift register. There is an inconvenience that it will not be done promptly.

In view of the above point, the present invention is configured using a PLL, and divides the oscillation output signal of the voltage controlled oscillator by the first frequency divider and the oscillation output signal of the reference oscillator by the first frequency divider. The frequency division ratios of the first and second frequency division units are set based on the frequency division ratio data held for the respective frequency division units. It is an object of the present invention to provide a frequency synthesizer in which the frequency division ratio data holding state for each of the above can be quickly obtained.

[0011]

In order to achieve the above object, in the frequency synthesizer according to the present invention, the first frequency divider for dividing the oscillation output signal of the voltage controlled oscillator has a frequency division ratio. First frequency division ratio data having a configuration of a plurality of bits to be set is supplied, a first data latch unit that holds the supplied first frequency division ratio data and supplies the first frequency division ratio data to the first frequency division unit, and A second frequency division unit for dividing the oscillation output signal of the reference oscillation unit has a second multi-bit configuration for setting the division ratio.
And the second data latch unit for holding the supplied second frequency division ratio data and supplying the second frequency division ratio data to the second frequency division unit. Form a control voltage signal based on the comparison output signal obtained from the phase comparison unit for phase-comparing the frequency division output signal obtained from the second frequency division unit with the frequency division output signal obtained from the second frequency division unit. A control voltage forming unit for controlling the frequency of the oscillation output signal of the voltage controlled oscillator, and a plurality of first division ratio data and second data to be selectively supplied to the first data latch unit. The memory unit in which the second frequency division ratio data to be supplied to the latch unit are stored with corresponding addresses, respectively, and a plurality of the first frequency division ratio data and the second frequency division ratio data in the memory unit are stored. Selectively address multiple addresses stored in each Addressing data to be supplied to the memory unit, and the specified one of the first frequency division ratio data and the second frequency division ratio data is read from the memory unit, and the first and second data latch units are read. It is configured to include an operation control unit that is in a state of being supplied as parallel data.

[0012]

In the frequency synthesizer according to the present invention configured as described above, the oscillation output signal of the voltage controlled oscillator is used as the output signal. The first and second frequency synthesizers are used to determine the frequency of the output signal. When the respective frequency division ratios of the frequency division units are set, the plurality of first frequency division ratio data and second frequency division ratio data in the memory unit are respectively stored from the operation control unit to the memory unit. Addressing data is transmitted that specifies a selected one of the plurality of addresses.
The address designation data is, for example, a binary code having a 5-bit structure and is capable of designating a maximum of 64 different addresses. Then, in the memory unit that has received the address designation data from the operation control unit, from the address designated by the address designation data, the first division ratio data of, for example, 19 bits and 1
The second division ratio data having a 4-bit configuration is read, and the read first division ratio data and the second division ratio data are respectively read as parallel data in the first data latch unit and the first data latch unit. The first data is supplied to and latched by the second data latch unit.
Held by the data latch unit and the second data latch unit. In this way, the first and second frequency division ratio data held in the first and second data latch sections, respectively, are supplied as parallel data to the first and second frequency division sections, respectively, and The frequency division ratio of the frequency division unit is set according to the first frequency division ratio data held by the first data latch unit, and the frequency division ratio of the second frequency division unit is set to the second data latch unit. It is set according to the second frequency division ratio data held by.

Under the above circumstances, the address control data is sent from the operation control section to the memory section bit by bit, for example, by the serial method. However, the address designating data has a 5-bit structure, for example, 19-bit data. The number of bits is extremely small compared to the first frequency division ratio data configured and the second frequency division ratio data configured to have, for example, 14 bits, so that the operation control unit transmits the data relatively. It can be completed in a short time. Further, the transmission of the first and second frequency division ratio data from the memory unit to the first and second data latch units is carried out with each of the first and second frequency division ratio data being parallel data. Therefore, it is performed in an extremely short time. Therefore, it is possible to quickly obtain the holding state of the frequency division ratio data that determines the frequency division ratio for each of the first and second frequency division units by the first and second data latch units.

[0014]

FIG. 1 shows an example of a frequency synthesizer according to the present invention. In this example, a voltage controlled oscillator (VC
O) 11 and a reference oscillator 12 are provided. The voltage controlled oscillator 11 is assumed to have 32 different oscillation frequencies for every 300 kHz in the frequency range of 1.5 to 1.5093 GHz, while the reference oscillator 12 is
For example, it is assumed to have a constant oscillation frequency of 120 MHz. The frequency obtained from the voltage controlled oscillator 11 is, for example, 1.5 to 1.5093 GHz.
The oscillation output signal SS that is within the frequency range of 10 is supplied to the frequency dividing unit 13, and the oscillation output signal SR that is obtained from the reference oscillator 12 and has a frequency of, for example, 120 MHz is Is supplied to.

The frequency division units 13 and 14 are accompanied by data latch units 15 and 16, respectively, and the data latch units 15 and 16 have frequency division ratio data DS and D from the memory 17, respectively.
R is supplied. The data latch unit 15 latches and holds the supplied frequency division ratio data DS, and the data latch unit 15 holds the frequency division ratio data DS.
The frequency division ratio of the frequency division unit 13 is set according to the frequency division ratio data DS. In addition, the data latch unit 1
6 latches and holds the supplied frequency division ratio data DR, supplies it to the frequency division unit 14, and the frequency division ratio of the frequency division unit 14 is set according to the frequency division ratio data DR.

The frequency division ratio data DS is, for example, a 19-bit binary code, and the frequency division ratio data DR is
For example, it is a 14-bit binary code. The memory has 32 different contents in advance and the first
Each of the division ratio data DS forming the group of is stored in 32 addresses together with one same division ratio data DR, and the other 32 different contents are mutually different. Each of the frequency division ratio data DS forming a group has the same content as that of the above-described one frequency division ratio data D.
It is assumed that they are stored in the other 32 addresses together with R.

That is, since a total of 64 frequency division ratio data DS are stored in the memory 17 together with the frequency division ratio data DR, the frequency division ratio data forming 32 first groups are stored. There is a correspondence relationship between each of the DSs and each of the division ratio data DS forming the 32nd second groups. For example, the division ratio data D forming the second group
Each S is selected to be doubled under the decimal system with respect to one of the frequency division ratio data DS forming the corresponding first group. Further, the frequency division ratio data DR that accompanies each of the frequency division ratio data DS that forms the second group is the frequency division ratio data D that forms the first group.
The frequency division ratio data DR that accompanies each S is doubled under the decimal system.

The control unit 18 stores in the memory 17 addressing data DA for selectively designating 64 addresses in which the 64 division ratio data DS in the memory 17 are stored together with the division ratio data DR. Then, the frequency division ratio data DS and the frequency division ratio data DR stored in the address designated by the address designation data DA are read out from the memory 17, and the read frequency division ratio data DS is data latched. While being supplied to the unit 15 and held by the data latch unit 15, the read division ratio data DR is supplied to the data latch unit 16 and held by the data latch unit 16. At that time, each of the frequency division ratio data DS and the frequency division ratio data DR is
The frequency division ratio data DS read out from the memory 17 as parallel data is held by the data latch unit 15,
Further, the data latch unit 15 supplies the frequency division ratio data DR to the frequency division unit 13 as parallel data, and the frequency division ratio data DR is held by the data latch unit 16 and is further supplied from the data latch unit 16 to the frequency division unit 14 as parallel data. To be done. The addressing data DA sent from the control unit 18 is, for example, a binary code having a 5-bit structure.

The frequency division unit 13 divides the oscillation output signal SS from the voltage controlled oscillator 11 with a frequency division ratio according to the frequency division ratio data DS held by the data latch unit 15 to obtain a frequency division. The output signal SQ is obtained and supplied to one input end of the phase comparison unit 19, and the frequency division unit 14 outputs the oscillation output signal SR from the reference oscillator 12.
However, a frequency division output signal SQR obtained by frequency division with a frequency division ratio according to the frequency division ratio data DR held by the data latch unit 16 is obtained, and the divided output signal SQR is input to the other input terminal of the phase comparison unit 19. Supplied. The frequency-divided output signal SQ obtained from the frequency dividing unit 13 and the frequency-divided output signal SQR obtained from the frequency dividing unit 14 are set so as to have the same frequency. The relative phase comparison between SQ and the frequency-divided output signal SQR is performed, and the comparison output signal CC is obtained. The comparison output signal CC obtained from the phase comparison unit 19 is supplied to a low pass filter (LPF) 20, and the low pass filter 20 forms a control voltage signal VC based on the comparison output signal CC and outputs it as a voltage. It is supplied to the control end of the controlled oscillator 11. As a result, the oscillation frequency of the voltage controlled oscillator 11 is controlled according to the control voltage signal VC, and the oscillation output signal SS having the oscillation frequency controlled by the control voltage signal VC is derived as an output signal. To be done. Thus, in the example shown in FIG. 1, the PLL including the voltage controlled oscillator 11 is formed.

Under such a condition, when the frequency division ratios of the frequency division units 13 and 14 are initially set, the control unit 18 outputs, for example, as shown in FIG. In the period Ta up to tb, the frequency division ratio data D forming the above-mentioned second group in the memory 17
Addressing data DA designating a specific one of the 32 addresses in which S is stored is sent to the memory 17. The addressing data DA is sent out serially bit by bit in a serial manner. However, since the addressing data DA is composed of, for example, 5 bits, the period Ta required for the sending out is The period Ts mentioned above
Alternatively, it is remarkably shorter than the period Tr.

Then, from the memory 17, from the address designated by the address designation data DA from the control unit 18, for example, "51,00 in decimal system".
0 ”, which is a 19-bit division ratio data DS (0
001100011100111000), for example,
Frequency division ratio data DR (0011111010000) of 14 bits, which represents "4,000" in decimal notation
0) is read out, and the frequency division ratio data DS and the frequency division ratio data DR are latched and held by the data latch units 15 and 16, respectively. As a result, the frequency division ratio of the frequency division unit 13 indicates the frequency division ratio data D representing "51,000".
It is set to "1 / 51,000" based on S, and the frequency division ratio of the frequency division unit 14 is "1 / 4,000" based on the frequency division ratio data DR representing "4,000". Is set to. In such a case, the second memory in the memory 17
3 in which the division ratio data DS forming the group of
The two addresses have "4.00" for each of them.
The division ratio data DR having a 14-bit structure representing “0” is
It is stored in association with the frequency division ratio data DS.

The frequency of the oscillation output signal SR obtained from the reference oscillator 12 is 120 MHz as described above, and the frequency of the oscillation output signal SS obtained from the voltage controlled oscillator 11 at this time is 1.53 GHz. Selected. As a result, the frequency division output signal SQR obtained from the frequency division unit 14 is set to have a frequency of 120,000 / 4,000 = 30 kHz, and the frequency division output signal SQ obtained from the frequency division unit 13 is set. Also, the frequency shall be set to 1530,000 / 51,000 = 30 kHz. Therefore, the frequency division output signal SQ obtained from the frequency division section 13 and the frequency division output signal S obtained from the frequency division section 14 in which the mutual phase comparison is performed in the phase comparison section 19
The frequency of each QR is set to 30 kHz, and under this condition, the voltage-controlled oscillator 1 that is used as an output signal.
The oscillation output signal SS of No. 1 is stabilized by setting its frequency to 1.53 GHz.

In this way, the oscillation frequency of the voltage controlled oscillator 11 is switched under the condition that the oscillation output signal SS from the voltage controlled oscillator 11 as the output signal has its frequency set to 1.53 GHz. , For example, the oscillation frequency of the voltage controlled oscillator 11 is 1.53 GHz to 1.5 GH
When the frequency of the oscillation output signal SS from the voltage controlled oscillator 11 is switched to z from 1.53 GHz to 1.5 GHz, the control unit 18
First, as shown in FIG. 3, in the period Tc from the time point tc to the time point td, 10 of the 32 addresses in which the frequency division ratio data DS forming the above-mentioned first group in the memory 17 are stored. Dividing ratio data DS (000011) of 19-bit structure representing "25,000" in the base system
The first addressing data DA (represented as DA1) designating the stored data (0000110101000) is sent to the memory 17. The addressing data DA1 is also sent out serially bit by bit in a serial manner, but the period Tc required for the sending out is remarkably shorter than the period Ts or the period Tr.

Then, from the memory 17, from the address designated by the first addressing data DA1 from the control unit 18, "25,00" under the decimal system.
"0" representing the division ratio data DS of 19-bit configuration,
For example, representing "2,000" in decimal notation 1
Frequency division ratio data DR of 4-bit configuration (000111110
10000) and the frequency division ratio data DS and frequency division ratio data DR are newly latched and held by the data latch units 15 and 16, respectively. As a result, the frequency division ratio of the frequency division unit 13 is "1 / 25,000" based on the frequency division ratio data DS representing "25,000".
In addition, the frequency division ratio of the frequency division unit 14 is increased to “2,000
0 ”based on the frequency division ratio data DR
2,000 ". In such a case, the frequency division ratio data D forming the first group in the memory 17
In each of the 32 addresses in which S is stored, the division ratio data DR of 14 bits representing “2,000” is stored in association with the division ratio data DS in each of them. become.

At this time, the frequency division output signal SQR obtained from the frequency division unit 14 is set to have a frequency of 120,000 / 2,000 = 60 kHz, and the frequency division output signal SQR obtained from the frequency division unit 13 is used. The output signal SQ also has a frequency of 1,500,000 / 25,000 = 60 kHz. Therefore, the frequency division output signal SQ obtained from the frequency division section 13 and the frequency division output signal S obtained from the frequency division section 14 in which the mutual phase comparison is performed in the phase comparison section 19
The frequency of each of the QRs is increased to 60 kHz, and the oscillation frequency is set to 1 when the phase comparison unit 19 quickly performs the mutual phase comparison between the divided output signal SQ and the divided output signal SQR. The operation of the voltage controlled oscillator 11 that can be switched from 0.53 GHz to 1.5 GHz is stabilized.

As described above, in the transient state period related to the switching of the oscillation frequency of the voltage controlled oscillator 11, the frequency division output signal SQ and the frequency division unit obtained from the frequency division unit 13 in which the mutual phase comparison is performed in the phase comparison unit 19 are performed. By increasing the frequency of each of the divided output signals SQR obtained from 14 to 60 kHz, the operation under the condition that the oscillation frequency of the voltage controlled oscillator 11 is switched from 1.53 GHz to 1.5 GHz is quickly stabilized, Therefore, the voltage controlled oscillator 1
The transient state period associated with switching the oscillation frequency of 1 is shortened.

Then, after the operation of the voltage controlled oscillator 11 whose oscillation frequency is switched from 1.53 GHz to 1.5 GHz is stabilized, the control unit 18 causes the time point te to the time point tf as shown in FIG. Of the 32 addresses in which the division ratio data DS forming the second group in the memory 17 is stored in the period Te of 10
19-bit division ratio data DS (00011000011010) representing "50,000" in the base system
The second addressing data DA (represented as DA2) for designating the data stored in the memory 1
7 is sent. The addressing data DA2 is also sent out serially bit by bit in a serial manner, but the period Te required for the sending out is remarkably shorter than the period Ts or the period Tr.

Then, from the memory 17, from the address designated by the second addressing data DA2 from the control unit 18, under the decimal system, "50,00".
"0" representing the division ratio data DS of 19-bit configuration,
The 14-bit frequency division ratio data DR representing "4,000" is read under the decimal system, and the frequency division ratio data DS and the frequency division ratio data DR are respectively read in the data latch unit 15 and It is newly latched and held by 16.
As a result, the frequency division ratio of the frequency division unit 13 is "50,000".
Based on the frequency division ratio data DS representing
000 ", that is, reduced to 1/2, and the frequency divider 1
The frequency division ratio of 4 is "1 / 4,000", that is, 1/2 based on the frequency division ratio data DR representing "4,000".
Is reduced to.

As a result, the frequency division output signal SQR obtained from the frequency division unit 14 is set to have a frequency of 120,000 / 4,000 = 30 kHz, and the frequency division output signal SQR obtained from the frequency division unit 13 is obtained. The output signal SQ also has a frequency of 1,500,000 / 50,000 = 30 kHz. Therefore, the frequency division output signal SQ obtained from the frequency division section 13 and the frequency division output signal S obtained from the frequency division section 14 in which the mutual phase comparison is performed in the phase comparison section 19
The frequency of each of the QRs is reduced to 60kHz, and the oscillation frequency is changed while the phase comparison unit 19 stably performs the mutual phase comparison between the frequency-divided output signal SQ and the frequency-divided output signal SQR. Voltage controlled oscillator 1 with 1.5 GHz
1 is returned to the steady operation state in which the operation is stabilized.

In the above example, the frequency division ratio in each of the frequency division units 13 and 14 is reduced to ½ when returning from the transient state to the steady operation state. The frequency synthesizer according to the present invention is not limited to such an example. In another example of the frequency synthesizer according to the present invention, the frequency dividers 13 and 14 perform frequency division in order to return from a transient state to a steady operation state. Ratio is 1 /
2 ^x (x is a positive integer of 2 or more) is adapted to be reduced doubled.

[0031]

As is apparent from the above description, in the frequency synthesizer according to the present invention, the oscillation output signal of the voltage controlled oscillator is used as the output signal, and the first and the second signals are used to determine the frequency of the output signal. When the respective frequency division ratios of the second frequency division unit are set, the plurality of first frequency division ratio data and second frequency division ratio data in the memory unit are transferred from the operation control unit to the memory unit. Addressing data designating a selected one of the plurality of stored addresses is transmitted, whereby the first division ratio data and the first dividing ratio data are transmitted from the address designated by the addressing data in the memory unit. And the frequency division ratio data of 2 are read and held in the first data latch unit and the second data latch unit, respectively, and the frequency division ratio of the first frequency division unit is held by the first data latch unit. Had the first Is set according to the division ratio data,
Further, since the frequency division ratio of the second frequency division unit is set according to the second frequency division ratio data held by the second data latch unit, the first frequency division unit and the second frequency division unit are respectively set. It is possible to quickly obtain the holding state of the frequency division ratio data that determines the frequency division ratio by the first and second data latch units.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a frequency synthesizer according to the present invention.

FIG. 2 is a time chart used for explaining the operation of the example shown in FIG.

FIG. 3 is a time chart used to explain the operation of the example shown in FIG.

FIG. 4 is a time chart provided for explaining the operation of a conventionally proposed frequency synthesizer.

[Explanation of symbols]

 11 Voltage Controlled Oscillator 12 Reference Oscillator 13, 14 Frequency Division Section 15, 16 Data Latch Section 17 Memory 18 Control Unit 19 Phase Comparison Section 20 Low Pass Filter

Claims (1)

[Claims] 1. A voltage controlled oscillator, a first frequency divider that divides an oscillation output signal of the voltage controlled oscillator, and a multi-bit configuration that sets a frequency division ratio of the first frequency divider. A first data latch unit supplied with the first frequency division ratio data, holding the supplied first frequency division ratio data and supplying the first frequency division ratio data to the first frequency division unit, a reference oscillation unit, and the reference A second frequency division unit for dividing the oscillation output signal of the oscillation unit and a second frequency division ratio data of a plurality of bits for setting the frequency division ratio of the second frequency division unit are supplied and supplied. A second data latch unit that holds the second frequency division ratio data and supplies the second frequency division ratio data to the second frequency division unit; a frequency division output signal obtained from the first frequency division unit;
Of the frequency division output signal obtained from the frequency division unit, and a control voltage signal based on the comparison output signal obtained from the phase comparison unit is formed, and the control voltage signal is generated from the voltage control oscillation unit. A control voltage forming unit for controlling the frequency of the oscillation output signal of the voltage controlled oscillator, and a plurality of first frequency division ratio data to be selectively supplied to the first data latch unit. A memory unit in which the second frequency division ratio data to be supplied to the second data latch unit are stored with corresponding addresses, and the plurality of first frequency division ratio data and the second frequency division ratio data in the memory unit are stored. The addressing data for selectively designating the address in which each of the frequency division ratio data is stored is supplied to the memory unit, and the first frequency division ratio data and the second frequency division ratio data are supplied from the memory unit. The one specified is Is Desa see frequency synthesizer constructed and a state and makes the operation control unit which is supplied to the first and second data latch section above.