JPH05283945A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption by stopping the current from the constant current source or the like when the current mirror circuit is out of operation. CONSTITUTION:When VDD potential is applied to a control terminal 120, a switch 30 is turned off and a switch 40 is turned on. When the current flows from an IREF terminal 110, the current flows through a transistor 10. According to the current flow, the electric potential is generated in the control terminal of the transistor. The same potential with the control terminal of the transistor 10 is applied to the control terminal of the transistor 20, and the current flows to the transistor 20. When the GND potential is applied to a control terminal 120, the switch 40 cuts the current of the IREF terminal and the switch 30 applies the VDD potential to the gate of the operating transistor 10 and to the gate of the reference transistor 20. The current of both transistors is cut, resulting in reducing the consumption current to zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit having a current mirror structure.

[0002]

2. Description of the Related Art In a conventional current mirror circuit, as shown in FIG. 3, for example, in a circuit which receives a current from an IREF terminal 110, a VDD terminal 100 is used.
A current always flows between the IREF terminal 110 and the IREF terminal 110 through the reference transistor 10, and the control current of the reference transistor 10 is determined by the flowing current, and the potential is connected to the control terminal of the operating transistor 20 and the operating transistor 20 is turned on. Always consuming current.

[0003]

However, in the above-mentioned conventional technique, even when the current mirror circuit is not operated, the current always continues to flow in the current mirror circuit, and extra current is consumed. Also, even if the IREF terminal 11
Stop the operation of the current source that supplies current to 0, or I
Even if the REF terminal 110 is set to OPEN or the like, the potential of the current control terminal of the transistor does not always reach a potential at which the transistor is turned off, and there is a problem that current flows. Therefore, the present invention solves such a problem, and an object thereof is to have a function of stopping current from a current source or the like to reduce current consumption when the current mirror circuit is not operated. It is to provide a current mirror circuit characterized by the above.

[0004]

Means for Solving the Problems (1) First transistor, second transistor, first electrical switching means, second
Electrical switching means, and the current control terminals of the first and second transistors, and the first and second
Is connected to one terminal A of the first electrical switching means and one current terminal C of the first transistor, and the other terminal B of the first electrical switching means is connected to the first and second terminals. The other current terminal D of the transistor is connected, and the operations of the first and second electrical switching means are reversed.

(2) It has a first transistor, a second transistor, a first electrical switching means, and a second electrical switching means, and the current control terminals of the first and second transistors and the first and second transistors. One terminal A of the one and the second electrical switching means is connected, one current terminal C of the first transistor and the other terminal B of the second electrical switching means are connected, and The other terminal B of the first electrical switching means and the other current output terminals D of the first and second transistors are connected, and the operation of the first and second electrical switching means is It is the opposite.

[0006]

1 is a circuit diagram showing an embodiment of a MOS type voltage generating circuit constructed by using a current mirror circuit according to the first aspect of the present invention. The transistors 10 and 20 form a current mirror circuit. 10 is a reference transistor (PM
OS), 20 is an operating transistor (PMOS), 30 and 40 are switch circuits (composed of transmission gates), 50 is a resistor, 100 is a VDD power input terminal, 110 is a constant current input terminal (hereinafter referred to as IREF terminal), 120 is a control terminal and 140 is a voltage output terminal.

When an H level electric potential (hereinafter referred to as H electric potential) is applied to the control terminal 120, the switch circuit 30 becomes O.
The FF is performed and the VDD terminal 100 and the gate of the transistor 10 are electrically cut. Also, the switch circuit 40 is turned on.
Then, the constant current supplied from the IREF terminal 110 flows between the drain of the reference transistor 10 and the source connected to the VDD terminal 100, and a constant potential corresponding to the constant current is generated in the drain of the transistor 10 and the transistor 10 , 20 gate potential. In the case of a MOS transistor, the current is proportional to the channel width (W) if the gate voltage and the channel length (L) are constant. When the channel width of the reference transistor 10 is W1, the operating transistor 2
When the channel length of 0 is αW1, and the external constant current is I, the current of αI flows through the operating transistor 20. Therefore, the current αI flows through the resistor R50, and the OUT terminal 1
A voltage αIR is generated at 40.

With the above configuration, the operating transistor 20
By arbitrarily setting the channel width of the MOS type transistor in a circuit manner, it operates as a voltage generator that outputs an arbitrary voltage to the OUT terminal 140.

In normal operation, IREF terminal 1
A constant current is always supplied from the reference transistor 10
And the operating transistor 20 always keeps flowing a constant current,
In the conventional circuit as shown in FIG. 3 which does not have the constant current control circuit of the present invention, current is consumed even when the circuit is not used.

However, in this embodiment, the switch circuit 30 is turned on by applying the L level potential (hereinafter referred to as the L potential) to the control terminal, and the switch circuit 4 is turned on.
When 0 is turned off, the H potential is applied to the gate of the reference transistor 10 and the reference transistor 10 is turned off. Therefore, IR
The constant current supplied from the EF terminal is cut off, and the gates of the reference transistor 10 and the operating transistor 20 are set to the H potential by the switch 30, so that no current flows.

FIG. 2 is a circuit diagram showing another embodiment of the MOS voltage generating circuit constructed by using the current mirror circuit of the second invention. The transistors 10 and 20 form a current mirror circuit via a switch 40. 10 is a reference transistor (PMOS), 20 is an operating transistor (PMOS), 30 and 40 are switch circuits (composed of transmission gates), 50 is a resistor, 100 is a VDD power input terminal, 110 is an IREF terminal (constant current). Input terminal), 120 is a control terminal, 1
40 is a voltage output terminal.

When an H potential is applied to the control terminal, FIG.
It operates as a voltage generator that outputs an arbitrary voltage as in the embodiment shown in FIG. In the normal operation, a constant current is always supplied from the IREF terminal 110, the reference transistor 10 and the operating transistor 20 always keep the constant current flowing, and a conventional constant current control circuit as shown in FIG. 3 is not provided. In the circuit of, the current was consumed even when the circuit was not used.

However, in the present embodiment, by applying the L potential to the control terminal 120, the switch circuit 30 is turned on and the switch circuit 40 is turned off, so that the reference transistor 10 and the operating transistor 2 are turned on.
Since the H potential is applied to the gate of 0, both transistors are turned off, the constant current supplied from the IREF terminal is cut, and no current flows in the reference transistor 10 and the operating transistor 20. Compared with the embodiment shown in FIG. 1, since there is no switch in the path through which the constant current flows, there is the effect that the potential fluctuation due to the switch is reduced. ..

FIG. 4 is a circuit diagram showing an embodiment of a CMOS 4-bit D / A converter constructed by using the current mirror circuit of the first invention. Transistors 10, 21-2
4 has a current mirror structure. 10 is a reference transistor (PMOS), 21 to 24 are operating transistors (PMOS), 30 and 40 are switch circuits (transmission gates), 70 to 77 are signal switch transistors (PMOS), 60 is an inverter, 50 is a resistor, and 100 is VDD power input terminal, 110 IREF terminal (constant current input terminal), 120 control terminal, 1
30 is a GND terminal, 141 is an analog output terminal, is 15
0 to 153 are digital data input terminals.

When an H potential is applied to the control terminal 120, the switch circuit 30 (VDD side transmission gate) is turned off, the switch circuit 40 (IREF side transmission gate) is turned on, and the IREF terminal 110 is turned on.
The constant current supplied from the reference transistor 10 flows,
The gate potential is determined, and the constant current results in a constant voltage. The constant voltage is supplied to the operation transistors 21 to 24.

A digital data signal is input to the data input terminal 15
The present circuit operates normally by being applied to 0 to 153. The least significant bit D0 of the 4 bits of data is assigned to the D0 data input terminal 150, the upper bit D1 is the D1 data input terminal 151, and the higher bit D2 is the D2 data input terminal 152. The most significant bit D3 is applied to the D3 data input terminal 153.

Taking the D0 bit as an example, when 0 (L potential) is applied to the D0 data input terminal 150, the L potential is applied to the gate of the D0 signal switch transistor 70 to turn it ON.
However, the gate of the D0 signal switch transistor 71 has H
The constant current output from the operating transistor 21 whose potential is applied and which is turned off and whose gate is supplied with a constant voltage is supplied to the GND terminal 130 via the D0 signal switch transistor 70.
As a result, the potential of the OUT terminal 140 becomes GND due to the resistor 50 connected to GND. Also, D0
When 1 (H potential) is applied to the data input terminal 150, 0
Contrary to when (L potential) is applied, the D0 signal switch transistor 70 is turned off and the D0 signal switch transistor 71 is turned on. Therefore, the constant current output from the operation transistor 21 flows through the resistor 50, and Ohm's law is applied. As a result, a certain potential is output to the OUT terminal 140. The same operation is performed for other bits.

The weight of each bit is D0 = 1, D1 =
Since 2, D2 = 4 and D3 = 8, assuming that the current capacity of the operating transistor 21 at D0 is β, the β of the operating transistors of other bits are
1 is 2β, D2 is 4β, and D3 is 8β. or,
Signal switch transistors 70, 71 corresponding to each
To 76 and 77 are the same as β of the respective operating transistors 21 to 24. With the above configuration, by setting the resistance 50 and β of each transistor arbitrarily, it operates as a D / A converter that outputs an arbitrary voltage.

In normal operation, IREF terminal 1
10 always supplies a current, the reference transistor 10 and the operation transistors 21 to 24 always supply a constant current, and the conventional circuit without the constant current control circuit of the present invention consumes the current even when the circuit is not used. It was dead. Even if the IREF terminal 110 is set to OPEN, the gate potentials of the operation transistors 21 to 24 do not become the potentials to turn off the operation transistors 21 to 24, and the operation transistors 21 to 24 consume current.

However, in this embodiment, by applying the L potential to the control terminal 10, the transmission gate 30 is turned on and the transmission gate 40 is turned off, so that the gates of the reference transistor 10 and the operating transistors 21 to 24 are applied. H potential is applied and turns off. Therefore, the constant current supplied from the IREF terminal 110 is cut, and its potential becomes an appropriate potential depending on the structure of the constant current source. In addition, no matter what data is input, the operation transistors 21 to 24 are turned on.
No current flows because it is FF.

As described above, in the present embodiment, by supplying the L potential to the control terminal, it is possible to reduce the current consumption due to the current flowing to the IREF terminal to zero.

FIG. 5 is a circuit diagram showing an embodiment of a CMOS 4-bit D / A converter constituted by using the current mirror circuit of the second invention. The D / A converter having the same configuration as that of the embodiment shown in FIG. 4 is different from the D / A converter in that the current mirror circuit of the second aspect of the present invention is used as the current mirror circuit. Similar to the embodiment shown in FIG. 4, the operation of the D / A converter can be stopped and the current consumption can be suppressed by the same procedure as that of the embodiment shown in FIG.

The present invention also relates to an NMOS transistor,
It is needless to say that it can be configured by using a transistor other than MOS and can be used for other than the voltage generating circuit and the D / A converter.

[0024]

As described above, according to the present invention, the current can be cut off when the operation of the circuit is not required, so that the current consumption can be suppressed. For example, in a personal computer or the like, when it is desired to stop only the screen display while the CPU is operating, the operation of the D / A converter can be stopped to prevent unnecessary current consumption. Also, C
This is effective in reducing current consumption when the D / A converter is used or not used, as in a system that can use both the RT and the flat panel. Reducing the current consumption also has the effect of facilitating heat dissipation in the case of an IC or the like. In the conventional circuit, the IR
Since the EF terminal is directly connected to the input terminal of the reference transistor, static electricity has been found in the case of a transistor such as a MOS type transistor. However, in the present invention, the switch element is inserted in the middle of the transistor, so that the effect of being strong against static electricity is also obtained. Have.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a MOS type voltage generation circuit configured by using a current mirror circuit of the first present invention.

FIG. 2 is a circuit diagram showing another embodiment of a MOS voltage generating circuit configured by using the current mirror circuit of the second present invention.

FIG. 3 is an M formed by using a conventional current mirror circuit.
It is a circuit diagram which shows an OS voltage generation circuit.

FIG. 4 is a circuit diagram showing an embodiment of a CMOS 4-bit D / A converter configured by using the current mirror circuit of the first present invention.

FIG. 5 is a circuit diagram showing an embodiment of a CMOS 4-bit D / A converter configured by using the current mirror circuit of the second present invention.

[Explanation of symbols]

 10 reference constant current transistor 20 operation constant current transistor 21 D0 operation transistor (1β) 22 D1 operation transistor (2β) 23 D2 operation transistor (4β) 24 D3 operation transistor (8β) 30 switch circuit (VDD side) 40 switch circuit (IREF) Side) 50 resistor 60 inverter 70 D0 negative signal switch circuit 71 D0 positive signal switch circuit 72 D1 negative signal switch circuit 73 D1 positive signal switch circuit 74 D2 negative signal switch circuit 75 D2 positive signal switch circuit 76 D3 negative signal switch circuit 77 D3 Positive signal switch circuit 100 VDD terminal 110 IREF terminal 120 Control terminal 130 GND terminal 140 Voltage output terminal 141 Analog output terminal 150 D0 data input terminal 151 D1 data input terminal 152 D2 data input terminal 153 D3 data input terminal

Claims (2)

[Claims] 1. A first transistor, a second transistor, a first electrical switching means, and a second electrical switching means, and the current control terminals A of the first and second transistors and the current control terminal A of the first and second transistors. One current terminal B of the first transistor,
One terminal D of the first and second electrical switching means is connected, and the other terminal E of the first electrical switching means and the other current of the first and second transistors are connected. A current mirror circuit, wherein a terminal C is connected and the operations of the first and second electrical switching means are reversed. 2. A first transistor, a second transistor, a first electrical switching means, a second electrical switching means, and the current control terminal A of the first and second transistors and the One terminal D of the first and second electrical switching means is connected, one current terminal B of the first transistor and the other terminal E of the second electrical switching means are connected, The other terminal E of the first electrical switching means and the other current output terminals C of the first and second transistors are connected, and the operation of the first and second electrical switching means Is a reverse current mirror circuit.